- fixed bug introduced in 1.6 which caused MP structures to be overwritten
by BCC generated data. This was pointed out by Tom Lindström <tom@debet.shh.fi>, and I took his suggestion of moving the MP structures to the end of the file.
This commit is contained in:
Bryce Denney
parent
e8d89eb7eb
commit
981fb8f55b
@ -256,7 +256,7 @@ static void keyboard_panic();
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static void boot_failure_msg();
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static void nmi_handler_msg();
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static void print_bios_banner();
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static char bios_version_string[] = "BIOS Version is $Id: rombios.c,v 1.10 2001-05-31 20:36:05 bdenney Exp $";
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static char bios_version_string[] = "BIOS Version is $Id: rombios.c,v 1.11 2001-06-07 12:29:22 bdenney Exp $";
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#define DEBUG_ROMBIOS 0
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@ -3919,194 +3919,6 @@ int76_handler:
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pop ax
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iret
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.org 0xd000
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// For documentation of this config structure, look on developer.intel.com and
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// search for multiprocessor specification. Note that when you change anything
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// you must update the checksum (a pain!). It would be better to construct this
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// with C structures, or at least fill in the checksum automatically.
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#if (BX_SMP_PROCESSORS==1)
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// no structure necessary.
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#elif (BX_SMP_PROCESSORS==2)
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// define the Intel MP Configuration Structure for 2 processors at
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// APIC ID 0,1. I/O APIC at ID=2.
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mp_config_table:
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db 0x50, 0x43, 0x4d, 0x50 ;; "PCMP" signature
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dw (mp_config_end-mp_config_table) ;; table length
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db 4 ;; spec rev
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db 0xdd ;; checksum
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db 0x42, 0x42, 0x44, 0x43, 0x50, 0x55, 0x20, 0x20 ;; OEM id = "BBDCPU "
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db 0x30, 0x2e, 0x31, 0x20 ;; vendor id = "0.1 "
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db 0x20, 0x20, 0x20, 0x20
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db 0x20, 0x20, 0x20, 0x20
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dw 0,0 ;; oem table ptr
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dw 0 ;; oem table size
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dw 3 ;; entry count
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dw 0x0000, 0xfee0 ;; memory mapped address of local APIC
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dw 0 ;; extended table length
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db 0 ;; extended table checksum
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db 0 ;; reserved
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mp_config_proc0:
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db 0 ;; entry type=processor
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db 0 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 3 ;; cpu flags: enabled
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_proc1:
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db 0 ;; entry type=processor
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db 1 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 1 ;; cpu flags: enabled
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_isa_bus:
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db 1 ;; entry type=bus
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db 0 ;; bus ID
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db 0x49, 0x53, 0x41, 0x20, 0x20, 0x20 ;; bus type="ISA "
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mp_config_ioapic:
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db 2 ;; entry type=I/O APIC
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db 2 ;; apic id=2. linux will set.
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db 0x11 ;; I/O APIC version number
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db 1 ;; flags=1=enabled
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dw 0x0000, 0xfec0 ;; memory mapped address of I/O APIC
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mp_config_irqs:
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db 3 ;; entry type=I/O interrupt
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db 0 ;; interrupt type=vectored interrupt
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db 0,0 ;; flags po=0, el=0 (linux uses as default)
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db 0 ;; source bus ID is ISA
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db 0 ;; source bus IRQ
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db 2 ;; destination I/O APIC ID
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db 0 ;; destination I/O APIC interrrupt in
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;; repeat pattern for interrupts 0-15
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db 3,0,0,0,0,1,2,1
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db 3,0,0,0,0,2,2,2
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db 3,0,0,0,0,3,2,3
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db 3,0,0,0,0,4,2,4
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db 3,0,0,0,0,5,2,5
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db 3,0,0,0,0,6,2,6
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db 3,0,0,0,0,7,2,7
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db 3,0,0,0,0,8,2,8
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db 3,0,0,0,0,9,2,9
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db 3,0,0,0,0,10,2,10
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db 3,0,0,0,0,11,2,11
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db 3,0,0,0,0,12,2,12
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db 3,0,0,0,0,13,2,13
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db 3,0,0,0,0,14,2,14
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db 3,0,0,0,0,15,2,15
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#elif (BX_SMP_PROCESSORS==4)
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// define the Intel MP Configuration Structure for 4 processors at
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// APIC ID 0,1,2,3. I/O APIC at ID=4.
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mp_config_table:
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db 0x50, 0x43, 0x4d, 0x50 ;; "PCMP" signature
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dw (mp_config_end-mp_config_table) ;; table length
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db 4 ;; spec rev
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db 0x55 ;; checksum
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db 0x42, 0x42, 0x44, 0x43, 0x50, 0x55, 0x20, 0x20 ;; OEM id = "BBDCPU "
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db 0x30, 0x2e, 0x31, 0x20 ;; vendor id = "0.1 "
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db 0x20, 0x20, 0x20, 0x20
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db 0x20, 0x20, 0x20, 0x20
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dw 0,0 ;; oem table ptr
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dw 0 ;; oem table size
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dw 5 ;; entry count
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dw 0x0000, 0xfee0 ;; memory mapped address of local APIC
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dw 0 ;; extended table length
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db 0 ;; extended table checksum
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db 0 ;; reserved
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mp_config_proc0:
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db 0 ;; entry type=processor
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db 0 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 1 ;; cpu flags: enabled
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_proc1:
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db 0 ;; entry type=processor
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db 1 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 1 ;; cpu flags: enabled
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_proc2:
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db 0 ;; entry type=processor
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db 2 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 3 ;; cpu flags: enabled, bootstrap processor
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_proc3:
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db 0 ;; entry type=processor
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db 3 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 1 ;; cpu flags: enabled
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_isa_bus:
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db 1 ;; entry type=bus
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db 0 ;; bus ID
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db 0x49, 0x53, 0x41, 0x20, 0x20, 0x20 ;; bus type="ISA "
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mp_config_ioapic:
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db 2 ;; entry type=I/O APIC
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db 4 ;; apic id=2. linux will set.
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db 0x11 ;; I/O APIC version number
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db 1 ;; flags=1=enabled
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dw 0x0000, 0xfec0 ;; memory mapped address of I/O APIC
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mp_config_irqs:
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db 3 ;; entry type=I/O interrupt
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db 0 ;; interrupt type=vectored interrupt
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db 0,0 ;; flags po=0, el=0 (linux uses as default)
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db 0 ;; source bus ID is ISA
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db 0 ;; source bus IRQ
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db 4 ;; destination I/O APIC ID
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db 0 ;; destination I/O APIC interrrupt in
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;; repeat pattern for interrupts 0-15
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db 3,0,0,0,0,1,4,1
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db 3,0,0,0,0,2,4,2
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db 3,0,0,0,0,3,4,3
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db 3,0,0,0,0,4,4,4
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db 3,0,0,0,0,5,4,5
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db 3,0,0,0,0,6,4,6
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db 3,0,0,0,0,7,4,7
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db 3,0,0,0,0,8,4,8
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db 3,0,0,0,0,9,4,9
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db 3,0,0,0,0,10,4,10
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db 3,0,0,0,0,11,4,11
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db 3,0,0,0,0,12,4,12
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db 3,0,0,0,0,13,4,13
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db 3,0,0,0,0,14,4,14
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db 3,0,0,0,0,15,4,15
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#else
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# error Sorry, rombios only has configurations for 1, 2, or 4 processors.
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#endif // if (BX_SMP_PROCESSORS==...)
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mp_config_end: // this label used to find length of mp structure
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db 0
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#if (BX_SMP_PROCESSORS>1)
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.align 16
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mp_floating_pointer_structure:
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db 0x5f, 0x4d, 0x50, 0x5f ; "_MP_" signature
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dw mp_config_table, 0xf ;; pointer to MP configuration table
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db 1 ;; length of this struct in 16-bit byte chunks
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db 4 ;; MP spec revision
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db 0xc1 ;; checksum
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db 0 ;; MP feature byte 1. value 0 means look at the config table
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db 0,0,0,0 ;; MP feature bytes 2-5.
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#endif
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;; for 'C' strings and other data, insert them here with
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;; a the following hack:
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;; DATA_SEG_DEFS_HERE
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@ -4871,4 +4683,193 @@ db 0x00 ; filler
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.org 0xd000
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// bcc-generated data will be placed here
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// For documentation of this config structure, look on developer.intel.com and
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// search for multiprocessor specification. Note that when you change anything
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// you must update the checksum (a pain!). It would be better to construct this
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// with C structures, or at least fill in the checksum automatically.
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#if (BX_SMP_PROCESSORS==1)
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// no structure necessary.
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#elif (BX_SMP_PROCESSORS==2)
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// define the Intel MP Configuration Structure for 2 processors at
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// APIC ID 0,1. I/O APIC at ID=2.
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.align 16
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mp_config_table:
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db 0x50, 0x43, 0x4d, 0x50 ;; "PCMP" signature
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dw (mp_config_end-mp_config_table) ;; table length
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db 4 ;; spec rev
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db 0xdd ;; checksum
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db 0x42, 0x42, 0x44, 0x43, 0x50, 0x55, 0x20, 0x20 ;; OEM id = "BBDCPU "
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db 0x30, 0x2e, 0x31, 0x20 ;; vendor id = "0.1 "
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db 0x20, 0x20, 0x20, 0x20
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db 0x20, 0x20, 0x20, 0x20
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dw 0,0 ;; oem table ptr
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dw 0 ;; oem table size
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dw 3 ;; entry count
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dw 0x0000, 0xfee0 ;; memory mapped address of local APIC
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dw 0 ;; extended table length
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db 0 ;; extended table checksum
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db 0 ;; reserved
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mp_config_proc0:
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db 0 ;; entry type=processor
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db 0 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 3 ;; cpu flags: enabled
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_proc1:
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db 0 ;; entry type=processor
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db 1 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 1 ;; cpu flags: enabled
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_isa_bus:
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db 1 ;; entry type=bus
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db 0 ;; bus ID
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db 0x49, 0x53, 0x41, 0x20, 0x20, 0x20 ;; bus type="ISA "
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mp_config_ioapic:
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db 2 ;; entry type=I/O APIC
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db 2 ;; apic id=2. linux will set.
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db 0x11 ;; I/O APIC version number
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db 1 ;; flags=1=enabled
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dw 0x0000, 0xfec0 ;; memory mapped address of I/O APIC
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mp_config_irqs:
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db 3 ;; entry type=I/O interrupt
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db 0 ;; interrupt type=vectored interrupt
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db 0,0 ;; flags po=0, el=0 (linux uses as default)
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db 0 ;; source bus ID is ISA
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db 0 ;; source bus IRQ
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db 2 ;; destination I/O APIC ID
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db 0 ;; destination I/O APIC interrrupt in
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;; repeat pattern for interrupts 0-15
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db 3,0,0,0,0,1,2,1
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db 3,0,0,0,0,2,2,2
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db 3,0,0,0,0,3,2,3
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db 3,0,0,0,0,4,2,4
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db 3,0,0,0,0,5,2,5
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db 3,0,0,0,0,6,2,6
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db 3,0,0,0,0,7,2,7
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db 3,0,0,0,0,8,2,8
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db 3,0,0,0,0,9,2,9
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db 3,0,0,0,0,10,2,10
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db 3,0,0,0,0,11,2,11
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db 3,0,0,0,0,12,2,12
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db 3,0,0,0,0,13,2,13
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db 3,0,0,0,0,14,2,14
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db 3,0,0,0,0,15,2,15
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#elif (BX_SMP_PROCESSORS==4)
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// define the Intel MP Configuration Structure for 4 processors at
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// APIC ID 0,1,2,3. I/O APIC at ID=4.
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.align 16
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mp_config_table:
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db 0x50, 0x43, 0x4d, 0x50 ;; "PCMP" signature
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dw (mp_config_end-mp_config_table) ;; table length
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db 4 ;; spec rev
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db 0x55 ;; checksum
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db 0x42, 0x42, 0x44, 0x43, 0x50, 0x55, 0x20, 0x20 ;; OEM id = "BBDCPU "
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db 0x30, 0x2e, 0x31, 0x20 ;; vendor id = "0.1 "
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db 0x20, 0x20, 0x20, 0x20
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db 0x20, 0x20, 0x20, 0x20
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dw 0,0 ;; oem table ptr
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dw 0 ;; oem table size
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dw 5 ;; entry count
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dw 0x0000, 0xfee0 ;; memory mapped address of local APIC
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dw 0 ;; extended table length
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db 0 ;; extended table checksum
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db 0 ;; reserved
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mp_config_proc0:
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db 0 ;; entry type=processor
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db 0 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 1 ;; cpu flags: enabled
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_proc1:
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db 0 ;; entry type=processor
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db 1 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 1 ;; cpu flags: enabled
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_proc2:
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db 0 ;; entry type=processor
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db 2 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 3 ;; cpu flags: enabled, bootstrap processor
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_proc3:
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db 0 ;; entry type=processor
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db 3 ;; local APIC id
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db 0x11 ;; local APIC version number
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db 1 ;; cpu flags: enabled
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db 0,6,0,0 ;; cpu signature
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dw 0x201,0 ;; feature flags
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dw 0,0 ;; reserved
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dw 0,0 ;; reserved
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mp_config_isa_bus:
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db 1 ;; entry type=bus
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db 0 ;; bus ID
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db 0x49, 0x53, 0x41, 0x20, 0x20, 0x20 ;; bus type="ISA "
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mp_config_ioapic:
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db 2 ;; entry type=I/O APIC
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db 4 ;; apic id=2. linux will set.
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db 0x11 ;; I/O APIC version number
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db 1 ;; flags=1=enabled
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dw 0x0000, 0xfec0 ;; memory mapped address of I/O APIC
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mp_config_irqs:
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db 3 ;; entry type=I/O interrupt
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db 0 ;; interrupt type=vectored interrupt
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db 0,0 ;; flags po=0, el=0 (linux uses as default)
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db 0 ;; source bus ID is ISA
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db 0 ;; source bus IRQ
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db 4 ;; destination I/O APIC ID
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db 0 ;; destination I/O APIC interrrupt in
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;; repeat pattern for interrupts 0-15
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db 3,0,0,0,0,1,4,1
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db 3,0,0,0,0,2,4,2
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db 3,0,0,0,0,3,4,3
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db 3,0,0,0,0,4,4,4
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db 3,0,0,0,0,5,4,5
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db 3,0,0,0,0,6,4,6
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db 3,0,0,0,0,7,4,7
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db 3,0,0,0,0,8,4,8
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db 3,0,0,0,0,9,4,9
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db 3,0,0,0,0,10,4,10
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db 3,0,0,0,0,11,4,11
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db 3,0,0,0,0,12,4,12
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db 3,0,0,0,0,13,4,13
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db 3,0,0,0,0,14,4,14
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db 3,0,0,0,0,15,4,15
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#else
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# error Sorry, rombios only has configurations for 1, 2, or 4 processors.
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#endif // if (BX_SMP_PROCESSORS==...)
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mp_config_end: // this label used to find length of mp structure
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db 0
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#if (BX_SMP_PROCESSORS>1)
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.align 16
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mp_floating_pointer_structure:
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db 0x5f, 0x4d, 0x50, 0x5f ; "_MP_" signature
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dw mp_config_table, 0xf ;; pointer to MP configuration table
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db 1 ;; length of this struct in 16-bit byte chunks
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db 4 ;; MP spec revision
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db 0xc1 ;; checksum
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db 0 ;; MP feature byte 1. value 0 means look at the config table
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db 0,0,0,0 ;; MP feature bytes 2-5.
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#endif
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#endasm
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Loading…
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Block a user