mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Finished bx_bool to bool type changes.

Browse Source 
- Changes in the USB host controller code.
- Finally removed bx_bool type definition.
- NOTE: The Bochs BIOS still has it's own bx_bool definition.
This commit is contained in:
Volker Ruppert 2021-02-04 20:15:13 +00:00
parent 908b798015
commit 96193ed79c
9 changed files with 248 additions and 252 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
bochs/config.h.in
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2001-2020 The Bochs Project
// Copyright (C) 2001-2021 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -527,10 +527,6 @@ typedef Bit32u bx_phy_address;
# error "could not define bx_ptr_equiv_t to size of int*"
#endif
// Use a boolean type that will not conflict with the builtin type
// on any system.
typedef Bit32u bx_bool;
#if BX_WITH_MACOS
# define bx_ptr_t char *
#else

8
bochs/iodev/usb/uhci_core.cc
View File

@ -596,7 +596,7 @@ void bx_uhci_core_c::uhci_timer(void)
}
if (hub.usb_command.schedule) {
busy = 1;
bx_bool interrupt = 0, shortpacket = 0, stalled = 0, was_inactive = 0;
bool interrupt = 0, shortpacket = 0, stalled = 0, was_inactive = 0;
struct TD td;
struct HCSTACK stack[USB_STACK_SIZE+1]; // queue stack for this item only
Bit32s stk = 0;
@ -647,9 +647,9 @@ void bx_uhci_core_c::uhci_timer(void)
DEV_MEM_READ_PHYSICAL(address+4, 4, (Bit8u*) &td.dword1);
DEV_MEM_READ_PHYSICAL(address+8, 4, (Bit8u*) &td.dword2);
DEV_MEM_READ_PHYSICAL(address+12, 4, (Bit8u*) &td.dword3);
bx_bool spd = (td.dword1 & (1<<29)) ? 1 : 0;
bool spd = (td.dword1 & (1<<29)) ? 1 : 0;
stack[stk].next = td.dword0 & ~0xF;
bx_bool depthbreadth = (td.dword0 & 0x0004) ? 1 : 0; // 1 = depth first, 0 = breadth first
bool depthbreadth = (td.dword0 & 0x0004) ? 1 : 0; // 1 = depth first, 0 = breadth first
stack[stk].q = (td.dword0 & 0x0002) ? 1 : 0;
stack[stk].t = (td.dword0 & 0x0001) ? 1 : 0;
if (td.dword1 & (1<<23)) { // is it an active TD
@ -775,7 +775,7 @@ bool bx_uhci_core_c::DoTransfer(Bit32u address, Bit32u queue_num, struct TD *td)
int len = 0, ret = 0;
USBAsync *p;
bx_bool completion;
bool completion;
Bit16u maxlen = (td->dword2 >> 21);
Bit8u addr = (td->dword2 >> 8) & 0x7F;

66
bochs/iodev/usb/uhci_core.h
View File

@ -51,14 +51,14 @@ typedef struct {
// Bit 1 = host controller reset
// Bit 0 = run/stop schedule
struct {
bx_bool max_packet_size; //(bit 7) 0 = 32 bytes, 1 = 64 bytes
bx_bool configured; //(bit 6)
bx_bool debug; //(bit 5)
bx_bool resume; //(bit 4)
bx_bool suspend; //(bit 3)
bx_bool reset; //(bit 2)
bx_bool host_reset; //(bit 1)
bx_bool schedule; //(bit 0) 0 = Stop, 1 = Run
bool max_packet_size; //(bit 7) 0 = 32 bytes, 1 = 64 bytes
bool configured; //(bit 6)
bool debug; //(bit 5)
bool resume; //(bit 4)
bool suspend; //(bit 3)
bool reset; //(bit 2)
bool host_reset; //(bit 1)
bool schedule; //(bit 0) 0 = Stop, 1 = Run
} usb_command;
// Status Register
@ -70,13 +70,13 @@ typedef struct {
// Bit 1 = USB error interrupt
// Bit 0 = USB interrupt
struct {
bx_bool host_halted; //(bit 5)
bx_bool host_error; //(bit 4)
bx_bool pci_error; //(bit 3)
bx_bool resume; //(bit 2)
bx_bool error_interrupt; //(bit 1)
bx_bool interrupt; //(bit 0)
Bit8u status2; // bit 0 and 1 are used to generate the interrupt
bool host_halted; //(bit 5)
bool host_error; //(bit 4)
bool pci_error; //(bit 3)
bool resume; //(bit 2)
bool error_interrupt; //(bit 1)
bool interrupt; //(bit 0)
Bit8u status2; // bit 0 and 1 are used to generate the interrupt
} usb_status;
// Interrupt Enable Register
@ -86,10 +86,10 @@ typedef struct {
// Bit 1 = enable resume
// Bit 0 = enable timeout/crc
struct {
bx_bool short_packet; //(bit 3)
bx_bool on_complete; //(bit 2)
bx_bool resume; //(bit 1)
bx_bool timeout_crc; //(bit 0)
bool short_packet; //(bit 3)
bool on_complete; //(bit 2)
bool resume; //(bit 1)
bool timeout_crc; //(bit 0)
} usb_enable;
// Frame Number Register
@ -136,19 +136,19 @@ typedef struct {
usb_device_c *device; // device connected to this port
// bit reps of actual port
bx_bool suspend;
bx_bool reset;
bx_bool low_speed;
bx_bool resume;
bx_bool line_dminus;
bx_bool line_dplus;
bx_bool able_changed;
bx_bool enabled;
bx_bool connect_changed;
bx_bool status;
bool suspend;
bool reset;
bool low_speed;
bool resume;
bool line_dminus;
bool line_dplus;
bool able_changed;
bool enabled;
bool connect_changed;
bool status;
} usb_port[USB_UHCI_PORTS];
Bit8u devfunc;
Bit8u devfunc;
} bx_uhci_core_t;
#pragma pack (push, 1)
@ -166,8 +166,8 @@ struct TD {
struct HCSTACK {
Bit32u next;
Bit8u d; // if queue, denotes VERT or HORZ
bx_bool q;
bx_bool t;
bool q;
bool t;
};
class bx_uhci_core_c : public bx_pci_device_c {
@ -186,7 +186,7 @@ public:
protected:
bx_uhci_core_t hub;
Bit8u global_reset;
bx_bool busy;
bool busy;
USBAsync *packets;

6
bochs/iodev/usb/usb_ehci.cc
View File

@ -538,8 +538,8 @@ void bx_usb_ehci_c::remove_device(Bit8u port)
void bx_usb_ehci_c::set_connect_status(Bit8u port, int type, bool connected)
{
const bx_bool ccs_org = BX_EHCI_THIS hub.usb_port[port].portsc.ccs;
const bx_bool ped_org = BX_EHCI_THIS hub.usb_port[port].portsc.ped;
const bool ccs_org = BX_EHCI_THIS hub.usb_port[port].portsc.ccs;
const bool ped_org = BX_EHCI_THIS hub.usb_port[port].portsc.ped;
usb_device_c *device = BX_EHCI_THIS hub.usb_port[port].device;
if (device != NULL) {
@ -756,7 +756,7 @@ bool bx_usb_ehci_c::write_handler(bx_phy_address addr, unsigned len, void *data,
{
Bit32u value = *((Bit32u *) data);
Bit32u value_hi = *((Bit32u *) ((Bit8u *) data + 4));
bx_bool oldcfg, oldpo, oldpr, oldfpr;
bool oldcfg, oldpo, oldpr, oldfpr;
int i, port;
const Bit32u offset = (Bit32u) (addr - BX_EHCI_THIS pci_bar[0].addr);

58
bochs/iodev/usb/usb_ehci.h
View File

@ -235,19 +235,19 @@ typedef struct {
struct {
struct {
Bit8u itc;
bx_bool iaad;
bx_bool ase;
bx_bool pse;
bx_bool hcreset;
bx_bool rs;
Bit8u itc;
bool iaad;
bool ase;
bool pse;
bool hcreset;
bool rs;
} UsbCmd;
struct {
bx_bool ass;
bx_bool pss;
bx_bool recl;
bx_bool hchalted;
Bit8u inti;
bool ass;
bool pss;
bool recl;
bool hchalted;
Bit8u inti;
} UsbSts;
Bit8u UsbIntr;
Bit32u FrIndex;
@ -260,25 +260,25 @@ typedef struct {
struct {
// our data
usb_device_c *device; // device connected to this port
bx_bool owner_change;
bool owner_change;
struct {
bx_bool woe;
bx_bool wde;
bx_bool wce;
Bit8u ptc;
Bit8u pic;
bx_bool po;
bx_bool pp;
Bit8u ls;
bx_bool pr;
bx_bool sus;
bx_bool fpr;
bx_bool occ;
bx_bool oca;
bx_bool pec;
bx_bool ped;
bx_bool csc;
bx_bool ccs;
bool woe;
bool wde;
bool wce;
Bit8u ptc;
Bit8u pic;
bool po;
bool pp;
Bit8u ls;
bool pr;
bool sus;
bool fpr;
bool occ;
bool oca;
bool pec;
bool ped;
bool csc;
bool ccs;
} portsc;
} usb_port[USB_EHCI_PORTS];

6
bochs/iodev/usb/usb_ohci.cc
View File

@ -1219,7 +1219,7 @@ bool bx_usb_ohci_c::process_td(struct OHCI_TD *td, struct OHCI_ED *ed)
Bit32u addr;
Bit16u maxlen = 0;
USBAsync *p;
bx_bool completion;
bool completion;
addr = ED_GET_HEADP(ed);
p = find_async_packet(&packets, addr);
@ -1461,8 +1461,8 @@ void bx_usb_ohci_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_l
void bx_usb_ohci_c::usb_set_connect_status(Bit8u port, int type, bool connected)
{
const bx_bool ccs_org = BX_OHCI_THIS hub.usb_port[port].HcRhPortStatus.ccs;
const bx_bool pes_org = BX_OHCI_THIS hub.usb_port[port].HcRhPortStatus.pes;
const bool ccs_org = BX_OHCI_THIS hub.usb_port[port].HcRhPortStatus.ccs;
const bool pes_org = BX_OHCI_THIS hub.usb_port[port].HcRhPortStatus.pes;
usb_device_c *device = BX_OHCI_THIS hub.usb_port[port].device;
if (device != NULL) {

126
bochs/iodev/usb/usb_ohci.h
View File

@ -148,26 +148,26 @@ typedef struct {
struct OHCI_OP_REGS {
Bit16u HcRevision;
struct {
Bit32u reserved; // 21 bit reserved = 0x000000 R R
bx_bool rwe; // 1 bit RemoteWakeupEnable = 0b RW R
bx_bool rwc; // 1 bit RemoteWakeupConnected = 0b RW RW
bx_bool ir; // 1 bit InterruptRouting = 0b RW R
Bit8u hcfs; // 2 bit HostControllerFuncState = 00b RW RW
bx_bool ble; // 1 bit BulkListEnable = 0b RW R
bx_bool cle; // 1 bit ControlListEnable = 0b RW R
bx_bool ie; // 1 bit IsochronousEnable = 0b RW R
bx_bool ple; // 1 bit PeriodicListEnable = 0b RW R
Bit8u cbsr; // 2 bit ControlBulkService Ratio = 00b RW R
} HcControl; // = 0x00000000
Bit32u reserved; // 21 bit reserved = 0x000000 R R
bool rwe; // 1 bit RemoteWakeupEnable = 0b RW R
bool rwc; // 1 bit RemoteWakeupConnected = 0b RW RW
bool ir; // 1 bit InterruptRouting = 0b RW R
Bit8u hcfs; // 2 bit HostControllerFuncState = 00b RW RW
bool ble; // 1 bit BulkListEnable = 0b RW R
bool cle; // 1 bit ControlListEnable = 0b RW R
bool ie; // 1 bit IsochronousEnable = 0b RW R
bool ple; // 1 bit PeriodicListEnable = 0b RW R
Bit8u cbsr; // 2 bit ControlBulkService Ratio = 00b RW R
} HcControl; // = 0x00000000
struct {
Bit16u reserved0; // 14 bit reserved = 0x000000 R R
Bit8u soc; // 2 bit SchedulingOverrunCount = 00b R RW
Bit16u reserved1; // 12 bit reserved = 0x000000 R R
bx_bool ocr; // 1 bit OwnershipChangeRequest = 0b RW RW
bx_bool blf; // 1 bit BulkListFilled = 0b RW RW
bx_bool clf; // 1 bit ControlListFilled = 0b RW RW
bx_bool hcr; // 1 bit HostControllerReset = 0b RW RW
} HcCommandStatus; // = 0x00000000
Bit16u reserved0; // 14 bit reserved = 0x000000 R R
Bit8u soc; // 2 bit SchedulingOverrunCount = 00b R RW
Bit16u reserved1; // 12 bit reserved = 0x000000 R R
bool ocr; // 1 bit OwnershipChangeRequest = 0b RW RW
bool blf; // 1 bit BulkListFilled = 0b RW RW
bool clf; // 1 bit ControlListFilled = 0b RW RW
bool hcr; // 1 bit HostControllerReset = 0b RW RW
} HcCommandStatus; // = 0x00000000
Bit32u HcInterruptStatus;
Bit32u HcInterruptEnable;
Bit32u HcHCCA;
@ -178,39 +178,39 @@ typedef struct {
Bit32u HcBulkCurrentED;
Bit32u HcDoneHead;
struct {
bx_bool fit; // 1 bit FrameIntervalToggle = 0b RW R
Bit16u fsmps; // 15 bit FSLargestDataPacket = TBD (0) RW R
Bit8u reserved; // 2 bit reserved = 00b R R
Bit16u fi; // 14 bit FrameInterval = 0x2EDF RW R
} HcFmInterval; // = 0x00002EDF
bx_bool HcFmRemainingToggle; // 1 bit FrameRemainingToggle = 0b R RW
bool fit; // 1 bit FrameIntervalToggle = 0b RW R
Bit16u fsmps; // 15 bit FSLargestDataPacket = TBD (0) RW R
Bit8u reserved; // 2 bit reserved = 00b R R
Bit16u fi; // 14 bit FrameInterval = 0x2EDF RW R
} HcFmInterval; // = 0x00002EDF
bool HcFmRemainingToggle; // 1 bit FrameRemainingToggle = 0b R RW
Bit32u HcFmNumber;
Bit32u HcPeriodicStart;
Bit16u HcLSThreshold;
struct {
Bit8u potpgt; // 8 bit PowerOnToPowerGoodTime = 0x10 RW R
Bit16u reserved; // 11 bit reserved = 0x000 R R
bx_bool nocp; // 1 bit NoOverCurrentProtection = 0b RW R
bx_bool ocpm; // 1 bit OverCurrentProtectionMode = 1b RW R
bx_bool dt; // 1 bit DeviceType = 0b R R
bx_bool nps; // 1 bit NoPowerSwitching = 0b RW R
bx_bool psm; // 1 bit PowerSwitchingMode = 1b RW R
Bit8u ndp; // 8 bit NumberDownstreamPorts = NUMPORTS RW R
} HcRhDescriptorA; // = 0x100009xx
Bit8u potpgt; // 8 bit PowerOnToPowerGoodTime = 0x10 RW R
Bit16u reserved; // 11 bit reserved = 0x000 R R
bool nocp; // 1 bit NoOverCurrentProtection = 0b RW R
bool ocpm; // 1 bit OverCurrentProtectionMode = 1b RW R
bool dt; // 1 bit DeviceType = 0b R R
bool nps; // 1 bit NoPowerSwitching = 0b RW R
bool psm; // 1 bit PowerSwitchingMode = 1b RW R
Bit8u ndp; // 8 bit NumberDownstreamPorts = NUMPORTS RW R
} HcRhDescriptorA; // = 0x100009xx
struct {
Bit16u ppcm; // 16 bit PortPowerControlMask = 0x0002 RW R
Bit16u dr; // 16 bit DeviceRemovable = 0x0000 RW R
} HcRhDescriptorB; // = 0x00020000
Bit16u ppcm; // 16 bit PortPowerControlMask = 0x0002 RW R
Bit16u dr; // 16 bit DeviceRemovable = 0x0000 RW R
} HcRhDescriptorB; // = 0x00020000
struct {
bx_bool crwe; // 1 bit ClearRemoteWakeupEnable = 0b WC R
Bit16u reserved0; // 13 bit reserved = 0x000000 R R
bx_bool ocic; // 1 bit OverCurrentIndicatorChange = 0b RW RW
bx_bool lpsc; // 1 bit LocalPowerStatusChange(r) = 0b RW R
bx_bool drwe; // 1 bit DeviceRemoteWakeupEnable(r) = 0b RW R
Bit16u reserved1; // 13 bit reserved = 0x000000 R R
bx_bool oci; // 1 bit OverCurrentIndicator = 0b R RW
bx_bool lps; // 1 bit LocalPowerStatus(r) = 0b RW R
} HcRhStatus; // = 0x00000000
bool crwe; // 1 bit ClearRemoteWakeupEnable = 0b WC R
Bit16u reserved0; // 13 bit reserved = 0x000000 R R
bool ocic; // 1 bit OverCurrentIndicatorChange = 0b RW RW
bool lpsc; // 1 bit LocalPowerStatusChange(r) = 0b RW R
bool drwe; // 1 bit DeviceRemoteWakeupEnable(r) = 0b RW R
Bit16u reserved1; // 13 bit reserved = 0x000000 R R
bool oci; // 1 bit OverCurrentIndicator = 0b R RW
bool lps; // 1 bit LocalPowerStatus(r) = 0b RW R
} HcRhStatus; // = 0x00000000
} op_regs;
struct {
@ -218,28 +218,28 @@ typedef struct {
usb_device_c *device; // device connected to this port
struct {
Bit16u reserved0; // 11 bit reserved = 0x000000 R R
bx_bool prsc; // 1 bit PortResetStatusChange = 0b RW RW
bx_bool ocic; // 1 bit OverCurrentIndicatorChange = 0b RW RW
bx_bool pssc; // 1 bit PortSuspendStatusChange = 0b RW RW
bx_bool pesc; // 1 bit PortEnableStatusChange = 0b RW RW
bx_bool csc; // 1 bit ConnectStatusChange = 0b RW RW
Bit8u reserved1; // 6 bit reserved = 0x00 R R
bx_bool lsda; // 1 bit LowSpeedDeviceAttached = 0b RW RW
bx_bool pps; // 1 bit PortPowerStatus = 0b RW RW
Bit8u reserved2; // 3 bit reserved = 0x0 R R
bx_bool prs; // 1 bit PortResetStatus = 0b RW RW
bx_bool poci; // 1 bit PortOverCurrentIndicator = 0b RW RW
bx_bool pss; // 1 bit PortSuspendStatus = 0b RW RW
bx_bool pes; // 1 bit PortEnableStatus = 0b RW RW
bx_bool ccs; // 1 bit CurrentConnectStatus = 0b RW RW
Bit16u reserved0; // 11 bit reserved = 0x000000 R R
bool prsc; // 1 bit PortResetStatusChange = 0b RW RW
bool ocic; // 1 bit OverCurrentIndicatorChange = 0b RW RW
bool pssc; // 1 bit PortSuspendStatusChange = 0b RW RW
bool pesc; // 1 bit PortEnableStatusChange = 0b RW RW
bool csc; // 1 bit ConnectStatusChange = 0b RW RW
Bit8u reserved1; // 6 bit reserved = 0x00 R R
bool lsda; // 1 bit LowSpeedDeviceAttached = 0b RW RW
bool pps; // 1 bit PortPowerStatus = 0b RW RW
Bit8u reserved2; // 3 bit reserved = 0x0 R R
bool prs; // 1 bit PortResetStatus = 0b RW RW
bool poci; // 1 bit PortOverCurrentIndicator = 0b RW RW
bool pss; // 1 bit PortSuspendStatus = 0b RW RW
bool pes; // 1 bit PortEnableStatus = 0b RW RW
bool ccs; // 1 bit CurrentConnectStatus = 0b RW RW
} HcRhPortStatus;
} usb_port[USB_OHCI_PORTS];
Bit8u devfunc;
unsigned ohci_done_count;
bx_bool use_control_head;
bx_bool use_bulk_head;
bool use_control_head;
bool use_bulk_head;
Bit64u sof_time;
Bit8u device_change;

14
bochs/iodev/usb/usb_xhci.cc
View File

@ -1934,8 +1934,8 @@ void bx_usb_xhci_c::process_transfer_ring(const int slot, const int ep)
int port_num = BX_XHCI_THIS hub.slots[slot].slot_context.rh_port_num;
USBAsync *p;
Bit8u cur_direction = (ep & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT; // for NORMAL without SETUP
bx_bool is_transfer_trb, is_immed_data, ioc, spd_occurred = 0;
bx_bool first_event_trb_encountered = 0;
bool is_transfer_trb, is_immed_data, ioc, spd_occurred = 0;
bool first_event_trb_encountered = 0;
Bit32u bytes_not_transferred = 0;
int comp_code = 0;
Bit8u immed_data[8];
@ -2099,7 +2099,7 @@ void bx_usb_xhci_c::process_transfer_ring(const int slot, const int ep)
// is there a transfer to be done?
if (is_transfer_trb) {
p = find_async_packet(&BX_XHCI_THIS packets, org_addr);
bx_bool completion = (p != NULL);
bool completion = (p != NULL);
if (completion && !p->done) {
return;
}
@ -2483,7 +2483,7 @@ void bx_usb_xhci_c::process_command_ring(void)
case CONFIG_EP: {
slot = TRB_GET_SLOT(trb.command); // slots are 1 based
bx_bool dc = TRB_DC(trb.command);
bool dc = TRB_DC(trb.command);
if (BX_XHCI_THIS hub.slots[slot].enabled) {
get_dwords((bx_phy_address) trb.parameter, (Bit32u*)buffer, (CONTEXT_SIZE + (CONTEXT_SIZE * 32)) >> 2);
DEV_MEM_READ_PHYSICAL((bx_phy_address) trb.parameter, 4, (Bit8u*)&d_flags);
@ -2572,7 +2572,7 @@ void bx_usb_xhci_c::process_command_ring(void)
BX_XHCI_THIS hub.slots[slot].ep_context[ep].ep_context.tr_dequeue_pointer =
BX_XHCI_THIS hub.slots[slot].ep_context[ep].enqueue_pointer = (trb.parameter & (Bit64u) ~0xF);
BX_XHCI_THIS hub.slots[slot].ep_context[ep].ep_context.dcs =
BX_XHCI_THIS hub.slots[slot].ep_context[ep].rcs = (bx_bool) (trb.parameter & 1);
BX_XHCI_THIS hub.slots[slot].ep_context[ep].rcs = (bool) (trb.parameter & 1);
BX_XHCI_THIS hub.slots[slot].ep_context[ep].edtla = 0;
update_ep_context(slot, ep);
comp_code = TRB_SUCCESS;
@ -3142,8 +3142,8 @@ void bx_usb_xhci_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_l
void bx_usb_xhci_c::usb_set_connect_status(Bit8u port, int type, bool connected)
{
const bx_bool ccs_org = BX_XHCI_THIS hub.usb_port[port].portsc.ccs;
const bx_bool ped_org = BX_XHCI_THIS hub.usb_port[port].portsc.ped;
const bool ccs_org = BX_XHCI_THIS hub.usb_port[port].portsc.ccs;
const bool ped_org = BX_XHCI_THIS hub.usb_port[port].portsc.ped;
usb_device_c *device = BX_XHCI_THIS hub.usb_port[port].device;
if (device != NULL) {

210
bochs/iodev/usb/usb_xhci.h
View File

@ -161,11 +161,11 @@
// our saved ring members
struct RING_MEMBERS {
struct {
Bit64u dq_pointer;
bx_bool rcs;
Bit64u dq_pointer;
bool rcs;
} command_ring;
struct {
bx_bool rcs;
bool rcs;
unsigned trb_count;
unsigned count;
Bit64u cur_trb;
@ -179,8 +179,8 @@ struct RING_MEMBERS {
struct SLOT_CONTEXT {
unsigned entries;
bx_bool hub;
bx_bool mtt;
bool hub;
bool mtt;
unsigned speed;
Bit32u route_string;
unsigned num_ports;
@ -196,32 +196,32 @@ struct SLOT_CONTEXT {
struct EP_CONTEXT {
unsigned interval;
bx_bool lsa;
bool lsa;
unsigned max_pstreams;
unsigned mult;
unsigned ep_state;
unsigned max_packet_size;
unsigned max_burst_size;
bx_bool hid;
bool hid;
unsigned ep_type;
unsigned cerr;
Bit64u tr_dequeue_pointer;
bx_bool dcs;
bool dcs;
unsigned max_esit_payload;
unsigned average_trb_len;
};
struct HC_SLOT_CONTEXT {
bx_bool enabled;
bx_bool sent_address; // have we sent a SET_ADDRESS command yet?
bool enabled;
bool sent_address; // have we sent a SET_ADDRESS command yet?
struct SLOT_CONTEXT slot_context;
struct {
struct EP_CONTEXT ep_context;
// our internal registers follow
Bit32u edtla;
Bit64u enqueue_pointer;
bx_bool rcs;
bx_bool retry;
bool rcs;
bool retry;
int retry_counter;
} ep_context[32]; // first one is ignored by controller.
};
@ -335,119 +335,119 @@ typedef struct {
struct XHCI_OP_REGS {
struct {
Bit32u RsvdP1; // 18/20 bit reserved and preserved = 0x000000 RW
Bit32u RsvdP1; // 18/20 bit reserved and preserved = 0x000000 RW
#if ((VERSION_MAJOR == 1) && (VERSION_MINOR >= 0x10))
bx_bool cme; // 1 bit Max Exit Latecy to Large = 0b RW
bx_bool spe; // 1 bit Generate Short Packet Comp = 0b RW
bool cme; // 1 bit Max Exit Latecy to Large = 0b RW
bool spe; // 1 bit Generate Short Packet Comp = 0b RW
#endif
bx_bool eu3s; // 1 bit Enable U3 MFINDEX Stop = 0b RW
bx_bool ewe; // 1 bit Enable Wrap Event = 0b RW
bx_bool crs; // 1 bit Controller Restore State = 0b RW
bx_bool css; // 1 bit Controller Save State = 0b RW
bx_bool lhcrst; // 1 bit Light HC Reset = 0b RW or RO (HCCPARAMS:LHRC)
Bit8u RsvdP0; // 1 bit reserved and preserved = 000b RW
bx_bool hsee; // 1 bit Host System Error Enable = 0b RW
bx_bool inte; // 1 bit Interrupter Enable = 0b RW
bx_bool hcrst; // 1 bit HC Reset = 0b RW
bx_bool rs; // 1 bit Run Stop = 0b RW
} HcCommand; // = 0x00000000
bool eu3s; // 1 bit Enable U3 MFINDEX Stop = 0b RW
bool ewe; // 1 bit Enable Wrap Event = 0b RW
bool crs; // 1 bit Controller Restore State = 0b RW
bool css; // 1 bit Controller Save State = 0b RW
bool lhcrst; // 1 bit Light HC Reset = 0b RW or RO (HCCPARAMS:LHRC)
Bit8u RsvdP0; // 1 bit reserved and preserved = 000b RW
bool hsee; // 1 bit Host System Error Enable = 0b RW
bool inte; // 1 bit Interrupter Enable = 0b RW
bool hcrst; // 1 bit HC Reset = 0b RW
bool rs; // 1 bit Run Stop = 0b RW
} HcCommand; // = 0x00000000
struct {
Bit32u RsvdZ1; // 19 bit reserved and zero'd = 0x000000 RW
bx_bool hce; // 1 bit Host Controller Error = 0b RO
bx_bool cnr; // 1 bit Controller Not Ready = 0b R0
bx_bool sre; // 1 bit Save/Restore Error = 0b RW1C
bx_bool rss; // 1 bit Restore State Status = 0b RO
bx_bool sss; // 1 bit Save State Status = 0b RO
Bit8u RsvdZ0; // 3 bit reserved and zero'd = 0x0 RW
bx_bool pcd; // 1 bit Port Change Detect = 0b RW1C
bx_bool eint; // 1 bit Event Interrupt = 0b RW1C
bx_bool hse; // 1 bit Host System Error = 0b RW1C
bx_bool RsvdZ2; // 1 bit reserved and zero'd = 0b RW
bx_bool hch; // 1 bit HCHalted = 1b RO
} HcStatus; // = 0x00000001
Bit32u RsvdZ1; // 19 bit reserved and zero'd = 0x000000 RW
bool hce; // 1 bit Host Controller Error = 0b RO
bool cnr; // 1 bit Controller Not Ready = 0b R0
bool sre; // 1 bit Save/Restore Error = 0b RW1C
bool rss; // 1 bit Restore State Status = 0b RO
bool sss; // 1 bit Save State Status = 0b RO
Bit8u RsvdZ0; // 3 bit reserved and zero'd = 0x0 RW
bool pcd; // 1 bit Port Change Detect = 0b RW1C
bool eint; // 1 bit Event Interrupt = 0b RW1C
bool hse; // 1 bit Host System Error = 0b RW1C
bool RsvdZ2; // 1 bit reserved and zero'd = 0b RW
bool hch; // 1 bit HCHalted = 1b RO
} HcStatus; // = 0x00000001
struct {
Bit16u Rsvd; // 16 bit reserved = 0x0000 RO
Bit16u pagesize; // 16 bit reserved = 0x0001 RO
} HcPageSize; // = 0x00000001
Bit16u Rsvd; // 16 bit reserved = 0x0000 RO
Bit16u pagesize; // 16 bit reserved = 0x0001 RO
} HcPageSize; // = 0x00000001
struct {
Bit16u RsvdP; // 16 bit reserved and presserved = 0x0000 RW
bx_bool n15; // 1 bit N15 = 0 RW
bx_bool n14; // 1 bit N14 = 0 RW
bx_bool n13; // 1 bit N13 = 0 RW
bx_bool n12; // 1 bit N12 = 0 RW
bx_bool n11; // 1 bit N11 = 0 RW
bx_bool n10; // 1 bit N10 = 0 RW
bx_bool n9; // 1 bit N9 = 0 RW
bx_bool n8; // 1 bit N8 = 0 RW
bx_bool n7; // 1 bit N7 = 0 RW
bx_bool n6; // 1 bit N6 = 0 RW
bx_bool n5; // 1 bit N5 = 0 RW
bx_bool n4; // 1 bit N4 = 0 RW
bx_bool n3; // 1 bit N3 = 0 RW
bx_bool n2; // 1 bit N2 = 0 RW
bx_bool n1; // 1 bit N1 = 0 RW
bx_bool n0; // 1 bit N0 = 0 RW
} HcNotification; // = 0x00000000
Bit16u RsvdP; // 16 bit reserved and presserved = 0x0000 RW
bool n15; // 1 bit N15 = 0 RW
bool n14; // 1 bit N14 = 0 RW
bool n13; // 1 bit N13 = 0 RW
bool n12; // 1 bit N12 = 0 RW
bool n11; // 1 bit N11 = 0 RW
bool n10; // 1 bit N10 = 0 RW
bool n9; // 1 bit N9 = 0 RW
bool n8; // 1 bit N8 = 0 RW
bool n7; // 1 bit N7 = 0 RW
bool n6; // 1 bit N6 = 0 RW
bool n5; // 1 bit N5 = 0 RW
bool n4; // 1 bit N4 = 0 RW
bool n3; // 1 bit N3 = 0 RW
bool n2; // 1 bit N2 = 0 RW
bool n1; // 1 bit N1 = 0 RW
bool n0; // 1 bit N0 = 0 RW
} HcNotification; // = 0x00000000
struct {
Bit64u crc; // 64 bit hi order address = 0x00000000 RW
Bit8u RsvdP; // 2 bit reserved and preserved = 00b RW
bx_bool crr; // 1 bit Command Ring Running = 0 RO
bx_bool ca; // 1 bit Command Abort = 0 RW1S
bx_bool cs; // 1 bit Command Stop = 0 RW1S
bx_bool rcs; // 1 bit Ring Cycle State = 0 RW
Bit64u crc; // 64 bit hi order address = 0x00000000 RW
Bit8u RsvdP; // 2 bit reserved and preserved = 00b RW
bool crr; // 1 bit Command Ring Running = 0 RO
bool ca; // 1 bit Command Abort = 0 RW1S
bool cs; // 1 bit Command Stop = 0 RW1S
bool rcs; // 1 bit Ring Cycle State = 0 RW
} HcCrcr;
struct {
Bit64u dcbaap; // 64 bit hi order address = 0x00000000 RW
Bit8u RsvdZ; // 6 bit reserved and zero'd = 000000b RW
Bit64u dcbaap; // 64 bit hi order address = 0x00000000 RW
Bit8u RsvdZ; // 6 bit reserved and zero'd = 000000b RW
} HcDCBAAP;
struct {
Bit32u RsvdP; // 22/24 bit reserved and preserved = 0x000000 RW
Bit32u RsvdP; // 22/24 bit reserved and preserved = 0x000000 RW
#if ((VERSION_MAJOR == 1) && (VERSION_MINOR >= 0x10))
bx_bool u3e; // 1 bit U3 Entry Enable = 0 RW
bx_bool cie; // 1 bit Config Info Enable = 0 RW
bool u3e; // 1 bit U3 Entry Enable = 0 RW
bool cie; // 1 bit Config Info Enable = 0 RW
#endif
Bit8u MaxSlotsEn; // 8 bit Max Device Slots Enabled = 0x00 RW
Bit8u MaxSlotsEn; // 8 bit Max Device Slots Enabled = 0x00 RW
} HcConfig;
} op_regs;
struct {
// our data
usb_device_c *device; // device connected to this port
bx_bool is_usb3; // set if usb3 port, cleared if usb2 port.
bx_bool has_been_reset; // set if the port has been reset aftet powered up.
usb_device_c *device; // device connected to this port
bool is_usb3; // set if usb3 port, cleared if usb2 port.
bool has_been_reset; // set if the port has been reset aftet powered up.
struct {
bx_bool wpr; // 1 bit Warm Port Reset = 0b RW or RsvdZ
bx_bool dr; // 1 bit Device Removable = 0b RO
Bit8u RsvdZ1; // 2 bit Reserved and Zero'd = 00b RW
bx_bool woe; // 1 bit Wake on Over Current Enable = 0b RW
bx_bool wde; // 1 bit Wake on Disconnect Enable = 0b RW
bx_bool wce; // 1 bit Wake on Connect Enable = 0b RW
bx_bool cas; // 1 bit Cold Attach Status = 0b RO
bx_bool cec; // 1 bit Port Config Error Change = 0b RW1C or RsvdZ
bx_bool plc; // 1 bit Port Link State Change = 0b RW1C
bx_bool prc; // 1 bit Port Reset Change = 0b RW1C
bx_bool occ; // 1 bit Over Current Change = 0b RW1C
bx_bool wrc; // 1 bit Warm Port Reset Change = 0b RW1C or RsvdZ
bx_bool pec; // 1 bit Port Enabled/Disabled Change= 0b RW1C
bx_bool csc; // 1 bit Connect Status Change = 0b RW1C
bx_bool lws; // 1 bit Port Link State Write Strobe= 0b RW
Bit8u pic; // 2 bit Port Indicator Control = 00b RW
Bit8u speed; // 4 bit Port Speed = 0000b RO
bx_bool pp; // 1 bit Port Power = 0b RW
Bit8u pls; // 4 bit Port Link State = 0x00 RW
bx_bool pr; // 1 bit Port Reset = 0b RW
bx_bool oca; // 1 bit Over Current Active = 0b RO
bx_bool RsvdZ0; // 1 bit Reserved and Zero'd = 0b RW
bx_bool ped; // 1 bit Port Enabled/Disabled = 0b RW1C
bx_bool ccs; // 1 bit Current Connect Status = 0b RO
bool wpr; // 1 bit Warm Port Reset = 0b RW or RsvdZ
bool dr; // 1 bit Device Removable = 0b RO
Bit8u RsvdZ1; // 2 bit Reserved and Zero'd = 00b RW
bool woe; // 1 bit Wake on Over Current Enable = 0b RW
bool wde; // 1 bit Wake on Disconnect Enable = 0b RW
bool wce; // 1 bit Wake on Connect Enable = 0b RW
bool cas; // 1 bit Cold Attach Status = 0b RO
bool cec; // 1 bit Port Config Error Change = 0b RW1C or RsvdZ
bool plc; // 1 bit Port Link State Change = 0b RW1C
bool prc; // 1 bit Port Reset Change = 0b RW1C
bool occ; // 1 bit Over Current Change = 0b RW1C
bool wrc; // 1 bit Warm Port Reset Change = 0b RW1C or RsvdZ
bool pec; // 1 bit Port Enabled/Disabled Change= 0b RW1C
bool csc; // 1 bit Connect Status Change = 0b RW1C
bool lws; // 1 bit Port Link State Write Strobe= 0b RW
Bit8u pic; // 2 bit Port Indicator Control = 00b RW
Bit8u speed; // 4 bit Port Speed = 0000b RO
bool pp; // 1 bit Port Power = 0b RW
Bit8u pls; // 4 bit Port Link State = 0x00 RW
bool pr; // 1 bit Port Reset = 0b RW
bool oca; // 1 bit Over Current Active = 0b RO
bool RsvdZ0; // 1 bit Reserved and Zero'd = 0b RW
bool ped; // 1 bit Port Enabled/Disabled = 0b RW1C
bool ccs; // 1 bit Current Connect Status = 0b RO
} portsc;
union {
// if usb3 port
struct {
struct {
Bit16u RsvdP; // 15 bit Reserved and Preserved = 0x0000 RW
bx_bool fla; // 1 bit Force Link PM Accept = 0x0000 RW
bool fla; // 1 bit Force Link PM Accept = 0x0000 RW
Bit8u u2timeout; // 8 bit U2 Timeout = 0x0000 RW
Bit8u u1timeout; // 8 bit U1 Timeout = 0x0000 RW
} portpmsc;
@ -461,10 +461,10 @@ typedef struct {
struct {
Bit8u tmode; // 4 bit Test Mode = 0x0 RO
Bit16u RsvdP; // 11 bit reserved and preseved = 0x000 RW
bx_bool hle; // 1 bit hardware LPM enable = 0b RW
bool hle; // 1 bit hardware LPM enable = 0b RW
Bit8u l1dslot; // 8 bit L1 Device Slot = 0x00 RW
Bit8u hird; // 4 bit Host Initiated Resume Durat = 0x0 RW
bx_bool rwe; // 1 bit Remote Wakeup Enable = 0b RW
bool rwe; // 1 bit Remote Wakeup Enable = 0b RW
Bit8u l1s; // 3 bit L1 Status = 000b RO
} portpmsc;
struct {
@ -491,8 +491,8 @@ typedef struct {
struct {
struct {
Bit32u RsvdP; // 30 bit reserved and preseved = 0x00000000 RW
bx_bool ie; // 1 bit Interrupt Enable = 0b RW
bx_bool ip; // 1 bit Interrupt Pending = 0b RW1C
bool ie; // 1 bit Interrupt Enable = 0b RW
bool ip; // 1 bit Interrupt Pending = 0b RW1C
} iman;
struct {
Bit16u imodc; // 16 bit Interrupter Mod Counter = 0x0000 RW
@ -509,7 +509,7 @@ typedef struct {
} erstba;
struct {
Bit64u eventadd; // 64 bit Event Ring Addy hi = 0x00000000 RW
bx_bool ehb; // 1 bit Event Handler Busy = 0b RW1C
bool ehb; // 1 bit Event Handler Busy = 0b RW1C
Bit8u desi; // 2 bit Dequeue ERST Seg Index = 00b RW
} erdp;
} interrupter[INTERRUPTERS];