diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h index a00946df6..f55fb8b1a 100644 --- a/bochs/cpu/cpu.h +++ b/bochs/cpu/cpu.h @@ -4114,6 +4114,9 @@ public: // for now... BX_SMF int fetchDecode64(const Bit8u *fetchPtr, Bit32u fetchModeMask, bxInstruction_c *i, unsigned remainingInPage) BX_CPP_AttrRegparmN(3); #endif BX_SMF void boundaryFetch(const Bit8u *fetchPtr, unsigned remainingInPage, bxInstruction_c *); +#if BX_SUPPORT_EVEX + BX_SMF unsigned evex_displ8_compression(bxInstruction_c *i, unsigned ia_opcode, unsigned type, unsigned vex_w); +#endif BX_SMF Bit16u WalkOpcodeTables(const BxOpcodeInfo_t *op, Bit16u &attr, unsigned modrm, unsigned sse_prefix, unsigned osize, unsigned vex_vl, bx_bool vex_w); BX_SMF char* disasm(const Bit8u *opcode, bool is_32, bool is_64, char *disbufptr, bxInstruction_c *i, bx_address cs_base = 0, bx_address rip = 0); diff --git a/bochs/cpu/disasm.cc b/bochs/cpu/disasm.cc index 9de422448..501b60e97 100644 --- a/bochs/cpu/disasm.cc +++ b/bochs/cpu/disasm.cc @@ -236,20 +236,21 @@ char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_a unsigned src = (unsigned) BxOpcodesTable[ia_opcode].src[n]; unsigned src_type = src >> 3; unsigned src_index = src & 0x7; - if (! src_type && src != BX_SRC_RM) continue; + if (! src_type && src != BX_SRC_RM && src != BX_SRC_EVEX_RM) continue; if (srcs_used++ > 0) disbufptr = dis_sprintf(disbufptr, ", "); - if (! i->modC0() && (src_index == BX_SRC_RM || src_index == BX_SRC_VSIB)) { + if (! i->modC0() && (src_index == BX_SRC_RM || src_index == BX_SRC_EVEX_RM || src_index == BX_SRC_VSIB)) { disbufptr = resolve_memref(disbufptr, i, src_index); #if BX_SUPPORT_EVEX // EVEX.z is ignored for memory destination forms - if (n == 0 && src_type == BX_VMM_REG && i->opmask()) { + if (n == 0 && (src_index == BX_SRC_EVEX_RM || src_type == BX_VMM_REG) && i->opmask()) { disbufptr = dis_sprintf(disbufptr, "{k%d}", i->opmask()); } #endif } else { + if (src_index == BX_SRC_EVEX_RM) src_type = BX_VMM_REG; unsigned srcreg = i->getSrcReg(n); if (src_type < 0x10) { switch(src_type) { diff --git a/bochs/cpu/fetchdecode.cc b/bochs/cpu/fetchdecode.cc index 0474ec979..6377fa340 100644 --- a/bochs/cpu/fetchdecode.cc +++ b/bochs/cpu/fetchdecode.cc @@ -1289,6 +1289,9 @@ BX_CPU_C::fetchDecode32(const Bit8u *iptr, Bit32u fetchModeMask, bxInstruction_c int had_vex_xop = 0, vvv = -1; bx_bool use_vvv = 0; #endif +#if BX_SUPPORT_EVEX + bx_bool displ8 = 0; +#endif os_32 = is_32 = fetchModeMask & BX_FETCH_MODE_IS32_MASK; @@ -1615,6 +1618,9 @@ fetch_b1: if (remain != 0) { // 8 sign extended to 32 i->modRMForm.displ32u = (Bit8s) *iptr++; +#if BX_SUPPORT_EVEX + displ8 = 1; +#endif remain--; goto modrm_done; } @@ -1658,6 +1664,9 @@ fetch_b1: if (remain != 0) { // 8 sign extended to 16 i->modRMForm.displ16u = (Bit8s) *iptr++; +#if BX_SUPPORT_EVEX + displ8 = 1; +#endif remain--; goto modrm_done; } @@ -1854,8 +1863,32 @@ modrm_done: } else { i->setSrcReg(n, (type == BX_VMM_REG) ? BX_VECTOR_TMP_REGISTER : BX_TMP_REGISTER); +#if BX_SUPPORT_EVEX + if (b1 == 0x62 && type == BX_GPR32 && displ8) { + if (i->as32L()) + i->modRMForm.displ32u *= 4; + else + i->modRMForm.displ16u *= 4; + } +#endif } break; +#if BX_SUPPORT_EVEX + case BX_SRC_EVEX_RM: + if (! mod_mem) { + i->setSrcReg(n, rm); + } + else { + i->setSrcReg(n, BX_VECTOR_TMP_REGISTER); + if (displ8) { + if (i->as32L()) + i->modRMForm.displ32u *= evex_displ8_compression(i, ia_opcode, type, vex_w); + else + i->modRMForm.displ16u *= evex_displ8_compression(i, ia_opcode, type, vex_w); + } + } + break; +#endif #if BX_SUPPORT_AVX case BX_SRC_VVV: i->setSrcReg(n, vvv); @@ -1868,7 +1901,15 @@ modrm_done: if (! i->as32L() || i->sibIndex() == BX_NIL_REGISTER) { ia_opcode = BX_IA_ERROR; } +#if BX_SUPPORT_EVEX + if (displ8) { + if (i->as32L()) + i->modRMForm.displ32u *= 4 << vex_w; + else + i->modRMForm.displ16u *= 4 << vex_w; + } break; +#endif #endif default: BX_PANIC(("fetchdecode32: unknown definition %d for src %d", src, n)); @@ -1989,6 +2030,53 @@ decode_done: return(0); } +#if BX_SUPPORT_EVEX +unsigned BX_CPU_C::evex_displ8_compression(bxInstruction_c *i, unsigned ia_opcode, unsigned type, unsigned vex_w) +{ + if (ia_opcode == BX_IA_V512_VMOVDDUP_VpdWpd && i->getVL() == BX_VL128) + return 8; + + unsigned len = i->getVL(); + + switch (type) { + case BX_VMM_FULL_VECTOR: + if (i->getEvexb()) { + return (4 << vex_w); + } + else { + return (16 * len); + } + + case BX_VMM_SCALAR: + return (4 << vex_w); + + case BX_VMM_HALF_VECTOR: + if (i->getEvexb()) { + return (4 << vex_w); + } + else { + return (8 * len); + } + + case BX_VMM_QUARTER_VECTOR: + BX_ASSERT(i->getEvexb()); + return (4 * len); + + case BX_VMM_OCT_VECTOR: + BX_ASSERT(i->getEvexb()); + return (2 * len); + + case BX_VMM_VEC128: + return 16; + + case BX_VMM_VEC256: + return 32; + } + + return 1; +} +#endif + Bit16u BX_CPU_C::WalkOpcodeTables(const BxOpcodeInfo_t *OpcodeInfoPtr, Bit16u &attr, unsigned modrm, unsigned sse_prefix, unsigned osize, unsigned vex_vl, bx_bool vex_w) { // Parse mod-nnn-rm and related bytes diff --git a/bochs/cpu/fetchdecode.h b/bochs/cpu/fetchdecode.h index ac8a1ca7c..164444ebb 100644 --- a/bochs/cpu/fetchdecode.h +++ b/bochs/cpu/fetchdecode.h @@ -79,7 +79,7 @@ enum { BX_SRC_EAX = 1, BX_SRC_NNN = 2, BX_SRC_RM = 3, - // place holder + BX_SRC_EVEX_RM = 4, BX_SRC_VVV = 5, BX_SRC_VIB = 6, BX_SRC_VSIB = 7 // gather/scatter vector index @@ -103,6 +103,16 @@ enum { BX_BOUNDS_REG = 0xE }; +enum { + BX_VMM_FULL_VECTOR = 0, + BX_VMM_SCALAR = 1, + BX_VMM_HALF_VECTOR = 2, + BX_VMM_QUARTER_VECTOR = 3, + BX_VMM_OCT_VECTOR = 4, + BX_VMM_VEC128 = 5, + BX_VMM_VEC256 = 6 +}; + enum { BX_IMMB = 0x10, BX_IMMW = 0x11, @@ -189,6 +199,19 @@ const Bit8u OP_Wpd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM); const Bit8u OP_Wss = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM); const Bit8u OP_Wsd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM); +const Bit8u OP_mVps = BX_FORM_SRC(BX_VMM_FULL_VECTOR, BX_SRC_EVEX_RM); +const Bit8u OP_mVpd = BX_FORM_SRC(BX_VMM_FULL_VECTOR, BX_SRC_EVEX_RM); +const Bit8u OP_mVdq = BX_FORM_SRC(BX_VMM_FULL_VECTOR, BX_SRC_EVEX_RM); +const Bit8u OP_mVss = BX_FORM_SRC(BX_VMM_SCALAR, BX_SRC_EVEX_RM); +const Bit8u OP_mVsd = BX_FORM_SRC(BX_VMM_SCALAR, BX_SRC_EVEX_RM); +const Bit8u OP_mVdq32 = BX_FORM_SRC(BX_VMM_SCALAR, BX_SRC_EVEX_RM); +const Bit8u OP_mVdq64 = BX_FORM_SRC(BX_VMM_SCALAR, BX_SRC_EVEX_RM); +const Bit8u OP_mVHV = BX_FORM_SRC(BX_VMM_HALF_VECTOR, BX_SRC_EVEX_RM); +const Bit8u OP_mVQV = BX_FORM_SRC(BX_VMM_QUARTER_VECTOR, BX_SRC_EVEX_RM); +const Bit8u OP_mVOV = BX_FORM_SRC(BX_VMM_OCT_VECTOR, BX_SRC_EVEX_RM); +const Bit8u OP_mVdq128 = BX_FORM_SRC(BX_VMM_VEC128, BX_SRC_EVEX_RM); +const Bit8u OP_mVdq256 = BX_FORM_SRC(BX_VMM_VEC256, BX_SRC_EVEX_RM); + const Bit8u OP_Hdq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VVV); const Bit8u OP_Hps = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VVV); const Bit8u OP_Hpd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VVV); diff --git a/bochs/cpu/fetchdecode64.cc b/bochs/cpu/fetchdecode64.cc index a50082bc7..b7f4cb804 100644 --- a/bochs/cpu/fetchdecode64.cc +++ b/bochs/cpu/fetchdecode64.cc @@ -1710,7 +1710,7 @@ BX_CPU_C::fetchDecode64(const Bit8u *iptr, Bit32u fetchModeMask, bxInstruction_c #endif #if BX_SUPPORT_EVEX - unsigned evex_v = 0; + unsigned evex_v = 0, displ8 = 0; #endif i->ResolveModrm = 0; @@ -2103,6 +2103,9 @@ fetch_b1: if (remain != 0) { // 8 sign extended to 32 i->modRMForm.displ32u = (Bit8s) *iptr++; +#if BX_SUPPORT_EVEX + displ8 = 1; +#endif remain--; } else { @@ -2320,8 +2323,25 @@ modrm_done: } else { i->setSrcReg(n, (type == BX_VMM_REG) ? BX_VECTOR_TMP_REGISTER : BX_TMP_REGISTER); +#if BX_SUPPORT_EVEX + if (b1 == 0x62 && displ8) { + if (type == BX_GPR32) i->modRMForm.displ32u *= 4; + else if (type == BX_GPR64) i->modRMForm.displ32u *= 8; + } +#endif } break; +#if BX_SUPPORT_EVEX + case BX_SRC_EVEX_RM: + if (! mod_mem) { + i->setSrcReg(n, rm); + } + else { + i->setSrcReg(n, BX_VECTOR_TMP_REGISTER); + if (displ8) i->modRMForm.displ32u *= evex_displ8_compression(i, ia_opcode, type, vex_w); + } + break; +#endif #if BX_SUPPORT_AVX case BX_SRC_VVV: i->setSrcReg(n, vvv); @@ -2344,6 +2364,7 @@ modrm_done: } #if BX_SUPPORT_EVEX i->setSibIndex(i->sibIndex() | evex_v); + if (displ8) i->modRMForm.displ32u *= 4 << vex_w; #endif break; #endif diff --git a/bochs/cpu/ia_opcodes.h b/bochs/cpu/ia_opcodes.h index c5bf99ab6..c20b89511 100644 --- a/bochs/cpu/ia_opcodes.h +++ b/bochs/cpu/ia_opcodes.h @@ -2462,125 +2462,125 @@ bx_define_opcode(BX_IA_KXORW_KGwKHwKEw, &BX_CPU_C::BxError, &BX_CPU_C::KXORW_KGw #endif #if BX_SUPPORT_EVEX -bx_define_opcode(BX_IA_V512_VADDPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VADDSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VADDSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VADDPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VADDSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VADDSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VADDPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VADDPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VADDSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VADDSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VADDPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VADDPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VADDSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VADDSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VSUBSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VSUBSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VSUBSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VSUBSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VSUBPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VSUBPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VSUBSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VSUBSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VSUBPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VSUBPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VSUBSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VSUBSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMULPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VMULPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMULPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VMULPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMULSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMULSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMULPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VMULPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMULPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VMULPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMULSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMULSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMULPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VMULPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMULPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VMULPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMULSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMULSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMULPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VMULPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMULPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VMULPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMULSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMULSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VDIVPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VDIVPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VDIVPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VDIVPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VDIVSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VDIVSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VDIVPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VDIVPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VDIVPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VDIVPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VDIVSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VDIVSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VDIVPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VDIVPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VDIVPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VDIVPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VDIVSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VDIVSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VDIVPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VDIVPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VDIVPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VDIVPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VDIVSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VDIVSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMINPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VMINPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMINPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VMINPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMINSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMINSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMINPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VMINPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMINPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VMINPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMINSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMINSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMINPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VMINPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMINPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VMINPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMINSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMINSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMINPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VMINPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMINPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VMINPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMINSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMINSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMAXPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VMAXPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMAXPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VMAXPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMAXSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMAXSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMAXPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VMAXPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMAXPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VMAXPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMAXSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMAXSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMAXPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VMAXPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMAXPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VMAXPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VMAXSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMAXSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMAXPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VMAXPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMAXPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VMAXPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VMAXSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMAXSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VSQRTPS_VpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VSQRTPS_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VSQRTPD_VpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VSQRTPD_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VSQRTSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VSQRTPS_VpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VSQRTPS_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VSQRTPD_VpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VSQRTPD_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VSQRTSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VSQRTPS_VpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VSQRTPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VSQRTPD_VpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VSQRTPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VSQRTSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VSQRTSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VSQRTPS_VpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VSQRTPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VSQRTPD_VpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VSQRTPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VSQRTSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VSQRTSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCMPPS_KGwHpsWpsIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VCMPPS_MASK_KGwHpsWpsIbR, BX_ISA_AVX512, OP_KGw, OP_Hps, OP_Wps, OP_Ib, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VCMPPD_KGbHpdWpdIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VCMPPD_MASK_KGbHpdWpdIbR, BX_ISA_AVX512, OP_KGb, OP_Hpd, OP_Wpd, OP_Ib, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VCMPSS_KGbHssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCMPSS_MASK_KGbHssWssIbR, BX_ISA_AVX512, OP_KGb, OP_Hss, OP_Wss, OP_Ib, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCMPSD_KGbHsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCMPSD_MASK_KGbHsdWsdIbR, BX_ISA_AVX512, OP_KGb, OP_Hsd, OP_Wsd, OP_Ib, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCMPPS_KGwHpsWpsIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VCMPPS_MASK_KGwHpsWpsIbR, BX_ISA_AVX512, OP_KGw, OP_Hps, OP_mVps, OP_Ib, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VCMPPD_KGbHpdWpdIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VCMPPD_MASK_KGbHpdWpdIbR, BX_ISA_AVX512, OP_KGb, OP_Hpd, OP_mVpd, OP_Ib, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VCMPSS_KGbHssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCMPSS_MASK_KGbHssWssIbR, BX_ISA_AVX512, OP_KGb, OP_Hss, OP_mVss, OP_Ib, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCMPSD_KGbHsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCMPSD_MASK_KGbHsdWsdIbR, BX_ISA_AVX512, OP_KGb, OP_Hsd, OP_mVsd, OP_Ib, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VUNPCKLPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VUNPCKLPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VUNPCKLPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKLPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VUNPCKLPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKLPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VUNPCKLPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VUNPCKLPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VUNPCKLPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKLPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VUNPCKLPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKLPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VUNPCKHPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VUNPCKHPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VUNPCKHPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VUNPCKHPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VUNPCKHPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VUNPCKHPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPUNPCKLDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKLPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPUNPCKLQDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKLPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPUNPCKLDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKLPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPUNPCKLQDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKLPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPUNPCKHDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPUNPCKHQDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPUNPCKHDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPUNPCKHQDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMULLD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPMULLD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMULDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMULDQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMULUDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMULUDQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMULLD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPMULLD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMULDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMULDQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMULUDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMULUDQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_AVX512, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VssWssR, BX_ISA_AVX512, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VUCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VsdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_AVX512, OP_Vss, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VssWssR, BX_ISA_AVX512, OP_Vss, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VUCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_AVX512, OP_Vsd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VsdWsdR, BX_ISA_AVX512, OP_Vsd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VCVTUDQ2PD_VpdWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VCVTUDQ2PD_VpdWdqR, BX_ISA_AVX512, OP_Vpd, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX) // ignore the SAE bx_define_opcode(BX_IA_V512_VCVTUDQ2PS_VpsWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VCVTUDQ2PS_VpsWdqR, BX_ISA_AVX512, OP_Vps, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX) bx_define_opcode(BX_IA_V512_VCVTUDQ2PD_VpdWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VCVTUDQ2PD_MASK_VpdWdqR, BX_ISA_AVX512, OP_Vpd, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX) // ignore the SAE bx_define_opcode(BX_IA_V512_VCVTUDQ2PS_VpsWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VCVTUDQ2PS_MASK_VpsWdqR, BX_ISA_AVX512, OP_Vps, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VCVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2SD_VsdWssR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2SS_VssWsdR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2SD_VsdWssR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2SS_VssWsdR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VCVTPS2PD_VpdWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VCVTPS2PD_VpdWpsR, BX_ISA_AVX512, OP_Vpd, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX) bx_define_opcode(BX_IA_V512_VCVTPD2PS_VpsWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VCVTPD2PS_VpsWpdR, BX_ISA_AVX512, OP_Vps, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VCVTSS2SD_VsdWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2SD_MASK_VsdWssR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTSD2SS_VssWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2SS_MASK_VssWsdR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSS2SD_VsdWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2SD_MASK_VsdWssR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSD2SS_VssWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2SS_MASK_VssWsdR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VCVTPS2PD_VpdWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VCVTPS2PD_MASK_VpdWpsR, BX_ISA_AVX512, OP_Vpd, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX) bx_define_opcode(BX_IA_V512_VCVTPD2PS_VpsWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VCVTPD2PS_MASK_VpsWpdR, BX_ISA_AVX512, OP_Vps, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX) @@ -2603,60 +2603,60 @@ bx_define_opcode(BX_IA_V512_VCVTTPD2DQ_VdqWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_M bx_define_opcode(BX_IA_V512_VCVTPH2PS_VpsWps, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VCVTPH2PS_VpsWps_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VCVTPH2PS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVAPS_VpsWps, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVAPS_VpsWps_Kmask, &BX_CPU_C::VMOVAPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVAPS_WpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVAPS_WpsVps_Kmask, &BX_CPU_C::VMOVAPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Wps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVAPS_VpsWps, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVAPS_VpsWps_Kmask, &BX_CPU_C::VMOVAPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVAPS_WpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_mVps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVAPS_WpsVps_Kmask, &BX_CPU_C::VMOVAPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_mVps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVAPD_VpdWpd_Kmask, &BX_CPU_C::VMOVAPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVAPD_WpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVAPD_WpdVpd_Kmask, &BX_CPU_C::VMOVAPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVAPD_VpdWpd_Kmask, &BX_CPU_C::VMOVAPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVAPD_WpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_mVpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVAPD_WpdVpd_Kmask, &BX_CPU_C::VMOVAPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_mVpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVUPS_VpsWps_Kmask, &BX_CPU_C::VMOVUPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVUPS_WpsVps, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVUPS_WpsVps_Kmask, &BX_CPU_C::VMOVUPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Wps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVUPS_VpsWps_Kmask, &BX_CPU_C::VMOVUPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVUPS_WpsVps, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_mVps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVUPS_WpsVps_Kmask, &BX_CPU_C::VMOVUPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_mVps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVUPD_VpdWpd, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVUPD_VpdWpd_Kmask, &BX_CPU_C::VMOVUPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVUPD_WpdVpd, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVUPD_WpdVpd_Kmask, &BX_CPU_C::VMOVUPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVUPD_VpdWpd, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVUPD_VpdWpd_Kmask, &BX_CPU_C::VMOVUPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVUPD_WpdVpd, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_mVpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVUPD_WpdVpd_Kmask, &BX_CPU_C::VMOVUPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_mVpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSD_VsdHpdWsd, NULL, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VMOVSS_VssHpsWss, NULL, &BX_CPU_C::VMOVSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VMOVSD_WsdHpdVsd, NULL, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Wsd, OP_Hpd, OP_Vsd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VMOVSS_WssHpsVss, NULL, &BX_CPU_C::VMOVSS_VssHpsWssR, BX_ISA_AVX512, OP_Wss, OP_Hps, OP_Vss, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VMOVSD_VsdHpdWsd, NULL, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VMOVSS_VssHpsWss, NULL, &BX_CPU_C::VMOVSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VMOVSD_WsdHpdVsd, NULL, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_ISA_AVX512, OP_mVsd, OP_Hpd, OP_Vsd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VMOVSS_WssHpsVss, NULL, &BX_CPU_C::VMOVSS_VssHpsWssR, BX_ISA_AVX512, OP_mVss, OP_Hps, OP_Vss, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VMOVSD_VsdWsd, &BX_CPU_C::MOVSD_VsdWsdM, NULL, BX_ISA_AVX512, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSS_VssWss, &BX_CPU_C::MOVSS_VssWssM, NULL, BX_ISA_AVX512, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSD_WsdVsd, &BX_CPU_C::MOVSD_WsdVsdM, NULL, BX_ISA_AVX512, OP_Wsd, OP_Vsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSS_WssVss, &BX_CPU_C::MOVSS_WssVssM, NULL, BX_ISA_AVX512, OP_Wss, OP_Vss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSD_VsdWsd, &BX_CPU_C::MOVSD_VsdWsdM, NULL, BX_ISA_AVX512, OP_Vsd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSS_VssWss, &BX_CPU_C::MOVSS_VssWssM, NULL, BX_ISA_AVX512, OP_Vss, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSD_WsdVsd, &BX_CPU_C::MOVSD_WsdVsdM, NULL, BX_ISA_AVX512, OP_mVsd, OP_Vsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSS_WssVss, &BX_CPU_C::MOVSS_WssVssM, NULL, BX_ISA_AVX512, OP_mVss, OP_Vss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSD_VsdHpdWsd_Kmask, NULL, &BX_CPU_C::VMOVSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VMOVSS_VssHpsWss_Kmask, NULL, &BX_CPU_C::VMOVSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VMOVSD_WsdHpdVsd_Kmask, NULL, &BX_CPU_C::VMOVSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Wsd, OP_Hpd, OP_Vsd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VMOVSS_WssHpsVss_Kmask, NULL, &BX_CPU_C::VMOVSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Wss, OP_Hps, OP_Vss, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VMOVSD_VsdHpdWsd_Kmask, NULL, &BX_CPU_C::VMOVSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VMOVSS_VssHpsWss_Kmask, NULL, &BX_CPU_C::VMOVSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VMOVSD_WsdHpdVsd_Kmask, NULL, &BX_CPU_C::VMOVSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_mVsd, OP_Hpd, OP_Vsd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VMOVSS_WssHpsVss_Kmask, NULL, &BX_CPU_C::VMOVSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_mVss, OP_Hps, OP_Vss, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VMOVSD_VsdWsd_Kmask, &BX_CPU_C::VMOVSD_MASK_VsdWsdM, NULL, BX_ISA_AVX512, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSS_VssWss_Kmask, &BX_CPU_C::VMOVSS_MASK_VssWssM, NULL, BX_ISA_AVX512, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSD_WsdVsd_Kmask, &BX_CPU_C::VMOVSD_MASK_WsdVsdM, NULL, BX_ISA_AVX512, OP_Wsd, OP_Vsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSS_WssVss_Kmask, &BX_CPU_C::VMOVSS_MASK_WssVssM, NULL, BX_ISA_AVX512, OP_Wss, OP_Vss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSD_VsdWsd_Kmask, &BX_CPU_C::VMOVSD_MASK_VsdWsdM, NULL, BX_ISA_AVX512, OP_Vsd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSS_VssWss_Kmask, &BX_CPU_C::VMOVSS_MASK_VssWssM, NULL, BX_ISA_AVX512, OP_Vss, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSD_WsdVsd_Kmask, &BX_CPU_C::VMOVSD_MASK_WsdVsdM, NULL, BX_ISA_AVX512, OP_mVsd, OP_Vsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSS_WssVss_Kmask, &BX_CPU_C::VMOVSS_MASK_WssVssM, NULL, BX_ISA_AVX512, OP_mVss, OP_Vss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPABSD_VdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPABSD_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPABSQ_VdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPABSQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPABSD_VdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPABSD_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPABSQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPABSQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPABSD_VdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPABSD_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPABSQ_VdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPABSQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPABSD_VdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPABSD_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPABSQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPABSQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVNTPS_MpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_Wps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVNTPD_MpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVNTDQ_MdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVNTPS_MpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_mVps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVNTPD_MpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_mVpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVNTDQ_MdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_mVdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPCMPEQD_KGwHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPCMPEQD_MASK_KGwHdqWdqR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPCMPEQQ_KGbHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPCMPEQQ_MASK_KGbHdqWdqR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPCMPGTD_KGwHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPCMPGTD_MASK_KGwHdqWdqR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPCMPGTQ_KGbHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPCMPGTQ_MASK_KGbHdqWdqR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPCMPEQD_KGwHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPCMPEQD_MASK_KGwHdqWdqR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPCMPEQQ_KGbHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPCMPEQQ_MASK_KGbHdqWdqR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPCMPGTD_KGwHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPCMPGTD_MASK_KGwHdqWdqR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPCMPGTQ_KGbHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPCMPGTQ_MASK_KGbHdqWdqR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) bx_define_opcode(BX_IA_V512_VPSRLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPSRLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) @@ -2668,46 +2668,46 @@ bx_define_opcode(BX_IA_V512_VPSLLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::V bx_define_opcode(BX_IA_V512_VPSLLD_VdqHdqWdq_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPSLLQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPSRLD_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSRLD_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRLQ_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSRLQ_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSLLD_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSLLD_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSLLQ_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSLLQ_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRLD_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSRLD_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRLQ_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSRLQ_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSLLD_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSLLD_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSLLQ_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSLLQ_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRLD_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSRLD_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRLQ_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSRLQ_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSLLD_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSLLD_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSLLQ_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSLLQ_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRLD_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSRLD_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRLQ_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSRLQ_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSLLD_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSLLD_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSLLQ_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSLLQ_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMQ_VdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMQ_MASK_VdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMPD_VpdWpdIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMQ_MASK_VdqWdqIbR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPERMQ_VdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMQ_MASK_VdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPERMPD_VpdWpdIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMQ_MASK_VdqWdqIbR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VSHUFPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VSHUFPS_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VSHUFPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VSHUFPD_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VSHUFPS_VpsHpsWpsIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VSHUFPS_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VSHUFPD_VpdHpdWpdIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VSHUFPD_MASK_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VSHUFPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VSHUFPS_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VSHUFPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VSHUFPD_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VSHUFPS_VpsHpsWpsIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VSHUFPS_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VSHUFPD_VpdHpdWpdIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VSHUFPD_MASK_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMILPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMILPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMILPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMILPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMILPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMILPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPERMILPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPERMILPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMILPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPERMILPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPERMILPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMILPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMILPS_VpsWpsIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMILPD_VpdWpdIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMILPD_VpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMILPS_VpsWpsIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_MASK_VpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMILPD_VpdWpdIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMILPD_MASK_VpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPERMILPS_VpsWpsIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPERMILPD_VpdWpdIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMILPD_VpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPERMILPS_VpsWpsIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_MASK_VpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPERMILPD_VpdWpdIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMILPD_MASK_VpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSHUFD_VdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_MASK_VpsWpsIbR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSHUFD_VdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMILPS_MASK_VpsWpsIbR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPBROADCASTD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_VdqWdR, BX_ISA_AVX512, OP_Vdq, OP_Wd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPBROADCASTQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWqR, BX_ISA_AVX512, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPBROADCASTD_VdqWd_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_MASK_VdqWdR, BX_ISA_AVX512, OP_Vdq, OP_Wd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPBROADCASTQ_VdqWq_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_MASK_VdqWqR, BX_ISA_AVX512, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPBROADCASTD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_VdqWdR, BX_ISA_AVX512, OP_Vdq, OP_mVdq32, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPBROADCASTQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWqR, BX_ISA_AVX512, OP_Vdq, OP_mVdq64, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPBROADCASTD_VdqWd_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_MASK_VdqWdR, BX_ISA_AVX512, OP_Vdq, OP_mVdq32, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPBROADCASTQ_VdqWq_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_MASK_VdqWqR, BX_ISA_AVX512, OP_Vdq, OP_mVdq64, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VBROADCASTSS_VpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_VdqWdR, BX_ISA_AVX512, OP_Vps, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VBROADCASTSD_VpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWqR, BX_ISA_AVX512, OP_Vpd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VBROADCASTSS_VpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_MASK_VdqWdR, BX_ISA_AVX512, OP_Vps, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VBROADCASTSD_VpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_MASK_VdqWqR, BX_ISA_AVX512, OP_Vpd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VBROADCASTSS_VpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_VdqWdR, BX_ISA_AVX512, OP_Vps, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VBROADCASTSD_VpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWqR, BX_ISA_AVX512, OP_Vpd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VBROADCASTSS_VpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_MASK_VdqWdR, BX_ISA_AVX512, OP_Vps, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VBROADCASTSD_VpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_MASK_VdqWqR, BX_ISA_AVX512, OP_Vpd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VBROADCASTF32x4_VpsWps, &BX_CPU_C::VBROADCASTF128_VdqMdq, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VBROADCASTF32x4_VpsWps_Kmask, &BX_CPU_C::VBROADCASTF32x4_MASK_VpsMps, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) @@ -2722,7 +2722,7 @@ bx_define_opcode(BX_IA_V512_VBROADCASTI64x4_VdqWdq_Kmask, &BX_CPU_C::VBROADCASTF bx_define_opcode(BX_IA_V512_VMOVQ_WqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX512, OP_Wq, OP_Vq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VMOVQ_VqWq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX512, OP_Vq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wss, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVss, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_ISA_AVX512, OP_Ed, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF32x4_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) @@ -2751,12 +2751,12 @@ bx_define_opcode(BX_IA_V512_VMOVLPD_VpdHpdMq, &BX_CPU_C::VMOVLPD_VpdHpdMq, &BX_C bx_define_opcode(BX_IA_V512_VMOVHPD_VpdHpdMq, &BX_CPU_C::VMOVHPD_VpdHpdMq, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VMOVDDUP_VpdWpd_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSLDUP_VpsWps_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVSHDUP_VpsWps_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSLDUP_VpsWps_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVSHDUP_VpsWps_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVQB_WdqVdq, &BX_CPU_C::VPMOVQB_MASK_WdqVdqM, &BX_CPU_C::VPMOVQB_WdqVdqR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVDB_WdqVdq, &BX_CPU_C::VPMOVDB_MASK_WdqVdqM, &BX_CPU_C::VPMOVDB_WdqVdqR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) @@ -2819,129 +2819,129 @@ bx_define_opcode(BX_IA_V512_VPMOVZXWQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Quarter_Vect bx_define_opcode(BX_IA_V512_VPMOVZXDQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXDQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) // VexW alias -bx_define_opcode(BX_IA_V512_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPADDD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPADDD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPADDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPADDQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPADDD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPADDD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPADDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPADDQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSUBD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSUBD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSUBQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSUBQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSUBD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSUBD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSUBQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSUBQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPANDD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPANDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPANDD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPANDD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPANDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPANDQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPANDD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPANDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPANDD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPANDD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPANDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPANDQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPANDND_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPANDNQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPANDND_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPANDND_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPANDNQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPANDNQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPANDND_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPANDNQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPANDND_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPANDND_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPANDNQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPANDNQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPORD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPORQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPORD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPORD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPORQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPORQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPORD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPORQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPORD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPORD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPORQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPORQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPXORD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPXORQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPXORD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPXORD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPXORQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPXORQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPXORD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPXORQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPXORD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPXORD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPXORQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPXORQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMAXSQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMAXSQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMAXSD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPMAXSD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMAXSQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMAXSQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMAXSQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMAXSQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMAXSD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPMAXSD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMAXSQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMAXSQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMAXUQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMAXUQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMAXUD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPMAXUD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMAXUQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMAXUQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMAXUQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMAXUQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMAXUD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPMAXUD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMAXUQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMAXUQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMINSQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMINSQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMINSD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPMINSD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMINSQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMINSQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMINSQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMINSQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMINSD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPMINSD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMINSQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMINSQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMINUQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMINUQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMINUD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPMINUD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPMINUQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMINUQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMINUQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMINUQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMINUD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPMINUD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMINUQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMINUQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VALIGND_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VALIGND_MASK_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VALIGNQ_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VALIGNQ_MASK_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VALIGND_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VALIGND_MASK_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VALIGNQ_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VALIGNQ_MASK_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRLVD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSRLVD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSRLVQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRAVD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSRAVD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRAVQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSRAVQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSLLVD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSLLVD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSLLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSLLVQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPROLVD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPROLVD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPROLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPROLVQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPRORVD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPRORVD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPRORVQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPRORVQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRLVD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSRLVD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSRLVQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRAVD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSRAVD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRAVQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSRAVQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSLLVD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSLLVD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSLLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSLLVQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPROLVD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPROLVD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPROLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPROLVQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPRORVD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPRORVD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPRORVQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPRORVQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRLVD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSRLVD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRLVQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSRLVQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRAVD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSRAVD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRAVQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSRAVQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSLLVD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSLLVD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSLLVQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSLLVQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPROLVD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPROLVD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPROLVQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPROLVQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPRORVD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPRORVD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPRORVQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPRORVQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRLVD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSRLVD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRLVQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSRLVQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRAVD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSRAVD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRAVQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSRAVQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSLLVD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSLLVD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSLLVQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSLLVQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPROLVD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPROLVD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPROLVQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPROLVQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPRORVD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPRORVD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPRORVQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPRORVQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPSRAQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPSRAD_VdqHdqWdq_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPSRAQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPSRAQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPSRAD_VdqHdqWdq_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPSRAQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPSRAD_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSRAD_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRAQ_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSRAQ_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPRORD_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPRORD_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPRORQ_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPRORQ_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPROLD_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPROLD_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPROLQ_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPROLQ_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRAD_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPSRAD_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRAQ_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPSRAQ_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPRORD_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPRORD_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPRORQ_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPRORQ_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPROLD_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPROLD_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPROLQ_UdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPROLQ_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRAD_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSRAD_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPSRAQ_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSRAQ_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPRORD_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPRORD_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPRORQ_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPRORQ_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPROLD_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPROLD_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPROLQ_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPROLQ_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRAD_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPSRAD_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPSRAQ_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPSRAQ_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPRORD_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPRORD_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPRORQ_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPRORQ_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPROLD_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPROLD_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPROLQ_UdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPROLQ_MASK_UdqIb, BX_ISA_AVX512, OP_Hdq, OP_mVdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VMOVDQU32_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQU64_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQU32_VdqWdq_Kmask, &BX_CPU_C::VMOVUPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQU64_VdqWdq_Kmask, &BX_CPU_C::VMOVUPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQU32_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQU64_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQU32_VdqWdq_Kmask, &BX_CPU_C::VMOVUPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQU64_VdqWdq_Kmask, &BX_CPU_C::VMOVUPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQU32_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQU64_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQU32_WdqVdq_Kmask, &BX_CPU_C::VMOVUPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQU64_WdqVdq_Kmask, &BX_CPU_C::VMOVUPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQU32_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_mVdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQU64_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_mVdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQU32_WdqVdq_Kmask, &BX_CPU_C::VMOVUPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_mVdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQU64_WdqVdq_Kmask, &BX_CPU_C::VMOVUPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_mVdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQA32_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQA64_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQA32_VdqWdq_Kmask, &BX_CPU_C::VMOVAPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQA64_VdqWdq_Kmask, &BX_CPU_C::VMOVAPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQA32_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQA64_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQA32_VdqWdq_Kmask, &BX_CPU_C::VMOVAPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQA64_VdqWdq_Kmask, &BX_CPU_C::VMOVAPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQA32_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQA64_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQA32_WdqVdq_Kmask, &BX_CPU_C::VMOVAPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VMOVDQA64_WdqVdq_Kmask, &BX_CPU_C::VMOVAPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQA32_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_mVdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQA64_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_mVdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQA32_WdqVdq_Kmask, &BX_CPU_C::VMOVAPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_mVdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VMOVDQA64_WdqVdq_Kmask, &BX_CPU_C::VMOVAPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_mVdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VGETEXPPS_VpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VGETEXPPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VGETEXPPD_VpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VGETEXPPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VGETEXPSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VGETEXPSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VGETEXPSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VGETEXPSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VGETEXPPS_VpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VGETEXPPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VGETEXPPD_VpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VGETEXPPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VGETEXPSS_VssHpsWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VGETEXPSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VGETEXPSD_VsdHpdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VGETEXPSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VGETMANTPS_VpsWpsIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VGETMANTPS_MASK_VpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_Ib, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VGETMANTPD_VpdWpdIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VGETMANTPD_MASK_VpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VGETMANTSS_VssHpsWssIb_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VGETMANTSS_MASK_VssHpsWssIbR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Wss, OP_Ib, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VGETMANTSD_VsdHpdWsdIb_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VGETMANTSD_MASK_VsdHpdWsdIbR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Wsd, OP_Ib, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VGETMANTPS_VpsWpsIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VGETMANTPS_MASK_VpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_Ib, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VGETMANTPD_VpdWpdIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VGETMANTPD_MASK_VpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VGETMANTSS_VssHpsWssIb_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VGETMANTSS_MASK_VssHpsWssIbR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_Ib, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VGETMANTSD_VsdHpdWsdIb_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VGETMANTSD_MASK_VsdHpdWsdIbR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_Ib, BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VCVTTPS2UDQ_VdqWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VCVTTPS2UDQ_VdqWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX) bx_define_opcode(BX_IA_V512_VCVTTPD2UDQ_VdqWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VCVTTPD2UDQ_VdqWpdR, BX_ISA_AVX512, OP_Vdq, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX) @@ -2953,160 +2953,160 @@ bx_define_opcode(BX_IA_V512_VCVTPD2UDQ_VdqWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ bx_define_opcode(BX_IA_V512_VCVTPS2UDQ_VdqWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VCVTPS2UDQ_MASK_VdqWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX) bx_define_opcode(BX_IA_V512_VCVTPD2UDQ_VdqWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VCVTPD2UDQ_MASK_VdqWpdR, BX_ISA_AVX512, OP_Vdq, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADD231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADD132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_Wss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_Wsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_Wss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_Wsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_mVss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_mVsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD132SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_Wss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD132SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_Wsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD213SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_Wss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD213SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_Wsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD231SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADD231SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD132SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD132SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD213SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_mVss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD213SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_mVsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD231SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMADD231SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMADDSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMADDSUB231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMADDSUB231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUBADD231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUBADD231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFMSUB231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFMSUB132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_Wss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_Wsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_Wss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_Wsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_mVss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_mVsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB132SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_Wss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB132SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_Wsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB213SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_Wss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB213SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_Wsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB231SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFMSUB231SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB132SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB132SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB213SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_mVss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB213SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_mVsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB231SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFMSUB231SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMADD231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMADD132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_Wss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_Wsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_Wss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_Wsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_mVss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_mVsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD132SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_Wss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD132SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_Wsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD213SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_Wss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD213SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_Wsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD231SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMADD231SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD132SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD132SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD213SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_mVss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD213SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_mVsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD231SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMADD231SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB132PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB132PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB213PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB213PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB231PS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB231PD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_Wss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMSUB132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_Wsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMSUB213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_Wss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMSUB213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_Wsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMSUB231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMSUB231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMSUB132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMSUB132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMSUB213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_mVss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMSUB213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_mVsd, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMSUB231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VFNMSUB231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFNMSUB132SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_Wss, OP_Hss, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB132SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_Wsd, OP_Hsd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB213SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_Wss, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB213SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_Wsd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB231SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFNMSUB231SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB132SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB132SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB213SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Vss, OP_mVss, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB213SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Vsd, OP_mVsd, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB231SS_VpsHssWss_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFNMSUB231SD_VpdHsdWsd_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VPCMPD_KGwHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPCMPD_MASK_KGwHdqWdqIbR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPCMPQ_KGbHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPCMPQ_MASK_KGbHdqWdqIbR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPCMPUD_KGwHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPCMPUD_MASK_KGwHdqWdqIbR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPCMPUQ_KGbHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPCMPUQ_MASK_KGbHdqWdqIbR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPCMPD_KGwHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPCMPD_MASK_KGwHdqWdqIbR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_mVdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPCMPQ_KGbHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPCMPQ_MASK_KGbHdqWdqIbR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_mVdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPCMPUD_KGwHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPCMPUD_MASK_KGwHdqWdqIbR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_mVdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPCMPUQ_KGbHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPCMPUQ_MASK_KGbHdqWdqIbR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_mVdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPTESTMD_KGwHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPTESTMD_MASK_KGwHdqWdqR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPTESTMQ_KGbHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPTESTMQ_MASK_KGbHdqWdqR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPTESTNMD_KGwHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPTESTNMD_MASK_KGwHdqWdqR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPTESTNMQ_KGbHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPTESTNMQ_MASK_KGbHdqWdqR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPTESTMD_KGwHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPTESTMD_MASK_KGwHdqWdqR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPTESTMQ_KGbHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPTESTMQ_MASK_KGbHdqWdqR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPTESTNMD_KGwHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPTESTNMD_MASK_KGwHdqWdqR, BX_ISA_AVX512, OP_KGw, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPTESTNMQ_KGbHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPTESTNMQ_MASK_KGbHdqWdqR, BX_ISA_AVX512, OP_KGb, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPTERNLOGD_VdqHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPTERNLOGD_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPTERNLOGQ_VdqHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPTERNLOGQ_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPTERNLOGD_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPTERNLOGD_MASK_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPTERNLOGQ_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPTERNLOGQ_MASK_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPTERNLOGD_VdqHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPTERNLOGD_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPTERNLOGQ_VdqHdqWdqIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPTERNLOGQ_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPTERNLOGD_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VPTERNLOGD_MASK_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPTERNLOGQ_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPTERNLOGQ_MASK_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) bx_define_opcode(BX_IA_V512_VGATHERDPS_VpsVSib, &BX_CPU_C::VGATHERDPS_MASK_VpsVSib, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_Vps, OP_VSib, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VGATHERDPD_VpdVSib, &BX_CPU_C::VGATHERDPD_MASK_VpdVSib, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_Vpd, OP_VSib, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) @@ -3128,10 +3128,10 @@ bx_define_opcode(BX_IA_V512_VSCATTERDQ_VSibVdq, &BX_CPU_C::VSCATTERDPD_MASK_VSib bx_define_opcode(BX_IA_V512_VSCATTERQD_VSibVdq, &BX_CPU_C::VSCATTERQPS_MASK_VSibVps, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_VSib, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VSCATTERQQ_VSibVdq, &BX_CPU_C::VSCATTERQPD_MASK_VSibVpd, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_VSib, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VBLENDMPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VBLENDMPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VBLENDMPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VBLENDMPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPBLENDMD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VBLENDMPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPBLENDMQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VBLENDMPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VBLENDMPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VBLENDMPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VBLENDMPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VBLENDMPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPBLENDMD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VBLENDMPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPBLENDMQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VBLENDMPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) bx_define_opcode(BX_IA_V512_VSHUFI32x4_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VSHUFF32x4_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) bx_define_opcode(BX_IA_V512_VSHUFI64x2_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VSHUFF64x2_MASK_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE) @@ -3158,13 +3158,13 @@ bx_define_opcode(BX_IA_V512_VCOMPRESSQ_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_C bx_define_opcode(BX_IA_V512_VCOMPRESSD_WdqVdq_Kmask, &BX_CPU_C::VCOMPRESSPS_MASK_WpsVps, &BX_CPU_C::VCOMPRESSPS_MASK_WpsVps, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VCOMPRESSQ_WdqVdq_Kmask, &BX_CPU_C::VCOMPRESSPD_MASK_WpdVpd, &BX_CPU_C::VCOMPRESSPD_MASK_WpdVpd, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VFIXUPIMMSS_VssHssWssIb_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFIXUPIMMSS_MASK_VssHssWssIbR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_Wss, OP_Ib, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFIXUPIMMSD_VsdHsdWsdIb_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFIXUPIMMSD_MASK_VsdHsdWsdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_Wsd, OP_Ib, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFIXUPIMMSS_VssHssWssIb_Kmask, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFIXUPIMMSS_MASK_VssHssWssIbR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Ib, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFIXUPIMMSD_VsdHsdWsdIb_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFIXUPIMMSD_MASK_VsdHsdWsdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Ib, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFIXUPIMMPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFIXUPIMMPS_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Ib, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFIXUPIMMPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFIXUPIMMPD_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Ib, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFIXUPIMMPS_VpsHpsWpsIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFIXUPIMMPS_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Ib, BX_PREPARE_EVEX) -bx_define_opcode(BX_IA_V512_VFIXUPIMMPD_VpdHpdWpdIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFIXUPIMMPD_MASK_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Ib, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFIXUPIMMPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFIXUPIMMPS_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Ib, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFIXUPIMMPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFIXUPIMMPD_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Ib, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFIXUPIMMPS_VpsHpsWpsIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFIXUPIMMPS_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Ib, BX_PREPARE_EVEX) +bx_define_opcode(BX_IA_V512_VFIXUPIMMPD_VpdHpdWpdIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFIXUPIMMPD_MASK_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Ib, BX_PREPARE_EVEX) bx_define_opcode(BX_IA_V512_VPERMT2D_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPERMT2PS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) bx_define_opcode(BX_IA_V512_VPERMT2Q_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPERMT2PD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) @@ -3189,15 +3189,15 @@ bx_define_opcode(BX_IA_V512_VPBROADCASTQ_VdqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::V bx_define_opcode(BX_IA_V512_VPBROADCASTD_VdqEd_Kmask, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VPBROADCASTD_MASK_VdqEdR, BX_ISA_AVX512, OP_Vdq, OP_Ed, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPBROADCASTQ_VdqEq_Kmask, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VPBROADCASTQ_MASK_VdqEqR, BX_ISA_AVX512, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_ISA_AVX512, OP_Gd, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, BX_ISA_AVX512, OP_Gq, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_ISA_AVX512, OP_Gd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, BX_ISA_AVX512, OP_Gq, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_ISA_AVX512, OP_Gd, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, BX_ISA_AVX512, OP_Gq, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_ISA_AVX512, OP_Gd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, BX_ISA_AVX512, OP_Gq, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_ISA_AVX512, OP_Gd, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, BX_ISA_AVX512, OP_Gq, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_ISA_AVX512, OP_Gd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GqWsdR, BX_ISA_AVX512, OP_Gq, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_ISA_AVX512, OP_Gd, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, BX_ISA_AVX512, OP_Gq, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_ISA_AVX512, OP_Gd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GqWsdR, BX_ISA_AVX512, OP_Gq, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VMOVD_VdqEd, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVD_VdqEdR, BX_ISA_AVX512, OP_Vdq, OP_Ed, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VMOVQ_VdqEq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VdqEqR, BX_ISA_AVX512, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) @@ -3214,15 +3214,15 @@ bx_define_opcode(BX_IA_V512_VCVTUSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCV bx_define_opcode(BX_IA_V512_VCVTUSI2SD_VsdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTUSI2SD_VsdEdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Ed, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) // ignore the SAE bx_define_opcode(BX_IA_V512_VCVTUSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTUSI2SD_VsdEqR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Eq, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTSS2USI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2USI_GdWssR, BX_ISA_AVX512, OP_Gd, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTSS2USI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2USI_GqWssR, BX_ISA_AVX512, OP_Gq, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTSD2USI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2USI_GdWsdR, BX_ISA_AVX512, OP_Gd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTSD2USI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2USI_GqWsdR, BX_ISA_AVX512, OP_Gq, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSS2USI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2USI_GdWssR, BX_ISA_AVX512, OP_Gd, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSS2USI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2USI_GqWssR, BX_ISA_AVX512, OP_Gq, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSD2USI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2USI_GdWsdR, BX_ISA_AVX512, OP_Gd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTSD2USI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2USI_GqWsdR, BX_ISA_AVX512, OP_Gq, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTTSS2USI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTTSS2USI_GdWssR, BX_ISA_AVX512, OP_Gd, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTTSS2USI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTTSS2USI_GqWssR, BX_ISA_AVX512, OP_Gq, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTTSD2USI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTTSD2USI_GdWsdR, BX_ISA_AVX512, OP_Gd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VCVTTSD2USI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTTSD2USI_GqWsdR, BX_ISA_AVX512, OP_Gq, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTTSS2USI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTTSS2USI_GdWssR, BX_ISA_AVX512, OP_Gd, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTTSS2USI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTTSS2USI_GqWssR, BX_ISA_AVX512, OP_Gq, OP_mVss, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTTSD2USI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTTSD2USI_GdWsdR, BX_ISA_AVX512, OP_Gd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VCVTTSD2USI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTTSD2USI_GqWsdR, BX_ISA_AVX512, OP_Gq, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST) // VexW64 aliased #endif // BX_SUPPORT_EVEX