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Do not try to update access/dirty bit if it was already set

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This commit is contained in:
Stanislav Shwartsman 2008-01-20 17:46:02 +00:00
parent 25602bb79e
commit 932d758547
2 changed files with 17 additions and 13 deletions
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10
bochs/cpu/protect_ctrl.cc
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// $Id: protect_ctrl.cc,v 1.71 2008-01-10 19:37:55 sshwarts Exp $ // $Id: protect_ctrl.cc,v 1.72 2008-01-20 17:46:02 sshwarts Exp $
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2001 MandrakeSoft S.A. // Copyright (C) 2001 MandrakeSoft S.A.
@ -472,9 +472,11 @@ void BX_CPU_C::LTR_Ew(bxInstruction_c *i)
BX_ASSERT((BX_CPU_THIS_PTR tr.cache.type & 2) == 0); BX_ASSERT((BX_CPU_THIS_PTR tr.cache.type & 2) == 0);
/* mark as busy */ /* mark as busy */
dword2 |= 0x00000200; /* set busy bit */ if (!(dword2 & 0x0200)) {
access_linear(BX_CPU_THIS_PTR gdtr.base + selector.index*8 + 4, 4, 0, dword2 |= 0x0200; /* set busy bit */
BX_WRITE, &dword2); access_linear(BX_CPU_THIS_PTR gdtr.base + selector.index*8 + 4, 4, 0,
BX_WRITE, &dword2);
}
} }
void BX_CPU_C::VERR_Ew(bxInstruction_c *i) void BX_CPU_C::VERR_Ew(bxInstruction_c *i)

20
bochs/cpu/segment_ctrl_pro.cc
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// $Id: segment_ctrl_pro.cc,v 1.77 2007-11-30 08:49:12 sshwarts Exp $ // $Id: segment_ctrl_pro.cc,v 1.78 2008-01-20 17:46:02 sshwarts Exp $
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2001 MandrakeSoft S.A. // Copyright (C) 2001 MandrakeSoft S.A.
@ -101,14 +101,16 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1; BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
/* now set accessed bit in descriptor */ /* now set accessed bit in descriptor */
dword2 |= 0x0100; if (!(dword2 & 0x0100)) {
if (ss_selector.ti == 0) { /* GDT */ dword2 |= 0x0100;
access_linear(BX_CPU_THIS_PTR gdtr.base + ss_selector.index*8 + 4, 4, 0, if (ss_selector.ti == 0) { /* GDT */
BX_WRITE, &dword2); access_linear(BX_CPU_THIS_PTR gdtr.base + ss_selector.index*8 + 4, 4, 0,
} BX_WRITE, &dword2);
else { /* LDT */ }
access_linear(BX_CPU_THIS_PTR ldtr.cache.u.system.base + ss_selector.index*8 + 4, 4, 0, else { /* LDT */
BX_WRITE, &dword2); access_linear(BX_CPU_THIS_PTR ldtr.cache.u.system.base + ss_selector.index*8 + 4, 4, 0,
BX_WRITE, &dword2);
}
} }
return; return;