define CPU feature's enum together with feature name in one place
This commit is contained in:
Stanislav Shwartsman
parent
e7910a30a0
commit
8e6bdcb4d9
@ -53,7 +53,6 @@ core2_penryn_t9600_t::core2_penryn_t9600_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
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#if BX_SUPPORT_VMX
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enable_cpu_extension(BX_ISA_VMX);
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#endif
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enable_cpu_extension(BX_ISA_SMX);
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enable_cpu_extension(BX_ISA_CLFLUSH);
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enable_cpu_extension(BX_ISA_DEBUG_EXTENSIONS);
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enable_cpu_extension(BX_ISA_VME);
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@ -108,7 +108,6 @@ corei3_cnl_t::corei3_cnl_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
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enable_cpu_extension(BX_ISA_AVX512_DQ);
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enable_cpu_extension(BX_ISA_AVX512_CD);
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enable_cpu_extension(BX_ISA_AVX512_BW);
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enable_cpu_extension(BX_ISA_AVX512_VL);
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enable_cpu_extension(BX_ISA_AVX512_IFMA52);
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enable_cpu_extension(BX_ISA_AVX512_VBMI);
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#endif
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@ -109,7 +109,6 @@ corei7_icelake_t::corei7_icelake_t(BX_CPU_C *cpu):
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enable_cpu_extension(BX_ISA_GFNI);
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enable_cpu_extension(BX_ISA_VAES_VPCLMULQDQ);
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enable_cpu_extension(BX_ISA_AVX512);
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enable_cpu_extension(BX_ISA_AVX512_VL);
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enable_cpu_extension(BX_ISA_AVX512_DQ);
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enable_cpu_extension(BX_ISA_AVX512_CD);
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enable_cpu_extension(BX_ISA_AVX512_BW);
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@ -107,7 +107,6 @@ corei7_skylake_x_t::corei7_skylake_x_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
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enable_cpu_extension(BX_ISA_AVX512_DQ);
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enable_cpu_extension(BX_ISA_AVX512_CD);
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enable_cpu_extension(BX_ISA_AVX512_BW);
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enable_cpu_extension(BX_ISA_AVX512_VL);
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#endif
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enable_cpu_extension(BX_ISA_CLFLUSHOPT);
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enable_cpu_extension(BX_ISA_CLWB);
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@ -109,7 +109,6 @@ tigerlake_t::tigerlake_t(BX_CPU_C *cpu):
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enable_cpu_extension(BX_ISA_GFNI);
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enable_cpu_extension(BX_ISA_VAES_VPCLMULQDQ);
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enable_cpu_extension(BX_ISA_AVX512);
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enable_cpu_extension(BX_ISA_AVX512_VL);
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enable_cpu_extension(BX_ISA_AVX512_DQ);
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enable_cpu_extension(BX_ISA_AVX512_CD);
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enable_cpu_extension(BX_ISA_AVX512_BW);
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@ -27,123 +27,11 @@
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#include "param_names.h"
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#include "cpuid.h"
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static const char *cpu_feature_name[] =
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{
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"386ni", // BX_ISA_386
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"x87", // BX_ISA_X87
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"486ni", // BX_ISA_486
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"pentium_ni", // BX_ISA_PENTIUM
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"p6ni", // BX_ISA_P6
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"mmx", // BX_ISA_MMX
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"3dnow!", // BX_ISA_3DNOW
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"debugext", // BX_ISA_DEBUG_EXTENSIONS
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"vme", // BX_ISA_VME
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"pse", // BX_ISA_PSE
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"pae", // BX_ISA_PAE
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"pge", // BX_ISA_PGE
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"pse36", // BX_ISA_PSE36
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"mtrr", // BX_ISA_MTRR
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"pat", // BX_ISA_PAT
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"legacy_syscall_sysret", // BX_ISA_SYSCALL_SYSRET_LEGACY
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"sysenter_sysexit", // BX_ISA_SYSENTER_SYSEXIT
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"clflush", // BX_ISA_CLFLUSH
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"clflushopt", // BX_ISA_CLFLUSHOPT
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"clwb", // BX_ISA_CLWB
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"cldemote", // BX_ISA_CLDEMOTE
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"sse", // BX_ISA_SSE
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"sse2", // BX_ISA_SSE2
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"sse3", // BX_ISA_SSE3
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"ssse3", // BX_ISA_SSSE3
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"sse4_1", // BX_ISA_SSE4_1
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"sse4_2", // BX_ISA_SSE4_2
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"popcnt", // BX_ISA_POPCNT
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"mwait", // BX_ISA_MONITOR_MWAIT
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"mwaitx", // BX_ISA_MONITORX_MWAITX
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"waitpkg", // BX_ISA_WAITPKG
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"vmx", // BX_ISA_VMX
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"smx", // BX_ISA_SMX
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"longmode", // BX_ISA_LONG_MODE
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"lm_lahf_sahf", // BX_ISA_LM_LAHF_SAHF
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"nx", // BX_ISA_NX
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"1g_pages", // BX_ISA_1G_PAGES
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"cmpxhg16b", // BX_ISA_CMPXCHG16B
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"rdtscp", // BX_ISA_RDTSCP
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"ffxsr", // BX_ISA_FFXSR
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"xsave", // BX_ISA_XSAVE
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"xsaveopt", // BX_ISA_XSAVEOPT
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"xsavec", // BX_ISA_XSAVEC
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"xsaves", // BX_ISA_XSAVES
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"aes_pclmulqdq", // BX_ISA_AES_PCLMULQDQ
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"vaes_vpclmulqdq", // BX_ISA_VAES_VPCLMULQDQ
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"movbe", // BX_ISA_MOVBE
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"fsgsbase", // BX_ISA_FSGSBASE
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"invpcid", // BX_ISA_INVPCID
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"avx", // BX_ISA_AVX
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"avx2", // BX_ISA_AVX2
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"avx_f16c", // BX_ISA_AVX_F16C
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"avx_fma", // BX_ISA_AVX_FMA
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"altmovcr8", // BX_ISA_ALT_MOV_CR8
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"sse4a", // BX_ISA_SSE4A
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"misaligned_sse", // BX_ISA_MISALIGNED_SSE
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"lzcnt", // BX_ISA_LZCNT
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"bmi1", // BX_ISA_BMI1
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"bmi2", // BX_ISA_BMI2
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"fma4", // BX_ISA_FMA4
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"xop", // BX_ISA_XOP
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"tbm", // BX_ISA_TBM
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"svm", // BX_ISA_SVM
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"rdrand", // BX_ISA_RDRAND
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"adx", // BX_ISA_ADX
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"smap", // BX_ISA_SMAP
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"rdseed", // BX_ISA_RDSEED
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"sha", // BX_ISA_SHA
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"sha512", // BX_ISA_SHA512
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"gfni", // BX_ISA_GFNI
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"sm3", // BX_ISA_SM3
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"sm4", // BX_ISA_SM4
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"avx512", // BX_ISA_AVX512
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"avx512cd", // BX_ISA_AVX512_CD
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"avx512pf", // BX_ISA_AVX512_PF
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"avx512er", // BX_ISA_AVX512_ER
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"avx512dq", // BX_ISA_AVX512_DQ
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"avx512bw", // BX_ISA_AVX512_BW
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"avx512vl", // BX_ISA_AVX512_VL
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"avx512vbmi", // BX_ISA_AVX512_VBMI
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"avx512vbmi2", // BX_ISA_AVX512_VBMI2
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"avx512ifma52", // BX_ISA_AVX512_IFMA52
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"avx512vpopcnt", // BX_ISA_AVX512_VPOPCNTDQ
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"avx512vnni", // BX_ISA_AVX512_VNNI
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"avx512bitalg", // BX_ISA_AVX512_BITALG
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"avx512vp2intersect", // BX_ISA_AVX512_VP2INTERSECT
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"avx512bf16", // BX_ISA_AVX512_BF16
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"avx_ifma", // BX_ISA_AVX_IFMA
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"avx_vnni", // BX_ISA_AVX_VNNI
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"avx_vnni_int8", // BX_ISA_AVX_VNNI_INT8
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"avx_vnni_int16", // BX_ISA_AVX_VNNI_INT16
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"avx_ne_convert", // BX_ISA_AVX_NE_CONVERT
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"xapic", // BX_ISA_XAPIC
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"x2apic", // BX_ISA_X2APIC
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"xapicext", // BX_ISA_XAPICEXT
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"pcid", // BX_ISA_PCID
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"smep", // BX_ISA_SMEP
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"tsc_adjust", // BX_ISA_TSC_ADJUST
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"tsc_deadline", // BX_ISA_TSC_DEADLINE
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"fopcode_deprecation", // BX_ISA_FOPCODE_DEPRECATION
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"fcs_fds_deprecation", // BX_ISA_FCS_FDS_DEPRECATION
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"fdp_deprecation", // BX_ISA_FDP_DEPRECATION
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"pku", // BX_ISA_PKU
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"pks", // BX_ISA_PKS
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"umip", // BX_ISA_UMIP
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"lass", // BX_ISA_LASS
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"rdpid", // BX_ISA_RDPID
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"tce", // BX_ISA_TCE
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"clzero", // BX_ISA_CLZERO
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"sca_mitigations", // BX_ISA_SCA_MITIGATIONS
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"cet", // BX_ISA_CET
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"wrmsrns", // BX_ISA_WRMSRNS
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"cmpccxadd", // BX_ISA_CMPCCXADD
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"serialize", // BX_ISA_SERIALIZE
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static const char *cpu_feature_name[BX_ISA_EXTENSION_LAST] = {
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#define x86_feature(isa, feature_name) #feature_name,
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#include "decoder/features.h"
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};
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#undef x86_feature
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const char *get_cpu_feature_name(unsigned feature) { return cpu_feature_name[feature]; }
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@ -2,7 +2,7 @@
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016-2020 The Bochs Project
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// Copyright (C) 2016-2023 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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@ -24,122 +24,11 @@
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// x86 Arch features
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enum x86_feature_name {
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BX_ISA_386 = 0, /* 386 or earlier instruction */
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BX_ISA_X87, /* FPU (X87) instruction */
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BX_ISA_486, /* 486 new instruction */
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BX_ISA_PENTIUM, /* Pentium new instruction */
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BX_ISA_P6, /* P6 new instruction */
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BX_ISA_MMX, /* MMX instruction */
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BX_ISA_3DNOW, /* 3DNow! instruction (AMD) */
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BX_ISA_DEBUG_EXTENSIONS, /* Debug Extensions support */
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BX_ISA_VME, /* VME support */
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BX_ISA_PSE, /* PSE support */
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BX_ISA_PAE, /* PAE support */
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BX_ISA_PGE, /* Global Pages support */
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BX_ISA_PSE36, /* PSE-36 support */
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BX_ISA_MTRR, /* MTRR support */
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BX_ISA_PAT, /* PAT support */
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BX_ISA_SYSCALL_SYSRET_LEGACY, /* SYSCALL/SYSRET in legacy mode (AMD) */
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BX_ISA_SYSENTER_SYSEXIT, /* SYSENTER/SYSEXIT instruction */
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BX_ISA_CLFLUSH, /* CLFLUSH instruction */
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BX_ISA_CLFLUSHOPT, /* CLFLUSHOPT instruction */
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BX_ISA_CLWB, /* CLWB instruction */
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BX_ISA_CLDEMOTE, /* CLDEMOTE instruction */
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BX_ISA_SSE, /* SSE instruction */
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BX_ISA_SSE2, /* SSE2 instruction */
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BX_ISA_SSE3, /* SSE3 instruction */
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BX_ISA_SSSE3, /* SSSE3 instruction */
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BX_ISA_SSE4_1, /* SSE4_1 instruction */
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BX_ISA_SSE4_2, /* SSE4_2 instruction */
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BX_ISA_POPCNT, /* POPCNT instruction */
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BX_ISA_MONITOR_MWAIT, /* MONITOR/MWAIT instruction */
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BX_ISA_MONITORX_MWAITX, /* MONITORX/MWAITX instruction (AMD) */
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BX_ISA_WAITPKG, /* TPAUSE/UMONITOR/UMWAIT instructions */
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BX_ISA_VMX, /* VMX instruction */
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BX_ISA_SMX, /* SMX instruction */
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BX_ISA_LONG_MODE, /* Long Mode (x86-64) support */
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BX_ISA_LM_LAHF_SAHF, /* Long Mode LAHF/SAHF instruction */
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BX_ISA_NX, /* No-Execute support */
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BX_ISA_1G_PAGES, /* 1Gb pages support */
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BX_ISA_CMPXCHG16B, /* CMPXCHG16B instruction */
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BX_ISA_RDTSCP, /* RDTSCP instruction */
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BX_ISA_FFXSR, /* EFER.FFXSR support */
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BX_ISA_XSAVE, /* XSAVE/XRSTOR extensions instruction */
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BX_ISA_XSAVEOPT, /* XSAVEOPT instruction */
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BX_ISA_XSAVEC, /* XSAVEC instruction */
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BX_ISA_XSAVES, /* XSAVES instruction */
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BX_ISA_AES_PCLMULQDQ, /* AES+PCLMULQDQ instructions */
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BX_ISA_VAES_VPCLMULQDQ, /* Wide vector versions of AES+PCLMULQDQ instructions */
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BX_ISA_MOVBE, /* MOVBE instruction */
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BX_ISA_FSGSBASE, /* FS/GS BASE access instruction */
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BX_ISA_INVPCID, /* INVPCID instruction */
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BX_ISA_AVX, /* AVX instruction */
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BX_ISA_AVX2, /* AVX2 instruction */
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BX_ISA_AVX_F16C, /* AVX F16 convert instruction */
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BX_ISA_AVX_FMA, /* AVX FMA instruction */
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BX_ISA_ALT_MOV_CR8, /* LOCK CR0 access CR8 (AMD) */
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BX_ISA_SSE4A, /* SSE4A instruction (AMD) */
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BX_ISA_MISALIGNED_SSE, /* Misaligned SSE (AMD) */
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BX_ISA_LZCNT, /* LZCNT instruction */
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BX_ISA_BMI1, /* BMI1 instruction */
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BX_ISA_BMI2, /* BMI2 instruction */
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BX_ISA_FMA4, /* FMA4 instruction (AMD) */
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BX_ISA_XOP, /* XOP instruction (AMD) */
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BX_ISA_TBM, /* TBM instruction (AMD) */
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BX_ISA_SVM, /* SVM instruction (AMD) */
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BX_ISA_RDRAND, /* RDRAND instruction */
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BX_ISA_ADX, /* ADCX/ADOX instruction */
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BX_ISA_SMAP, /* SMAP support */
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BX_ISA_RDSEED, /* RDSEED instruction */
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BX_ISA_SHA, /* SHA instruction */
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BX_ISA_SHA512, /* SHA512 instruction */
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BX_ISA_GFNI, /* GFNI instruction */
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BX_ISA_SM3, /* SM3 instruction */
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BX_ISA_SM4, /* SM4 instruction */
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BX_ISA_AVX512, /* AVX-512 instruction */
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BX_ISA_AVX512_CD, /* AVX-512 Conflict Detection instruction */
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BX_ISA_AVX512_PF, /* AVX-512 Sparse Prefetch instruction */
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BX_ISA_AVX512_ER, /* AVX-512 Exponential/Reciprocal instruction */
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BX_ISA_AVX512_DQ, /* AVX-512DQ instruction */
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BX_ISA_AVX512_BW, /* AVX-512 Byte/Word instruction */
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BX_ISA_AVX512_VL, /* AVX-512 Vector Length extensions */
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BX_ISA_AVX512_VBMI, /* AVX-512 VBMI : Vector Bit Manipulation Instructions */
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BX_ISA_AVX512_VBMI2, /* AVX-512 VBMI2 : Vector Bit Manipulation Instructions */
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BX_ISA_AVX512_IFMA52, /* AVX-512 IFMA52 Instructions */
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BX_ISA_AVX512_VPOPCNTDQ, /* AVX-512 VPOPCNTD/VPOPCNTQ Instructions */
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BX_ISA_AVX512_VNNI, /* AVX-512 VNNI Instructions */
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BX_ISA_AVX512_BITALG, /* AVX-512 BITALG Instructions */
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BX_ISA_AVX512_VP2INTERSECT, /* AVX-512 VP2INTERSECT Instructions */
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BX_ISA_AVX512_BF16, /* AVX-512 BF16 Instructions */
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BX_ISA_AVX_IFMA, /* AVX encoded IFMA Instructions */
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BX_ISA_AVX_VNNI, /* AVX encoded VNNI Instructions */
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BX_ISA_AVX_VNNI_INT8, /* AVX encoded VNNI-INT8 Instructions */
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BX_ISA_AVX_VNNI_INT16, /* AVX encoded VNNI-INT16 Instructions */
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BX_ISA_AVX_NE_CONVERT, /* AVX-NE-CONVERT Instructions */
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BX_ISA_XAPIC, /* XAPIC support */
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BX_ISA_X2APIC, /* X2APIC support */
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BX_ISA_XAPIC_EXT, /* XAPIC Extensions support */
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BX_ISA_PCID, /* PCID pages support */
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BX_ISA_SMEP, /* SMEP support */
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BX_ISA_TSC_ADJUST, /* TSC-Adjust MSR */
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BX_ISA_TSC_DEADLINE, /* TSC-Deadline */
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BX_ISA_FOPCODE_DEPRECATION, /* FOPCODE Deprecation - FOPCODE update on unmasked x87 exception only */
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BX_ISA_FCS_FDS_DEPRECATION, /* FCS/FDS Deprecation */
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BX_ISA_FDP_DEPRECATION, /* FDP Deprecation - FDP update on unmasked x87 exception only */
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BX_ISA_PKU, /* User-Mode Protection Keys */
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BX_ISA_PKS, /* Supervisor-Mode Protection Keys */
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BX_ISA_UMIP, /* User-Mode Instructions Prevention */
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BX_ISA_LASS, /* Linear Address Separation */
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BX_ISA_RDPID, /* RDPID Support */
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BX_ISA_TCE, /* Translation Cache Extensions (TCE) support (AMD) */
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BX_ISA_CLZERO, /* CLZERO instruction support (AMD) */
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BX_ISA_SCA_MITIGATIONS, /* SCA Mitigations */
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BX_ISA_CET, /* Control Flow Enforcement */
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BX_ISA_WRMSRNS, /* Non-Serializing version of WRMSR */
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BX_ISA_CMPCCXADD, /* CMPccXADD instructions */
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BX_ISA_SERIALIZE, /* SERIALIZE instruction */
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#define x86_feature(isa, feature_name) isa,
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#include "features.h"
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BX_ISA_EXTENSION_LAST
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};
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#undef x86_feature
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#define BX_ISA_EXTENSIONS_ARRAY_SIZE (4)
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141
bochs/cpu/decoder/features.h
Normal file
141
bochs/cpu/decoder/features.h
Normal file
@ -0,0 +1,141 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2023 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_X86_FEATURES_H
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#define BX_X86_FEATURES_H
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x86_feature(BX_ISA_386, "386ni") /* 386 or earlier instruction */
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x86_feature(BX_ISA_X87, "x87") /* FPU (x87) instruction */
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x86_feature(BX_ISA_486, "486ni") /* 486 new instruction */
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x86_feature(BX_ISA_PENTIUM, "pentium_ni") /* Pentium new instruction */
|
||||
x86_feature(BX_ISA_P6, "p6ni") /* P6 new instruction */
|
||||
x86_feature(BX_ISA_MMX, "mmx") /* MMX instruction */
|
||||
x86_feature(BX_ISA_3DNOW, "3dnow") /* 3DNow! instruction (AMD) */
|
||||
x86_feature(BX_ISA_DEBUG_EXTENSIONS, "debugext") /* Debug Extensions support */
|
||||
x86_feature(BX_ISA_VME, "vme") /* VME support */
|
||||
x86_feature(BX_ISA_PSE, "pse") /* PSE support */
|
||||
x86_feature(BX_ISA_PAE, "pae") /* PAE support */
|
||||
x86_feature(BX_ISA_PGE, "pge") /* Global Pages support */
|
||||
x86_feature(BX_ISA_PSE36, "pse36") /* PSE-36 support */
|
||||
x86_feature(BX_ISA_MTRR, "mtrr") /* MTRR support */
|
||||
x86_feature(BX_ISA_PAT, "pat") /* PAT support */
|
||||
x86_feature(BX_ISA_SYSCALL_SYSRET_LEGACY, "legacy_syscall_sysret") /* SYSCALL/SYSRET in legacy mode (AMD) */
|
||||
x86_feature(BX_ISA_SYSENTER_SYSEXIT, "sysenter_sysexit") /* SYSENTER/SYSEXIT instruction */
|
||||
x86_feature(BX_ISA_CLFLUSH, "clflush") /* CLFLUSH instruction */
|
||||
x86_feature(BX_ISA_CLFLUSHOPT, "clflushopt") /* CLFLUSHOPT instruction */
|
||||
x86_feature(BX_ISA_CLWB, "clwb") /* CLWB instruction */
|
||||
x86_feature(BX_ISA_CLDEMOTE, "cldemote") /* CLDEMOTE instruction */
|
||||
x86_feature(BX_ISA_SSE, "sse") /* SSE instruction */
|
||||
x86_feature(BX_ISA_SSE2, "sse2") /* SSE2 instruction */
|
||||
x86_feature(BX_ISA_SSE3, "sse3") /* SSE3 instruction */
|
||||
x86_feature(BX_ISA_SSSE3, "ssse3") /* SSSE3 instruction */
|
||||
x86_feature(BX_ISA_SSE4_1, "sse4_1") /* SSE4_1 instruction */
|
||||
x86_feature(BX_ISA_SSE4_2, "sse4_2") /* SSE4_2 instruction */
|
||||
x86_feature(BX_ISA_POPCNT, "popcnt") /* POPCNT instruction */
|
||||
x86_feature(BX_ISA_MONITOR_MWAIT, "mwait") /* MONITOR/MWAIT instruction */
|
||||
x86_feature(BX_ISA_MONITORX_MWAITX, "mwaitx") /* MONITORX/MWAITX instruction (AMD) */
|
||||
x86_feature(BX_ISA_WAITPKG, "waitpkg") /* TPAUSE/UMONITOR/UMWAIT instructions */
|
||||
x86_feature(BX_ISA_VMX, "vmx") /* VMX instruction */
|
||||
x86_feature(BX_ISA_SMX, "smx") /* SMX instruction */
|
||||
x86_feature(BX_ISA_LONG_MODE, "longmode") /* Long Mode (x86-64) support */
|
||||
x86_feature(BX_ISA_LM_LAHF_SAHF, "lm_lahf_sahf") /* Long Mode LAHF/SAHF instruction */
|
||||
x86_feature(BX_ISA_NX, "nx") /* No-Execute Pages support */
|
||||
x86_feature(BX_ISA_1G_PAGES, "1g_pages") /* 1Gb pages support */
|
||||
x86_feature(BX_ISA_CMPXCHG16B, "cmpxhg16b") /* CMPXCHG16B instruction */
|
||||
x86_feature(BX_ISA_RDTSCP, "rdtscp") /* RDTSCP instruction */
|
||||
x86_feature(BX_ISA_FFXSR, "ffxsr") /* EFER.FFXSR support (AMD) */
|
||||
x86_feature(BX_ISA_XSAVE, "xsave") /* XSAVE/XRSTOR extensions instruction */
|
||||
x86_feature(BX_ISA_XSAVEOPT, "xsaveopt") /* XSAVEOPT instruction */
|
||||
x86_feature(BX_ISA_XSAVEC, "xsavec") /* XSAVEC instruction */
|
||||
x86_feature(BX_ISA_XSAVES, "xsaves") /* XSAVES instruction */
|
||||
x86_feature(BX_ISA_AES_PCLMULQDQ, "aes_pclmulqdq") /* AES+PCLMULQDQ instructions */
|
||||
x86_feature(BX_ISA_VAES_VPCLMULQDQ, "vaes_vpclmulqdq") /* Wide vector versions of AES+PCLMULQDQ instructions */
|
||||
x86_feature(BX_ISA_MOVBE, "movbe") /* MOVBE instruction */
|
||||
x86_feature(BX_ISA_FSGSBASE, "fsgsbase") /* FS/GS BASE access instruction */
|
||||
x86_feature(BX_ISA_INVPCID, "invpcid") /* INVPCID instruction */
|
||||
x86_feature(BX_ISA_AVX, "avx") /* AVX instruction */
|
||||
x86_feature(BX_ISA_AVX2, "avx2") /* AVX2 instruction */
|
||||
x86_feature(BX_ISA_AVX_F16C, "avx_f16c") /* AVX F16 convert instruction */
|
||||
x86_feature(BX_ISA_AVX_FMA, "avx_fma") /* AVX FMA instruction */
|
||||
x86_feature(BX_ISA_ALT_MOV_CR8, "altmovcr8") /* LOCK CR0 access CR8 (AMD) */
|
||||
x86_feature(BX_ISA_SSE4A, "sse4a") /* SSE4A instruction (AMD) */
|
||||
x86_feature(BX_ISA_MISALIGNED_SSE, "misaligned_sse") /* Misaligned SSE (AMD) */
|
||||
x86_feature(BX_ISA_LZCNT, "lzcnt") /* LZCNT instruction */
|
||||
x86_feature(BX_ISA_BMI1, "bmi1") /* BMI1 instruction */
|
||||
x86_feature(BX_ISA_BMI2, "bmi2") /* BMI2 instruction */
|
||||
x86_feature(BX_ISA_FMA4, "fma4") /* FMA4 instruction (AMD) */
|
||||
x86_feature(BX_ISA_XOP, "xop") /* XOP instruction (AMD) */
|
||||
x86_feature(BX_ISA_TBM, "tbm") /* TBM instruction (AMD) */
|
||||
x86_feature(BX_ISA_SVM, "svm") /* SVM instruction (AMD) */
|
||||
x86_feature(BX_ISA_RDRAND, "rdrand") /* RDRAND instruction */
|
||||
x86_feature(BX_ISA_RDSEED, "rdseed") /* RDSEED instruction */
|
||||
x86_feature(BX_ISA_ADX, "adx") /* ADCX/ADOX instruction */
|
||||
x86_feature(BX_ISA_SMAP, "smap") /* SMAP support */
|
||||
x86_feature(BX_ISA_SHA, "sha") /* SHA instruction */
|
||||
x86_feature(BX_ISA_SHA512, "sha512") /* SHA-512 instruction */
|
||||
x86_feature(BX_ISA_GFNI, "gfni") /* GFNI instruction */
|
||||
x86_feature(BX_ISA_SM3, "sm3") /* SM3 instruction */
|
||||
x86_feature(BX_ISA_SM4, "sm4") /* SM4 instruction */
|
||||
#if BX_SUPPORT_EVEX
|
||||
x86_feature(BX_ISA_AVX512, "avx512") /* AVX-512 instruction */
|
||||
x86_feature(BX_ISA_AVX512_CD, "avx512cd") /* AVX-512 Conflict Detection instruction */
|
||||
x86_feature(BX_ISA_AVX512_PF, "avx512pf") /* AVX-512 Sparse Prefetch instruction */
|
||||
x86_feature(BX_ISA_AVX512_ER, "avx512er") /* AVX-512 Exponential/Reciprocal instruction */
|
||||
x86_feature(BX_ISA_AVX512_DQ, "avx512dq") /* AVX-512DQ instruction */
|
||||
x86_feature(BX_ISA_AVX512_BW, "avx512bw") /* AVX-512 Byte/Word instruction */
|
||||
x86_feature(BX_ISA_AVX512_VBMI, "avx512vbmi") /* AVX-512 VBMI : Vector Bit Manipulation Instructions */
|
||||
x86_feature(BX_ISA_AVX512_VBMI2, "avx512vbmi2") /* AVX-512 VBMI2 : Vector Bit Manipulation Instructions */
|
||||
x86_feature(BX_ISA_AVX512_IFMA52, "avx512ifma52") /* AVX-512 IFMA52 Instructions */
|
||||
x86_feature(BX_ISA_AVX512_VPOPCNTDQ, "avx512vpopcnt") /* AVX-512 VPOPCNTD/VPOPCNTQ Instructions */
|
||||
x86_feature(BX_ISA_AVX512_VNNI, "avx512vnni") /* AVX-512 VNNI Instructions */
|
||||
x86_feature(BX_ISA_AVX512_BITALG, "avx512bitalg") /* AVX-512 BITALG Instructions */
|
||||
x86_feature(BX_ISA_AVX512_VP2INTERSECT, "avx512vp2intersect") /* AVX-512 VP2INTERSECT Instructions */
|
||||
x86_feature(BX_ISA_AVX512_BF16, "avx512bf16") /* AVX-512 BF16 Instructions */
|
||||
#endif
|
||||
x86_feature(BX_ISA_AVX_IFMA, "avx_ifma") /* AVX encoded IFMA Instructions */
|
||||
x86_feature(BX_ISA_AVX_VNNI, "avx_vnni") /* AVX encoded VNNI Instructions */
|
||||
x86_feature(BX_ISA_AVX_VNNI_INT8, "avx_vnni_int8") /* AVX encoded VNNI-INT8 Instructions */
|
||||
x86_feature(BX_ISA_AVX_VNNI_INT16, "avx_vnni_int16") /* AVX encoded VNNI-INT16 Instructions */
|
||||
x86_feature(BX_ISA_AVX_NE_CONVERT, "avx_ne_convert") /* AVX-NE-CONVERT Instructions */
|
||||
x86_feature(BX_ISA_XAPIC, "xapic") /* XAPIC support */
|
||||
x86_feature(BX_ISA_X2APIC, "x2apic") /* X2APIC support */
|
||||
x86_feature(BX_ISA_XAPIC_EXT, "xapicext") /* XAPIC Extensions support (AMD) */
|
||||
x86_feature(BX_ISA_PCID, "pcid") /* PCID support */
|
||||
x86_feature(BX_ISA_SMEP, "smep") /* SMEP support */
|
||||
x86_feature(BX_ISA_TSC_ADJUST, "tsc_adjust") /* TSC-Adjust MSR */
|
||||
x86_feature(BX_ISA_TSC_DEADLINE, "tsc_deadline") /* TSC-Deadline */
|
||||
x86_feature(BX_ISA_FOPCODE_DEPRECATION, "fopcode_deprecation") /* FOPCODE Deprecation - FOPCODE update on unmasked x87 exception only */
|
||||
x86_feature(BX_ISA_FCS_FDS_DEPRECATION, "fcs_fds_deprecation") /* FCS/FDS Deprecation */
|
||||
x86_feature(BX_ISA_FDP_DEPRECATION, "fdp_deprecation") /* FDP Deprecation - FDP update on unmasked x87 exception only */
|
||||
x86_feature(BX_ISA_PKU, "pku") /* User-Mode Protection Keys */
|
||||
x86_feature(BX_ISA_PKS, "pks") /* Supervisor-Mode Protection Keys */
|
||||
x86_feature(BX_ISA_UMIP, "umip") /* User-Mode Instructions Prevention */
|
||||
x86_feature(BX_ISA_RDPID, "rdpid") /* RDPID Support */
|
||||
x86_feature(BX_ISA_TCE, "tce") /* Translation Cache Extensions (TCE) support (AMD) */
|
||||
x86_feature(BX_ISA_CLZERO, "clzero") /* CLZERO instruction support (AMD) */
|
||||
x86_feature(BX_ISA_SCA_MITIGATIONS, "sca_mitigations") /* Report SCA Mitigations in CPUID */
|
||||
x86_feature(BX_ISA_CET, "cet") /* Control Flow Enforcement */
|
||||
x86_feature(BX_ISA_WRMSRNS, "wrmsrns") /* Non-Serializing version of WRMSR */
|
||||
x86_feature(BX_ISA_CMPCCXADD, "cmpccxadd") /* CMPccXADD instructions */
|
||||
x86_feature(BX_ISA_SERIALIZE, "serialize") /* SERIALIZE instruction */
|
||||
x86_feature(BX_ISA_LASS, "lass") /* Linear Address Space Separation support */
|
||||
|
||||
#endif
|
||||
@ -589,7 +589,6 @@ void bx_generic_cpuid_t::init_cpu_extensions_bitmask(void)
|
||||
#if BX_SUPPORT_EVEX
|
||||
case BX_CPUID_SUPPORT_AVX512:
|
||||
enable_cpu_extension(BX_ISA_AVX512);
|
||||
enable_cpu_extension(BX_ISA_AVX512_VL);
|
||||
enable_cpu_extension(BX_ISA_AVX512_BW);
|
||||
enable_cpu_extension(BX_ISA_AVX512_DQ);
|
||||
enable_cpu_extension(BX_ISA_AVX512_CD);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user