From 7e04c23d2f18915ddd4bcf34ccadda825054ce01 Mon Sep 17 00:00:00 2001
From: Bryce Denney <bryce@tlw.com>
Date: Wed, 19 Jun 2002 15:49:07 +0000
Subject: [PATCH] - check in Mike Reiker's 4meg page code from a patch that he
 submitted last   November 17.

---
 bochs/cpu/paging.cc    | 37 ++++++++++++++++++++++++++++++++++---
 bochs/cpu/proc_ctrl.cc | 11 +++++------
 2 files changed, 39 insertions(+), 9 deletions(-)

diff --git a/bochs/cpu/paging.cc b/bochs/cpu/paging.cc
index 46bdb4696..ca6746bbc 100644
--- a/bochs/cpu/paging.cc
+++ b/bochs/cpu/paging.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: paging.cc,v 1.8 2001-10-03 13:10:37 bdenney Exp $
+// $Id: paging.cc,v 1.9 2002-06-19 15:49:07 bdenney Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -502,9 +502,9 @@ priv_check:
       // A/D bits need updating first
       BX_CPU_THIS_PTR TLB.entry[TLB_index].combined_access = new_combined_access;
       pte_addr = BX_CPU_THIS_PTR TLB.entry[TLB_index].pte_addr;
-      BX_CPU_THIS_PTR mem->read_physical(this, pte_addr, 4, &pte); // get old PTE
+      BX_CPU_THIS_PTR mem->read_physical(this, pte_addr, 4, &pte); // get old 4kPTE/4mPDE
       pte |= 0x20 | (is_rw << 6);
-      BX_CPU_THIS_PTR mem->write_physical(this, pte_addr, 4, &pte); // write updated PTE
+      BX_CPU_THIS_PTR mem->write_physical(this, pte_addr, 4, &pte); // write updated 4kPTE/4mPDE
       return(paddress);
       }
 
@@ -523,6 +523,18 @@ priv_check:
     goto page_fault_not_present;
     }
 
+  // check for 4Mbyte page
+
+  if ((pde & 0x80) && (BX_CPU_THIS_PTR cr4 & 0x10)) {     // check for 4M page and make sure it's enabled
+    combined_access = pde & 0x06;                         // combined access is just access from the pde
+    ppf = (pde & 0xFFC00000) | (laddress & 0x003FF000);   // make up the physical frame number
+    pte_addr = pde_addr;                                  // A/D bits in same place as a real pte
+  }
+
+  // normal 4Kbyte page
+  
+  else {
+
   // Get page table entry
   pte_addr = (pde & 0xfffff000) |
              ((laddress & 0x003ff000) >> 10);
@@ -556,12 +568,17 @@ priv_check:
 #endif
 
   ppf = pte & 0xfffff000;
+  }
+
+  // Calculate physical memory address and fill in TLB cache entry
+
   paddress = ppf | poffset;
 
   BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = lpf;
   BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf = ppf;
   BX_CPU_THIS_PTR TLB.entry[TLB_index].pte_addr = pte_addr;
   BX_CPU_THIS_PTR TLB.entry[TLB_index].combined_access = combined_access;
+
   goto priv_check;
 
 
@@ -654,6 +671,18 @@ priv_check:
     goto page_fault;
     }
 
+  // check for 4Mbyte page
+
+  if ((pde & 0x80) && (BX_CPU_THIS_PTR cr4 & 0x10)) {     // check for 4M page and make sure it's enabled
+    combined_access = pde & 0x06;                         // combined access is just access from the pde
+    ppf = (pde & 0xFFC00000) | (laddress & 0x003FF000);   // make up the physical frame number
+    pte_addr = pde_addr;                                  // A/D bits in same place as a real pte
+  }
+
+  
+  else {
+  // normal 4Kbyte page
+
   // Get page table entry
   pte_addr = (pde & 0xfffff000) |
              ((laddress & 0x003ff000) >> 10);
@@ -687,6 +716,8 @@ priv_check:
 #endif
 
   ppf = pte & 0xfffff000;
+  }
+
   paddress = ppf | poffset;
 
   BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = lpf;
diff --git a/bochs/cpu/proc_ctrl.cc b/bochs/cpu/proc_ctrl.cc
index e31056e4a..93c9b5919 100644
--- a/bochs/cpu/proc_ctrl.cc
+++ b/bochs/cpu/proc_ctrl.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: proc_ctrl.cc,v 1.21 2002-04-11 01:19:24 instinc Exp $
+// $Id: proc_ctrl.cc,v 1.22 2002-06-19 15:49:07 bdenney Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -505,16 +505,14 @@ BX_CPU_C::MOV_CdRd(BxInstruction_t *i)
       //  Protected mode: #GP(0) if attempt to write a 1 to
       //  any reserved bit of CR4
 
-      BX_INFO(("MOV_CdRd: ignoring write to CR4 of 0x%08x",
-        val_32));
-      if (val_32) {
+      if (val_32 & ~ 0x10) { // support CR4<PSE> (to allow 4M pages)
         BX_INFO(("MOV_CdRd: (CR4) write of 0x%08x not supported!",
           val_32));
         }
       // Only allow writes of 0 to CR4 for now.
       // Writes to bits in CR4 should not be 1s as CPUID
       // returns not-supported for all of these features.
-      BX_CPU_THIS_PTR cr4 = 0;
+      BX_CPU_THIS_PTR cr4 = val_32 & 0x10;
 #endif
       break;
     default:
@@ -1040,7 +1038,8 @@ BX_CPU_C::CPUID(BxInstruction_t *i)
 #  endif
 #else
       BX_PANIC(("CPUID: not implemented for > 6"));
-#endif
+#endif
+      features |= 8; // support page-size extension (4m pages)
 
       EAX = (family <<8) | (model<<4) | stepping;
       EBX = ECX = 0; // reserved