According to the Intel (and AMD) manuals a lot different SSE/SSE2 opcodes has EXACTLY the same operation.

Deleted first three redundant opcodes (move integer data):
   MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
   MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
   MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
   MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)

Until under examination:
XORPS,XORPD
ORPS,ORPD
ANDPS,ANDPD
ANDNPS,ANDNPD
MOVUPS,MOVUPD

bochs/cpu/cpu.h

@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: cpu.h,v 1.114 2002-11-13 21:35:16 sshwarts Exp $
+// $Id: cpu.h,v 1.115 2002-11-13 22:24:02 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -2120,12 +2120,8 @@ union {
   BX_SMF void MOVSD_VsdWsd(bxInstruction_c *i);
   BX_SMF void MOVUPD_WpdVpd(bxInstruction_c *i);
   BX_SMF void MOVSD_WsdVsd(bxInstruction_c *i);
-  BX_SMF void MOVLPD_VsdMq(bxInstruction_c *i);
-  BX_SMF void MOVLPD_MqVsd(bxInstruction_c *i);
   BX_SMF void UNPCKLPD_VpdWq(bxInstruction_c *i);
   BX_SMF void UNPCKHPD_VpdWq(bxInstruction_c *i);
-  BX_SMF void MOVHPD_VpdMq(bxInstruction_c *i);
-  BX_SMF void MOVHPD_MqVpd(bxInstruction_c *i);
   BX_SMF void CVTPI2PD_VpdQd(bxInstruction_c *i);
   BX_SMF void CVTSI2SD_VsdEd(bxInstruction_c *i);
   BX_SMF void CVTTPD2PI_PqWpd(bxInstruction_c *i);

bochs/cpu/fetchdecode.cc

@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: fetchdecode.cc,v 1.32 2002-11-13 21:35:17 sshwarts Exp $
+// $Id: fetchdecode.cc,v 1.33 2002-11-13 22:24:02 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -219,6 +219,10 @@ static BxOpcodeInfo_t opcodesMOV_EdGd[2] = {
    MOVAPS_VpsWps  (0f 28) = MOVAPD_VpdWpd  (66 0f 28)
    MOVAPS_WpsVps  (0f 29) = MOVAPD_WpdVpd  (66 0f 29)
    MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
+   MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
+   MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
+   MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
+   MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)
 */
 
 static BxOpcodeInfo_t BxOpcodeGroupSSE_0f10[4] = {
@@ -237,14 +241,14 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f11[4] = {
 
 static BxOpcodeInfo_t BxOpcodeGroupSSE_0f12[4] = {
   /* -- */  { 0, &BX_CPU_C::MOVLPS_VpsMq },
-  /* 66 */  { 0, &BX_CPU_C::MOVLPD_VsdMq },
+  /* 66 */  { 0, &BX_CPU_C::MOVLPS_VpsMq },
   /* F2 */  { 0, &BX_CPU_C::BxError },
   /* F3 */  { 0, &BX_CPU_C::BxError }
   };
 
 static BxOpcodeInfo_t BxOpcodeGroupSSE_0f13[4] = {
   /* -- */  { 0, &BX_CPU_C::MOVLPS_MqVps },
-  /* 66 */  { 0, &BX_CPU_C::MOVLPD_MqVsd },
+  /* 66 */  { 0, &BX_CPU_C::MOVLPS_MqVps },
   /* F2 */  { 0, &BX_CPU_C::BxError },
   /* F3 */  { 0, &BX_CPU_C::BxError }
   };
@@ -265,14 +269,14 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f15[4] = {
 
 static BxOpcodeInfo_t BxOpcodeGroupSSE_0f16[4] = {
   /* -- */  { 0, &BX_CPU_C::MOVHPS_VpsMq },
-  /* 66 */  { 0, &BX_CPU_C::MOVHPD_VpdMq },
+  /* 66 */  { 0, &BX_CPU_C::MOVHPS_VpsMq },
   /* F2 */  { 0, &BX_CPU_C::BxError },
   /* F3 */  { 0, &BX_CPU_C::BxError }
   };
 
 static BxOpcodeInfo_t BxOpcodeGroupSSE_0f17[4] = {
   /* -- */  { 0, &BX_CPU_C::MOVHPS_MqVps },
-  /* 66 */  { 0, &BX_CPU_C::MOVHPD_MqVpd },
+  /* 66 */  { 0, &BX_CPU_C::MOVHPS_MqVps },
   /* F2 */  { 0, &BX_CPU_C::BxError },
   /* F3 */  { 0, &BX_CPU_C::BxError }
   };

bochs/cpu/fetchdecode64.cc

@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: fetchdecode64.cc,v 1.28 2002-11-13 21:35:17 sshwarts Exp $
+// $Id: fetchdecode64.cc,v 1.29 2002-11-13 22:24:03 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -285,6 +285,10 @@ static BxOpcodeInfo_t opcodesMOV_EdGd[2] = {
    MOVAPS_VpsWps  (0f 28) = MOVAPD_VpdWpd  (66 0f 28)
    MOVAPS_WpsVps  (0f 29) = MOVAPD_WpdVpd  (66 0f 29)
    MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
+   MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
+   MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
+   MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
+   MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)
 */
 
 static BxOpcodeInfo_t BxOpcodeGroupSSE_0f10[4] = {
@@ -303,14 +307,14 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f11[4] = {
 
 static BxOpcodeInfo_t BxOpcodeGroupSSE_0f12[4] = {
   /* -- */  { 0, &BX_CPU_C::MOVLPS_VpsMq },
-  /* 66 */  { 0, &BX_CPU_C::MOVLPD_VsdMq },
+  /* 66 */  { 0, &BX_CPU_C::MOVLPS_VpsMq },
   /* F2 */  { 0, &BX_CPU_C::BxError },
   /* F3 */  { 0, &BX_CPU_C::BxError }
   };
 
 static BxOpcodeInfo_t BxOpcodeGroupSSE_0f13[4] = {
   /* -- */  { 0, &BX_CPU_C::MOVLPS_MqVps },
-  /* 66 */  { 0, &BX_CPU_C::MOVLPD_MqVsd },
+  /* 66 */  { 0, &BX_CPU_C::MOVLPS_MqVps },
   /* F2 */  { 0, &BX_CPU_C::BxError },
   /* F3 */  { 0, &BX_CPU_C::BxError }
   };
@@ -331,14 +335,14 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f15[4] = {
 
 static BxOpcodeInfo_t BxOpcodeGroupSSE_0f16[4] = {
   /* -- */  { 0, &BX_CPU_C::MOVHPS_VpsMq },
-  /* 66 */  { 0, &BX_CPU_C::MOVHPD_VpdMq },
+  /* 66 */  { 0, &BX_CPU_C::MOVHPS_VpsMq },
   /* F2 */  { 0, &BX_CPU_C::BxError },
   /* F3 */  { 0, &BX_CPU_C::BxError }
   };
 
 static BxOpcodeInfo_t BxOpcodeGroupSSE_0f17[4] = {
   /* -- */  { 0, &BX_CPU_C::MOVHPS_MqVps },
-  /* 66 */  { 0, &BX_CPU_C::MOVHPD_MqVpd },
+  /* 66 */  { 0, &BX_CPU_C::MOVHPS_MqVps },
   /* F2 */  { 0, &BX_CPU_C::BxError },
   /* F3 */  { 0, &BX_CPU_C::BxError }
   };

bochs/cpu/sse2.cc

@@ -72,30 +72,6 @@ void BX_CPU_C::MOVSD_WsdVsd(bxInstruction_c *i)
 #endif
 }
 
-void BX_CPU_C::MOVLPD_VsdMq(bxInstruction_c *i)
-{
-#if BX_SUPPORT_SSE >= 2
-  BX_CPU_THIS_PTR prepareSSE();
-
-  BX_PANIC(("MOVLPD_VsdMq: SSE2 instruction still not implemented"));
-#else
-  BX_INFO(("MOVLPD_VsdMq: SSE2 not supported in current configuration"));
-  UndefinedOpcode(i);
-#endif
-}
-
-void BX_CPU_C::MOVLPD_MqVsd(bxInstruction_c *i)
-{
-#if BX_SUPPORT_SSE >= 2
-  BX_CPU_THIS_PTR prepareSSE();
-
-  BX_PANIC(("MOVLPD_MqVsd: SSE2 instruction still not implemented"));
-#else
-  BX_INFO(("MOVLPD_MqVsd: SSE2 not supported in current configuration"));
-  UndefinedOpcode(i);
-#endif
-}
-
 void BX_CPU_C::UNPCKLPD_VpdWq(bxInstruction_c *i)
 {
 #if BX_SUPPORT_SSE >= 2
@@ -120,30 +96,6 @@ void BX_CPU_C::UNPCKHPD_VpdWq(bxInstruction_c *i)
 #endif
 }
 
-void BX_CPU_C::MOVHPD_VpdMq(bxInstruction_c *i)
-{
-#if BX_SUPPORT_SSE >= 2
-  BX_CPU_THIS_PTR prepareSSE();
-
-  BX_PANIC(("MOVHPD_VpdMq: SSE2 instruction still not implemented"));
-#else
-  BX_INFO(("MOVHPD_VpdMq: SSE2 not supported in current configuration"));
-  UndefinedOpcode(i);
-#endif
-}
-
-void BX_CPU_C::MOVHPD_MqVpd(bxInstruction_c *i)
-{
-#if BX_SUPPORT_SSE >= 2
-  BX_CPU_THIS_PTR prepareSSE();
-
-  BX_PANIC(("MOVHPD_MqVpd: SSE2 instruction still not implemented"));
-#else
-  BX_INFO(("MOVHPD_MqVpd: SSE2 not supported in current configuration"));
-  UndefinedOpcode(i);
-#endif
-}
-
 void BX_CPU_C::CVTPI2PD_VpdQd(bxInstruction_c *i)
 {
 #if BX_SUPPORT_SSE >= 2