mirror of https://github.com/bochs-emu/Bochs
* Fix LOCK prefix handling for x86-64
* Split BT*_EvGv functions to 3 different function according to exec mode
This commit is contained in:
Stanislav Shwartsman
parent
c3cdd7ef21
commit
760a195c9d
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@ -2,8 +2,8 @@ Changes to next release:
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- CPU
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- fixes for booting OS/2 by Dmitri Froloff
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- v8086 priveleged instruction processing bug (was also reported by
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LightCone Aug 7 2003)
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- fuxed v8086 priveleged instruction processing bug (was also reported
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by LightCone Aug 7 2003)
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- exception process bug (was reported by Diego Henriquez Sat Nov 15
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01:16:51 CET 2003)
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- segment validation with IRET instruction
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@ -20,7 +20,7 @@ Changes to next release:
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- fixed using invalid segment register for MOV instruction (h.johansson)
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- fixed ET bit mismatch between CR0 and SMSW instruction
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- fixed possible simulator #DIVZERO fault when executing IDIV instruction
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- fixed undocumented flags handling for BTS, BTR, SHR and MUL
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- fixed undocumented flags handling for BTS, BTR, SHR, MUL and IMUL
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instructions (Stanislav Shwartsman)
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- fixed CF flag handling for SHL instruction in x86-64 mode
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(Stanislav Shwartsman)
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@ -133,8 +133,19 @@ Changes to next release:
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- patches applied
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- patch.rombios.markevich (Start/Stop Wait Timer) (Kory Markevich)
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- patch.apic-zwane (APIC fixes) (Zwane Mwaikambo)
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- these S.F. bugs were closed
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#1028682 Report incorrect disk parameters of floppy
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#1026234 make fails on Cygwin because of missing .exe extension
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#1026241 --enable-cpp needed for .conf.win32-cygwin
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#855323 BIOS Panic at rombios.c, line 1563
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#762773 ROM checksum is not checked in rom_scan_loop
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#657604 concat_image_t.lseek to byte -1378816 fa
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#800140 No AH=83h INT15h implemented
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#831965 Win32.zip BIOSes in wrong directory
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#873280 bximage crashes after createing "growing"
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#892223 bochsrc-sample.txt/vgaromimage option error
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#1014361 Bximage on WinXP won't create image
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#651510 bximage won't create larger than 2GB
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#759206 bximage fails on Win32 for hd images over 2Gb
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773
bochs/cpu/bit.cc
773
bochs/cpu/bit.cc
File diff suppressed because it is too large
Load Diff
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.178 2004-09-15 21:48:56 sshwarts Exp $
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// $Id: cpu.h,v 1.179 2004-09-17 20:47:17 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1568,7 +1568,6 @@ public: // for now...
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BX_SMF void ARPL_EwGw(bxInstruction_c *);
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BX_SMF void PUSH_Id(bxInstruction_c *);
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BX_SMF void PUSH_Iw(bxInstruction_c *);
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BX_SMF void IMUL_GdEdId(bxInstruction_c *);
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BX_SMF void INSB_YbDX(bxInstruction_c *);
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BX_SMF void INSW_YvDX(bxInstruction_c *);
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BX_SMF void OUTSB_DXXb(bxInstruction_c *);
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@ -1718,28 +1717,33 @@ public: // for now...
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BX_SMF void SETNLE_Eb(bxInstruction_c *);
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BX_SMF void CPUID(bxInstruction_c *);
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BX_SMF void BT_EvGv(bxInstruction_c *);
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BX_SMF void SHLD_EdGd(bxInstruction_c *);
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BX_SMF void SHLD_EwGw(bxInstruction_c *);
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BX_SMF void BTS_EvGv(bxInstruction_c *);
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BX_SMF void SHRD_EwGw(bxInstruction_c *);
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BX_SMF void SHRD_EdGd(bxInstruction_c *);
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BX_SMF void SHLD_EdGd(bxInstruction_c *);
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BX_SMF void SHLD_EwGw(bxInstruction_c *);
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BX_SMF void IMUL_GdEd(bxInstruction_c *);
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BX_SMF void BSF_GwEw(bxInstruction_c *);
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BX_SMF void BSF_GdEd(bxInstruction_c *);
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BX_SMF void BSR_GwEw(bxInstruction_c *);
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BX_SMF void BSR_GdEd(bxInstruction_c *);
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BX_SMF void BT_EwGw(bxInstruction_c *);
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BX_SMF void BT_EdGd(bxInstruction_c *);
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BX_SMF void BTS_EwGw(bxInstruction_c *);
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BX_SMF void BTS_EdGd(bxInstruction_c *);
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BX_SMF void BTR_EwGw(bxInstruction_c *);
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BX_SMF void BTR_EdGd(bxInstruction_c *);
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BX_SMF void BTC_EwGw(bxInstruction_c *);
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BX_SMF void BTC_EdGd(bxInstruction_c *);
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BX_SMF void LSS_GvMp(bxInstruction_c *);
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BX_SMF void BTR_EvGv(bxInstruction_c *);
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BX_SMF void LFS_GvMp(bxInstruction_c *);
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BX_SMF void LGS_GvMp(bxInstruction_c *);
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BX_SMF void MOVZX_GdEb(bxInstruction_c *);
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BX_SMF void MOVZX_GwEb(bxInstruction_c *);
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BX_SMF void MOVZX_GdEw(bxInstruction_c *);
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BX_SMF void MOVZX_GwEw(bxInstruction_c *);
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BX_SMF void BTC_EvGv(bxInstruction_c *);
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BX_SMF void BSF_GvEv(bxInstruction_c *);
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BX_SMF void BSR_GvEv(bxInstruction_c *);
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BX_SMF void MOVSX_GdEb(bxInstruction_c *);
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BX_SMF void MOVSX_GwEb(bxInstruction_c *);
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BX_SMF void MOVSX_GdEw(bxInstruction_c *);
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@ -1805,7 +1809,9 @@ public: // for now...
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BX_SMF void NOT_Eb(bxInstruction_c *);
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BX_SMF void NEG_Eb(bxInstruction_c *);
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BX_SMF void MUL_ALEb(bxInstruction_c *);
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BX_SMF void IMUL_GdEd(bxInstruction_c *);
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BX_SMF void IMUL_ALEb(bxInstruction_c *);
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BX_SMF void IMUL_GdEdId(bxInstruction_c *);
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BX_SMF void DIV_ALEb(bxInstruction_c *);
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BX_SMF void IDIV_ALEb(bxInstruction_c *);
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@ -2471,6 +2477,14 @@ public: // for now...
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BX_SMF void MOVSX_GqEw(bxInstruction_c *);
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BX_SMF void MOVSX_GqEd(bxInstruction_c *);
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BX_SMF void BSF_GqEq(bxInstruction_c *);
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BX_SMF void BSR_GqEq(bxInstruction_c *);
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BX_SMF void BT_EqGq(bxInstruction_c *);
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BX_SMF void BTS_EqGq(bxInstruction_c *);
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BX_SMF void BTR_EqGq(bxInstruction_c *);
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BX_SMF void BTC_EqGq(bxInstruction_c *);
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BX_SMF void BSWAP_RAX(bxInstruction_c *);
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BX_SMF void BSWAP_RCX(bxInstruction_c *);
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BX_SMF void BSWAP_RDX(bxInstruction_c *);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.67 2004-09-06 20:22:38 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.68 2004-09-17 20:47:18 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -895,7 +895,7 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F A0 */ { 0, &BX_CPU_C::PUSH_FS },
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/* 0F A1 */ { 0, &BX_CPU_C::POP_FS },
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/* 0F A2 */ { 0, &BX_CPU_C::CPUID },
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/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EvGv },
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/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EwGw },
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/* 0F A4 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHLD_EwGw },
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/* 0F A5 */ { BxAnother, &BX_CPU_C::SHLD_EwGw },
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/* 0F A6 */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
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@ -903,7 +903,7 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F A8 */ { 0, &BX_CPU_C::PUSH_GS },
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/* 0F A9 */ { 0, &BX_CPU_C::POP_GS },
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/* 0F AA */ { 0, &BX_CPU_C::RSM },
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/* 0F AB */ { BxAnother | BxLockable, &BX_CPU_C::BTS_EvGv },
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/* 0F AB */ { BxAnother | BxLockable, &BX_CPU_C::BTS_EwGw },
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/* 0F AC */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHRD_EwGw },
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/* 0F AD */ { BxAnother, &BX_CPU_C::SHRD_EwGw },
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/* 0F AE */ { BxAnother | BxGroup15, NULL, BxOpcodeInfoG15 },
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@ -911,7 +911,7 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
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/* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EwGw },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EvGv },
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EwGw },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
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/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GwEb },
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@ -919,9 +919,9 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F B8 */ { 0, &BX_CPU_C::BxError },
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/* 0F B9 */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
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/* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfoG8EvIb },
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/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EvGv },
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/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GvEv },
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/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GvEv },
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/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EwGw },
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/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GwEw },
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/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GwEw },
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/* 0F BE */ { BxAnother, &BX_CPU_C::MOVSX_GwEb },
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/* 0F BF */ { BxAnother, &BX_CPU_C::MOVSX_GwEw },
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/* 0F C0 */ { BxAnother | BxLockable, &BX_CPU_C::XADD_EbGb },
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@ -1443,7 +1443,7 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F A0 */ { 0, &BX_CPU_C::PUSH_FS },
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/* 0F A1 */ { 0, &BX_CPU_C::POP_FS },
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/* 0F A2 */ { 0, &BX_CPU_C::CPUID },
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/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EvGv },
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/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EdGd },
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/* 0F A4 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHLD_EdGd },
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/* 0F A5 */ { BxAnother, &BX_CPU_C::SHLD_EdGd },
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/* 0F A6 */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
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@ -1451,7 +1451,7 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F A8 */ { 0, &BX_CPU_C::PUSH_GS },
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/* 0F A9 */ { 0, &BX_CPU_C::POP_GS },
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/* 0F AA */ { 0, &BX_CPU_C::RSM },
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/* 0F AB */ { BxAnother | BxLockable, &BX_CPU_C::BTS_EvGv },
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/* 0F AB */ { BxAnother | BxLockable, &BX_CPU_C::BTS_EdGd },
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/* 0F AC */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHRD_EdGd },
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/* 0F AD */ { BxAnother, &BX_CPU_C::SHRD_EdGd },
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/* 0F AE */ { BxAnother | BxGroup15, NULL, BxOpcodeInfoG15 },
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@ -1459,7 +1459,7 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
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/* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EdGd },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EvGv },
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EdGd },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
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/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GdEb },
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@ -1467,9 +1467,9 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F B8 */ { 0, &BX_CPU_C::BxError },
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/* 0F B9 */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
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/* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfoG8EvIb },
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/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EvGv },
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/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GvEv },
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/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GvEv },
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/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EdGd },
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/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GdEd },
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/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GdEd },
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/* 0F BE */ { BxAnother, &BX_CPU_C::MOVSX_GdEb },
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/* 0F BF */ { BxAnother, &BX_CPU_C::MOVSX_GdEw },
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/* 0F C0 */ { BxAnother | BxLockable, &BX_CPU_C::XADD_EbGb },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.61 2004-09-06 20:22:39 sshwarts Exp $
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// $Id: fetchdecode64.cc,v 1.62 2004-09-17 20:47:19 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -57,6 +57,23 @@
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// Use the 0F0B opcode (UD2 instruction) or the 0FB9H opcode when deliberately
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// trying to generate an invalid opcode exception (#UD).
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/* *********** */
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// LOCK PREFIX //
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/* *********** */
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/*
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* The LOCK prefix can be prepended only to the following instructions
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* and only to those forms of the instructions where the destination
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* operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG,
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* CMPXCH8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If
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* the LOCK prefix is used with one of these instructions and the source
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* operand is a memory operand, an undefined opcode exception (#UD) will
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* be generated. An undefined opcode exception will also be generated if
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* the LOCK prefix is used with any instruction not in the above list.
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* The XCHG instruction always asserts the LOCK# signal regardless of the
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* presence or absence of the LOCK prefix.
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*/
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void BxResolveError(bxInstruction_c *);
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@ -969,15 +986,15 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
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/* 0F A0 */ { 0, &BX_CPU_C::PUSH_FS },
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/* 0F A1 */ { 0, &BX_CPU_C::POP_FS },
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/* 0F A2 */ { 0, &BX_CPU_C::CPUID },
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/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EvGv },
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/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EwGw },
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/* 0F A4 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHLD_EwGw },
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/* 0F A5 */ { BxAnother, &BX_CPU_C::SHLD_EwGw },
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/* 0F A6 */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
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/* 0F A7 */ { 0, &BX_CPU_C::CMPXCHG_IBTS },
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/* 0F A6 */ { 0, &BX_CPU_C::BxError },
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/* 0F A7 */ { 0, &BX_CPU_C::BxError },
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/* 0F A8 */ { 0, &BX_CPU_C::PUSH_GS },
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/* 0F A9 */ { 0, &BX_CPU_C::POP_GS },
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/* 0F AA */ { 0, &BX_CPU_C::RSM },
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/* 0F AB */ { BxAnother | BxLockable, &BX_CPU_C::BTS_EvGv },
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/* 0F AB */ { BxAnother | BxLockable, &BX_CPU_C::BTS_EwGw },
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/* 0F AC */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHRD_EwGw },
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/* 0F AD */ { BxAnother, &BX_CPU_C::SHRD_EwGw },
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/* 0F AE */ { BxAnother | BxGroup15, NULL, BxOpcodeInfo64G15 },
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@ -985,7 +1002,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
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/* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
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/* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EwGw },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EvGv },
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EwGw },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
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/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GwEb },
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@ -993,9 +1010,9 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
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/* 0F B8 */ { 0, &BX_CPU_C::BxError },
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/* 0F B9 */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
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/* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EvIb },
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/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EvGv },
|
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/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GvEv },
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/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GvEv },
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/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EwGw },
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/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GwEw },
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/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GwEw },
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/* 0F BE */ { BxAnother, &BX_CPU_C::MOVSX_GwEb },
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/* 0F BF */ { BxAnother, &BX_CPU_C::MOVSX_GwEw },
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/* 0F C0 */ { BxAnother | BxLockable, &BX_CPU_C::XADD_EbGb },
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|
|
@ -1494,15 +1511,15 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
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/* 0F A0 */ { 0, &BX_CPU_C::PUSH64_FS },
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/* 0F A1 */ { 0, &BX_CPU_C::POP64_FS },
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/* 0F A2 */ { 0, &BX_CPU_C::CPUID },
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/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EvGv },
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/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EdGd },
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/* 0F A4 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHLD_EdGd },
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/* 0F A5 */ { BxAnother, &BX_CPU_C::SHLD_EdGd },
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/* 0F A6 */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
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/* 0F A7 */ { 0, &BX_CPU_C::CMPXCHG_IBTS },
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/* 0F A6 */ { 0, &BX_CPU_C::BxError },
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/* 0F A7 */ { 0, &BX_CPU_C::BxError },
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/* 0F A8 */ { 0, &BX_CPU_C::PUSH64_GS },
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/* 0F A9 */ { 0, &BX_CPU_C::POP64_GS },
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/* 0F AA */ { 0, &BX_CPU_C::RSM },
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/* 0F AB */ { BxAnother | BxLockable, &BX_CPU_C::BTS_EvGv },
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/* 0F AB */ { BxAnother | BxLockable, &BX_CPU_C::BTS_EdGd },
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/* 0F AC */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHRD_EdGd },
|
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/* 0F AD */ { BxAnother, &BX_CPU_C::SHRD_EdGd },
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/* 0F AE */ { BxAnother | BxGroup15, NULL, BxOpcodeInfo64G15 },
|
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|
|
@ -1510,7 +1527,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
|||
/* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
|
||||
/* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EdGd },
|
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
|
||||
/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EvGv },
|
||||
/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EdGd },
|
||||
/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
|
||||
/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
|
||||
/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GdEb },
|
||||
|
|
@ -1518,9 +1535,9 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
|||
/* 0F B8 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F B9 */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
|
||||
/* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EvIb },
|
||||
/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EvGv },
|
||||
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GvEv },
|
||||
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GvEv },
|
||||
/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EdGd },
|
||||
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GdEd },
|
||||
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GdEd },
|
||||
/* 0F BE */ { BxAnother, &BX_CPU_C::MOVSX_GdEb },
|
||||
/* 0F BF */ { BxAnother, &BX_CPU_C::MOVSX_GdEw },
|
||||
/* 0F C0 */ { BxAnother | BxLockable, &BX_CPU_C::XADD_EbGb },
|
||||
|
|
@ -2016,15 +2033,15 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
|||
/* 0F A0 */ { 0, &BX_CPU_C::PUSH64_FS },
|
||||
/* 0F A1 */ { 0, &BX_CPU_C::POP64_FS },
|
||||
/* 0F A2 */ { 0, &BX_CPU_C::CPUID },
|
||||
/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EvGv },
|
||||
/* 0F A3 */ { BxAnother, &BX_CPU_C::BT_EqGq },
|
||||
/* 0F A4 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHLD_EqGq },
|
||||
/* 0F A5 */ { BxAnother, &BX_CPU_C::SHLD_EqGq },
|
||||
/* 0F A6 */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
|
||||
/* 0F A7 */ { 0, &BX_CPU_C::CMPXCHG_IBTS },
|
||||
/* 0F A6 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F A7 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F A8 */ { 0, &BX_CPU_C::PUSH64_GS },
|
||||
/* 0F A9 */ { 0, &BX_CPU_C::POP64_GS },
|
||||
/* 0F AA */ { 0, &BX_CPU_C::RSM },
|
||||
/* 0F AB */ { BxAnother | BxLockable, &BX_CPU_C::BTS_EvGv },
|
||||
/* 0F AB */ { BxAnother | BxLockable, &BX_CPU_C::BTS_EqGq },
|
||||
/* 0F AC */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::SHRD_EqGq },
|
||||
/* 0F AD */ { BxAnother, &BX_CPU_C::SHRD_EqGq },
|
||||
/* 0F AE */ { BxAnother | BxGroup15, NULL, BxOpcodeInfo64G15 },
|
||||
|
|
@ -2032,7 +2049,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
|||
/* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
|
||||
/* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EqGq },
|
||||
/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
|
||||
/* 0F B3 */ { BxAnother, &BX_CPU_C::BTR_EvGv },
|
||||
/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EqGq },
|
||||
/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
|
||||
/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
|
||||
/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GqEb },
|
||||
|
|
@ -2040,12 +2057,12 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
|||
/* 0F B8 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F B9 */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
|
||||
/* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EvIb },
|
||||
/* 0F BB */ { BxAnother, &BX_CPU_C::BTC_EvGv },
|
||||
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GvEv },
|
||||
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GvEv },
|
||||
/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EqGq },
|
||||
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GqEq },
|
||||
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GqEq },
|
||||
/* 0F BE */ { BxAnother, &BX_CPU_C::MOVSX_GqEb },
|
||||
/* 0F BF */ { BxAnother, &BX_CPU_C::MOVSX_GqEw },
|
||||
/* 0F C0 */ { BxAnother, &BX_CPU_C::XADD_EbGb },
|
||||
/* 0F C0 */ { BxAnother | BxLockable, &BX_CPU_C::XADD_EbGb },
|
||||
/* 0F C1 */ { BxAnother | BxLockable, &BX_CPU_C::XADD_EqGq },
|
||||
/* 0F C2 */ { BxAnother | BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
|
||||
/* 0F C3 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc3 },
|
||||
|
|
@ -2511,8 +2528,7 @@ modrm_done:
|
|||
b1,b2,offset,
|
||||
instruction->modRMForm.rm,
|
||||
mod,
|
||||
nnn
|
||||
));
|
||||
nnn));
|
||||
*/
|
||||
|
||||
// Resolve ExecutePtr and additional opcode Attr
|
||||
|
|
|
|||
Loading…
Reference in New Issue