From 74b87d2b68733464ab314bf1cc272bf28e0201ee Mon Sep 17 00:00:00 2001
From: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
Date: Wed, 12 May 2010 21:33:04 +0000
Subject: [PATCH] fixes for CPUID and alloweds bits in CRs

---
 bochs/cpu/cpu.h     |  8 +++++++-
 bochs/cpu/crregs.cc |  8 ++------
 bochs/cpu/crregs.h  | 30 ++++++++++++++++++------------
 3 files changed, 27 insertions(+), 19 deletions(-)

diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h
index fa0cca727..40d718cb4 100644
--- a/bochs/cpu/cpu.h
+++ b/bochs/cpu/cpu.h
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: cpu.h,v 1.675 2010-05-12 14:55:12 sshwarts Exp $
+// $Id: cpu.h,v 1.676 2010-05-12 21:33:04 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2010  The Bochs Project
@@ -3280,6 +3280,7 @@ public: // for now...
   BX_SMF BX_CPP_INLINE int bx_cpuid_support_vme(void);
   BX_SMF BX_CPP_INLINE int bx_cpuid_support_pae(void);
   BX_SMF BX_CPP_INLINE int bx_cpuid_support_pge(void);
+  BX_SMF BX_CPP_INLINE int bx_cpuid_support_pse(void);
   BX_SMF BX_CPP_INLINE int bx_cpuid_support_pse36(void);
   BX_SMF BX_CPP_INLINE int bx_cpuid_support_pcid(void);
 
@@ -3715,6 +3716,11 @@ BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_debug_extensions(void)
   return (BX_CPU_THIS_PTR cpuid_std_function[1].edx >>  2) & 0x1;
 }
 
+BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_pse(void)
+{
+  return (BX_CPU_THIS_PTR cpuid_std_function[1].edx >>  3) & 0x1;
+}
+
 BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_pae(void)
 {
   return (BX_CPU_THIS_PTR cpuid_std_function[1].edx >>  6) & 0x1;
diff --git a/bochs/cpu/crregs.cc b/bochs/cpu/crregs.cc
index a99d79948..6886631ba 100755
--- a/bochs/cpu/crregs.cc
+++ b/bochs/cpu/crregs.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: crregs.cc,v 1.17 2010-05-12 14:55:12 sshwarts Exp $
+// $Id: crregs.cc,v 1.18 2010-05-12 21:33:04 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2010 Stanislav Shwartsman
@@ -929,17 +929,13 @@ Bit32u BX_CPU_C::get_cr4_allow_mask(void)
   /* VME */
   if (bx_cpuid_support_vme())
     allowMask |= BX_CR4_VME_MASK | BX_CR4_PVI_MASK;
-#endif
 
-#if BX_CPU_LEVEL >= 5
   allowMask |= BX_CR4_TSD_MASK;
-#endif
 
   if (bx_cpuid_support_debug_extensions())
     allowMask |= BX_CR4_DE_MASK;
 
-#if BX_CPU_LEVEL >= 5
-  if (bx_cpuid_support_pse36())
+  if (bx_cpuid_support_pse())
     allowMask |= BX_CR4_PSE_MASK;
 #endif
 
diff --git a/bochs/cpu/crregs.h b/bochs/cpu/crregs.h
index 176ae35c1..cea8cddd9 100755
--- a/bochs/cpu/crregs.h
+++ b/bochs/cpu/crregs.h
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: crregs.h,v 1.28 2010-05-12 18:48:51 sshwarts Exp $
+// $Id: crregs.h,v 1.29 2010-05-12 21:33:04 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2007-2009 Stanislav Shwartsman
@@ -28,12 +28,12 @@ struct bx_cr0_t {
   Bit32u  val32; // 32bit value of register
 
   // Accessors for all cr0 bitfields.
-#define IMPLEMENT_CRREG_ACCESSORS(name,bitnum)               \
-  BX_CPP_INLINE bx_bool get_##name () {                      \
-    return 1 & (val32 >> bitnum);                            \
-  }                                                          \
-  BX_CPP_INLINE void set_##name (Bit8u val) {                \
-    val32 = (val32&~(1<<bitnum)) | (val ? (1<<bitnum) : 0);  \
+#define IMPLEMENT_CRREG_ACCESSORS(name, bitnum)            \
+  BX_CPP_INLINE bx_bool get_##name () {                    \
+    return 1 & (val32 >> bitnum);                          \
+  }                                                        \
+  BX_CPP_INLINE void set_##name (Bit8u val) {              \
+    val32 = (val32 & ~(1<<bitnum)) | ((!!val) << bitnum);  \
   }
 
 // CR0 notes:
@@ -112,9 +112,7 @@ struct bx_cr4_t {
 #if BX_SUPPORT_X86_64
   IMPLEMENT_CRREG_ACCESSORS(PCIDE, 17);
 #endif
-#if BX_CPU_LEVEL >= 6
   IMPLEMENT_CRREG_ACCESSORS(OSXSAVE, 18);
-#endif
 
   BX_CPP_INLINE Bit32u get32() { return val32; }
   BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
@@ -127,6 +125,12 @@ struct bx_cr4_t {
 
 #if BX_SUPPORT_X86_64
 
+#define BX_EFER_SCE_MASK       (1 <<  0)
+#define BX_EFER_LME_MASK       (1 <<  8)
+#define BX_EFER_LMA_MASK       (1 << 10)
+#define BX_EFER_NXE_MASK       (1 << 11)
+#define BX_EFER_FFXSR_MASK     (1 << 14)
+
 struct bx_efer_t {
   Bit32u val32; // 32bit value of register
 
@@ -134,15 +138,17 @@ struct bx_efer_t {
   IMPLEMENT_CRREG_ACCESSORS(LME,    8);
   IMPLEMENT_CRREG_ACCESSORS(LMA,   10);
   IMPLEMENT_CRREG_ACCESSORS(NXE,   11);
+  IMPLEMENT_CRREG_ACCESSORS(SVME,  12); /* AMD Secure Virtual Machine */
+  IMPLEMENT_CRREG_ACCESSORS(LMSLE, 13); /* AMD Long Mode Segment Limit */
   IMPLEMENT_CRREG_ACCESSORS(FFXSR, 14);
 
   BX_CPP_INLINE Bit32u get32() { return val32; }
   BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
 };
 
-#define BX_EFER_LME_MASK       (1 <<  8)
-#define BX_EFER_LMA_MASK       (1 << 10)
-#define BX_EFER_SUPPORTED_BITS BX_CONST64(0x00004d01)
+#define BX_EFER_SUPPORTED_BITS \
+   ((Bit64u) (BX_EFER_SCE_MASK | BX_EFER_LME_MASK | \
+              BX_EFER_LMA_MASK | BX_EFER_NXE_MASK | BX_EFER_FFXSR_MASK))
 
 #endif