diff --git a/bochs/cpu/debugstuff.cc b/bochs/cpu/debugstuff.cc
index accefea15..ac843edd3 100644
--- a/bochs/cpu/debugstuff.cc
+++ b/bochs/cpu/debugstuff.cc
@@ -147,10 +147,8 @@ void BX_CPU_C::debug(bx_address offset)
   else
 #endif
   {
-    BX_INFO(("| EAX=%08x  EBX=%08x  ECX=%08x  EDX=%08x",
-          (unsigned) EAX, (unsigned) EBX, (unsigned) ECX, (unsigned) EDX));
-    BX_INFO(("| ESP=%08x  EBP=%08x  ESI=%08x  EDI=%08x",
-          (unsigned) ESP, (unsigned) EBP, (unsigned) ESI, (unsigned) EDI));
+    BX_INFO(("| EAX=%08x  EBX=%08x  ECX=%08x  EDX=%08x", EAX, EBX, ECX, EDX));
+    BX_INFO(("| ESP=%08x  EBP=%08x  ESI=%08x  EDI=%08x", ESP, EBP, ESI, EDI));
   }
   BX_INFO(("| IOPL=%1u %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s",
     BX_CPU_THIS_PTR get_IOPL(),
diff --git a/bochs/cpu/fetchdecode.cc b/bochs/cpu/fetchdecode.cc
index 87797f694..5cb47f3da 100644
--- a/bochs/cpu/fetchdecode.cc
+++ b/bochs/cpu/fetchdecode.cc
@@ -1909,6 +1909,9 @@ modrm_done:
     case BX_SRC_RM:
       i->setSrcReg(n, mod_mem ? BX_TMP_REGISTER : rm);
       break;
+    case BX_SRC_VEC_RM:
+      i->setSrcReg(n, mod_mem ? BX_VECTOR_TMP_REGISTER : rm);
+      break;
 #if BX_SUPPORT_AVX
     case BX_SRC_MEM_NO_VVV:
       if (mod_mem) break;
diff --git a/bochs/cpu/fetchdecode.h b/bochs/cpu/fetchdecode.h
index baf60a362..c1b18b737 100644
--- a/bochs/cpu/fetchdecode.h
+++ b/bochs/cpu/fetchdecode.h
@@ -73,6 +73,7 @@ enum {
   BX_SRC_EAX,
   BX_SRC_NNN,
   BX_SRC_RM,
+  BX_SRC_VEC_RM, // will use vector TMP register
   BX_SRC_MEM_NO_VVV,
   BX_SRC_VVV,
   BX_SRC_VIB
diff --git a/bochs/cpu/fetchdecode64.cc b/bochs/cpu/fetchdecode64.cc
index 2d7767a1b..f31875cdf 100644
--- a/bochs/cpu/fetchdecode64.cc
+++ b/bochs/cpu/fetchdecode64.cc
@@ -2340,6 +2340,9 @@ modrm_done:
     case BX_SRC_RM:
       i->setSrcReg(n, mod_mem ? BX_TMP_REGISTER : rm);
       break;
+    case BX_SRC_VEC_RM:
+      i->setSrcReg(n, mod_mem ? BX_VECTOR_TMP_REGISTER : rm);
+      break;
 #if BX_SUPPORT_AVX
     case BX_SRC_MEM_NO_VVV:
       if (mod_mem) break;
diff --git a/bochs/cpu/ia_opcodes.h b/bochs/cpu/ia_opcodes.h
index 0579adb55..1401966d0 100644
--- a/bochs/cpu/ia_opcodes.h
+++ b/bochs/cpu/ia_opcodes.h
@@ -871,10 +871,11 @@ bx_define_opcode(BX_IA_PREFETCH, &BX_CPU_C::PREFETCH, &BX_CPU_C::NOP, BX_ISA_SSE
 // SSE
 
 // SSE and SSE2
-bx_define_opcode(BX_IA_ANDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ORPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_XORPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ANDNPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDNPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ANDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ORPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_XORPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ANDNPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDNPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+
 bx_define_opcode(BX_IA_MOVUPS_VpsWps, &BX_CPU_C::MOVUPS_VpsWpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVUPS_WpsVps, &BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVSS_VssWss, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
@@ -885,25 +886,25 @@ bx_define_opcode(BX_IA_MOVHPS_VpsMq, &BX_CPU_C::MOVHPS_VpsMq, &BX_CPU_C::MOVLHPS
 bx_define_opcode(BX_IA_MOVHPS_MqVps, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_ISA_SSE, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVAPS_VpsWps, &BX_CPU_C::MOVAPS_VpsWpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVAPS_WpsVps, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MOVNTPS_MpsVps, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_SSE, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTPI2PS_VpsQq, &BX_CPU_C::CVTPI2PS_VpsQqM, &BX_CPU_C::CVTPI2PS_VpsQqR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTSI2SS_VssEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CVTSI2SS_VssEdR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MOVNTPS_MpsVps, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_SSE, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTTPS2PI_PqWps, &BX_CPU_C::CVTTPS2PI_PqWps, &BX_CPU_C::CVTTPS2PI_PqWps, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTPS2PI_PqWps, &BX_CPU_C::CVTPS2PI_PqWps, &BX_CPU_C::CVTPS2PI_PqWps, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_COMISS_VpsWps, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_UCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_COMISS_VpsWps, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVMSKPS_GdVRps, &BX_CPU_C::BxError, &BX_CPU_C::MOVMSKPS_GdVRps, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_RSQRTPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::RSQRTPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_RSQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RSQRTSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_RCPPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::RCPPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_RCPSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RCPSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_RSQRTPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::RSQRTPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_RSQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RSQRTSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_RCPPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::RCPPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_RCPSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RCPSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PSHUFW_PqQqIb, &BX_CPU_C::PSHUFW_PqQqIb, &BX_CPU_C::PSHUFW_PqQqIb, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_PSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFLW_VdqWdqIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFLW_VdqWdqIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PINSRW_PqEwIb, &BX_CPU_C::PINSRW_PqEwIb, &BX_CPU_C::PINSRW_PqEwIb, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
 bx_define_opcode(BX_IA_PEXTRW_GdPqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdPqIb, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_SHUFPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPS_VpsWpsIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHUFPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPS_VpsWpsIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PMOVMSKB_GdPRq, &BX_CPU_C::BxError, &BX_CPU_C::PMOVMSKB_GdPRq, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
 bx_define_opcode(BX_IA_PMINUB_PqQq, &BX_CPU_C::PMINUB_PqQq, &BX_CPU_C::PMINUB_PqQq, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
 bx_define_opcode(BX_IA_PMAXUB_PqQq, &BX_CPU_C::PMAXUB_PqQq, &BX_CPU_C::PMAXUB_PqQq, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
@@ -917,50 +918,50 @@ bx_define_opcode(BX_IA_PSADBW_PqQq, &BX_CPU_C::PSADBW_PqQq, &BX_CPU_C::PSADBW_Pq
 bx_define_opcode(BX_IA_MASKMOVQ_PqPRq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVQ_PqPRq, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NONE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, 0)
 
 // SSE alias
-bx_define_opcode(BX_IA_ADDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ADDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ADDSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::ADDSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ADDSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::ADDSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ADDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ADDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ADDSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::ADDSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ADDSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::ADDSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 
-bx_define_opcode(BX_IA_MULPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MULPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MULSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MULSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MULSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MULSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MULPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MULPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MULSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MULSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MULSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MULSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 
-bx_define_opcode(BX_IA_SUBPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SUBSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::SUBSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SUBSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::SUBSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SUBPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SUBSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::SUBSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SUBSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::SUBSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 
-bx_define_opcode(BX_IA_MINPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MINPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MINPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MINPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MINSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MINSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MINSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MINSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MINPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MINPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MINPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MINPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MINSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MINSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MINSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MINSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 
-bx_define_opcode(BX_IA_DIVPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DIVPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DIVPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DIVPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DIVSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::DIVSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DIVSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::DIVSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_DIVPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DIVPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_DIVPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DIVPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_DIVSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::DIVSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_DIVSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::DIVSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 
-bx_define_opcode(BX_IA_MAXPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MAXPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MAXSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MAXSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MAXSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MAXSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MAXPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MAXPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MAXSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MAXSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MAXSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MAXSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 
-bx_define_opcode(BX_IA_SQRTPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SQRTPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::SQRTSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SQRTSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::SQRTSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SQRTPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SQRTPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::SQRTSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SQRTSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::SQRTSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 
-bx_define_opcode(BX_IA_CMPPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPS_VpsWpsIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPD_VpdWpdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPSS_VssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CMPSS_VssWssIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CMPSD_VsdWsdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CMPPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPS_VpsWpsIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CMPPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPD_VpdWpdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CMPSS_VssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CMPSS_VssWssIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CMPSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CMPSD_VsdWsdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 
-bx_define_opcode(BX_IA_CVTPS2PD_VpdWps, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTPS2PD_VpdWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTPD2PS_VpsWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPD2PS_VpsWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SD_VsdWssR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SS_VssWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTPS2PD_VpdWps, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTPS2PD_VpdWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTPD2PS_VpsWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPD2PS_VpsWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SD_VsdWssR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SS_VssWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 // SSE alias
 
 bx_define_opcode(BX_IA_MOVSD_VsdWsd, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
@@ -968,19 +969,19 @@ bx_define_opcode(BX_IA_MOVSD_WsdVsd, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVSD_
 bx_define_opcode(BX_IA_CVTPI2PD_VpdQq, &BX_CPU_C::CVTPI2PD_VpdQqM, &BX_CPU_C::CVTPI2PD_VpdQqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTSI2SD_VsdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CVTSI2SD_VsdEdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTTPD2PI_PqWpd, &BX_CPU_C::CVTTPD2PI_PqWpd, &BX_CPU_C::CVTTPD2PI_PqWpd, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTPD2PI_PqWpd, &BX_CPU_C::CVTPD2PI_PqWpd, &BX_CPU_C::CVTPD2PI_PqWpd, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_COMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_UCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_COMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVMSKPD_GdVRpd, &BX_CPU_C::BxError, &BX_CPU_C::MOVMSKPD_GdVRpd, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTDQ2PS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTDQ2PS_VpsWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPS2DQ_VdqWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTTPS2DQ_VdqWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UNPCKHPD_VpdWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UNPCKLPD_VpdWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKHDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKHPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKLDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKLPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTDQ2PS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTDQ2PS_VpsWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPS2DQ_VdqWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTTPS2DQ_VdqWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_UNPCKHPD_VpdWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_UNPCKLPD_VpdWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PUNPCKHDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKHPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PUNPCKLDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKLPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVAPD_VpdWpd, &BX_CPU_C::MOVAPS_VpsWpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVAPD_WpdVpd, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVDQA_VdqWdq, &BX_CPU_C::MOVAPS_VpsWpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
@@ -995,87 +996,87 @@ bx_define_opcode(BX_IA_MOVNTDQ_MdqVdq, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::BxE
 bx_define_opcode(BX_IA_MOVNTPD_MpdVpd, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVUPD_VpdWpd, &BX_CPU_C::MOVUPS_VpsWpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVUPD_WpdVpd, &BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ANDNPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDNPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ANDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ORPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_XORPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PAND_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PANDN_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDNPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_POR_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PXOR_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKLBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKLWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UNPCKLPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKLPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PACKSSWB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKSSWB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPGTB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPGTW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPGTD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PACKUSWB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKUSWB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKHBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKHWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UNPCKHPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKHPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PACKSSDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKSSDW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKLQDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKHQDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ANDNPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDNPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ANDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ORPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_XORPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PAND_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PANDN_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDNPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_POR_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PXOR_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PUNPCKLBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PUNPCKLWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_UNPCKLPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKLPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PACKSSWB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKSSWB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPGTB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPGTW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPGTD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PACKUSWB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKUSWB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PUNPCKHBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PUNPCKHWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_UNPCKHPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKHPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PACKSSDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKSSDW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PUNPCKLQDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PUNPCKHQDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVD_VdqEd, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVD_VdqEdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFD_VdqWdqIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSHUFHW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFHW_VdqWdqIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPEQB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPEQW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPEQD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFD_VdqWdqIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSHUFHW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFHW_VdqWdqIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPEQB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPEQW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPEQD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVNTI32_MdGd, &BX_CPU_C::MOV32_EdGdM, &BX_CPU_C::BxError, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, 0)
 bx_define_opcode(BX_IA_PINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::PINSRW_VdqHdqEwIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHUFPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPD_VpdWpdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSRLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSRLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSRLQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHUFPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPD_VpdWpdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSRLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSRLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSRLQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PADDQ_PqQq, &BX_CPU_C::PADDQ_PqQq, &BX_CPU_C::PADDQ_PqQq, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_PADDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULLW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PADDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMULLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULLW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVQ_WqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVDQ2Q_PqVRq, &BX_CPU_C::BxError, &BX_CPU_C::MOVDQ2Q_PqVRq, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVQ2DQ_VdqQq, &BX_CPU_C::BxError, &BX_CPU_C::MOVQ2DQ_VdqQq, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::PMOVMSKB_GdUdq, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBUSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBUSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBUSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBUSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINUB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINUB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDUSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDUSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDUSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDUSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXUB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXUB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PAVGB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PAVGB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSRAW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRAW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSRAD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRAD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PAVGW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PAVGW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULHUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULHUW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULHW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULHW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTTPD2DQ_VqWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPD2DQ_VqWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTDQ2PD_VpdWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTDQ2PD_VpdWqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSLLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSLLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSLLQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSUBUSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBUSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSUBUSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBUSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMINUB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINUB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PADDUSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDUSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PADDUSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDUSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMAXUB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXUB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PAVGB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PAVGB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSRAW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRAW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSRAD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRAD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PAVGW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PAVGW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMULHUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULHUW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMULHW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULHW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTTPD2DQ_VqWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPD2DQ_VqWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTDQ2PD_VpdWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTDQ2PD_VpdWqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSUBSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMINSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PADDSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PADDSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMAXSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSLLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSLLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSLLQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PMULUDQ_PqQq, &BX_CPU_C::PMULUDQ_PqQq, &BX_CPU_C::PMULUDQ_PqQq, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_PMULUDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULUDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMADDWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMADDWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSADBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSADBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMULUDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULUDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMADDWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMADDWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSADBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSADBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVDQU_VdqUdq, BX_ISA_SSE2, BX_SRC_NONE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSUBB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSUBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSUBD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PSUBQ_PqQq, &BX_CPU_C::PSUBQ_PqQq, &BX_CPU_C::PSUBQ_PqQq, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_PSUBQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSUBQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PADDB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PADDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PADDD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PSRLW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLW_UdqIb, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PSRAW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRAW_UdqIb, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PSLLW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLW_UdqIb, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
@@ -1093,15 +1094,15 @@ bx_define_opcode(BX_IA_MFENCE, &BX_CPU_C::BxError, &BX_CPU_C::NOP, BX_ISA_SSE2,
 // SSE and SSE2
 
 // SSE3
-bx_define_opcode(BX_IA_MOVDDUP_VpdWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MOVDDUP_VpdWqR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MOVSLDUP_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MOVSHDUP_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_HADDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HADDPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_HADDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HADDPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_HSUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HSUBPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_HSUBPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HSUBPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ADDSUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDSUBPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ADDSUBPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDSUBPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MOVDDUP_VpdWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MOVDDUP_VpdWqR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MOVSLDUP_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MOVSHDUP_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_HADDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HADDPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_HADDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HADDPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_HSUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HSUBPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_HSUBPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HSUBPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ADDSUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDSUBPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ADDSUBPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDSUBPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_LDDQU_VdqMdq, &BX_CPU_C::MOVUPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 // SSE3
 
@@ -1124,61 +1125,61 @@ bx_define_opcode(BX_IA_PABSW_PqQq, &BX_CPU_C::PABSW_PqQq, &BX_CPU_C::PABSW_PqQq,
 bx_define_opcode(BX_IA_PABSD_PqQq, &BX_CPU_C::PABSD_PqQq, &BX_CPU_C::PABSD_PqQq, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
 bx_define_opcode(BX_IA_PALIGNR_PqQqIb, &BX_CPU_C::PALIGNR_PqQqIb, &BX_CPU_C::PALIGNR_PqQqIb, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
 
-bx_define_opcode(BX_IA_PSHUFB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHADDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHADDW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHADDD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHADDD_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHADDSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHADDSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMADDUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMADDUBSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHSUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHSUBSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHSUBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHSUBW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHSUBD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHSUBD_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSIGNB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSIGNB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSIGNW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSIGNW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSIGND_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSIGND_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULHRSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULHRSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PABSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PABSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PABSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSD_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PALIGNR_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PALIGNR_VdqWdqIbR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSHUFB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PHADDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHADDW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PHADDD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHADDD_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PHADDSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHADDSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMADDUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMADDUBSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PHSUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHSUBSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PHSUBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHSUBW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PHSUBD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHSUBD_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSIGNB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSIGNB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSIGNW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSIGNW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PSIGND_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSIGND_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMULHRSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULHRSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PABSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PABSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PABSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSD_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PALIGNR_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PALIGNR_VdqWdqIbR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 // SSSE3
 
 // SSE4.1
-bx_define_opcode(BX_IA_PBLENDVB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PBLENDVB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_BLENDVPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDVPS_VpsWpsR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_BLENDVPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDVPD_VpdWpdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PTEST_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PTEST_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULDQ_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPEQQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQQ_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PACKUSDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKUSDW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXBW_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXBD_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVSXBQ_VdqWwR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXWD_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXWQ_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXDQ_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXBW_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXBD_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVZXBQ_VdqWwR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXWD_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXWQ_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXDQ_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINSB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINSD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINUD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINUD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXSB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXSD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXUD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXUD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULLD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHMINPOSUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ROUNDPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ROUNDPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ROUNDPD_VpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ROUNDSS_VssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::ROUNDSS_VssWssIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ROUNDSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::ROUNDSD_VsdWsdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_BLENDPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_BLENDPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDPD_VpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PBLENDW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PBLENDW_VdqWdqIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PBLENDVB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PBLENDVB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_BLENDVPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDVPS_VpsWpsR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_BLENDVPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDVPD_VpdWpdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PTEST_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PTEST_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMULDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULDQ_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPEQQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQQ_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PACKUSDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKUSDW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVSXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXBW_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXBD_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVSXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVSXBQ_VdqWwR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVSXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXWD_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVSXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXWQ_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVSXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXDQ_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVZXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXBW_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVZXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXBD_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVZXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVZXBQ_VdqWwR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVZXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXWD_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVZXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXWQ_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMOVZXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXDQ_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMINSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINSB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMINSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINSD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMINUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMINUD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINUD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMAXSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXSB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMAXSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXSD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMAXUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMAXUD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXUD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PMULLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULLD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PHMINPOSUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ROUNDPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ROUNDPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ROUNDPD_VpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ROUNDSS_VssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::ROUNDSS_VssWssIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_ROUNDSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::ROUNDSD_VsdWsdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_BLENDPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_BLENDPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDPD_VpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PBLENDW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PBLENDW_VdqWdqIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, &BX_CPU_C::PEXTRB_EbdVdqIbR, BX_ISA_SSE4_1, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_CPU_C::PEXTRW_EwdVdqIbR, BX_ISA_SSE4_1, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_SSE4_1, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
@@ -1186,9 +1187,9 @@ bx_define_opcode(BX_IA_EXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU
 bx_define_opcode(BX_IA_PINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqHdqEbIbM, &BX_CPU_C::PINSRB_VdqHdqEbIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_INSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_PINSRD_VdqEdIb, &BX_CPU_C::PINSRD_VdqHdqEdIbM, &BX_CPU_C::PINSRD_VdqHdqEdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DPPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DPPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DPPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DPPD_VpdHpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MPSADBW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MPSADBW_VdqWdqIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_DPPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DPPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_DPPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DPPD_VpdHpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_MPSADBW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MPSADBW_VdqWdqIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVNTDQA_VdqMdq, &BX_CPU_C::MOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 // SSE4.1
 
@@ -1199,11 +1200,11 @@ bx_define_opcode(BX_IA_CRC32_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CRC32_GdEdR, B
 #if BX_SUPPORT_X86_64
 bx_define_opcode(BX_IA_CRC32_GdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::CRC32_GdEqR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
 #endif
-bx_define_opcode(BX_IA_PCMPGTQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTQ_VdqWdqR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPESTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPISTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPISTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPGTQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTQ_VdqWdqR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPESTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPISTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCMPISTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 // SSE4.2
 
 // MOVBE instruction
@@ -1239,22 +1240,22 @@ bx_define_opcode(BX_IA_XSAVEOPT, &BX_CPU_C::XSAVE, &BX_CPU_C::BxError, BX_ISA_XS
 #if BX_CPU_LEVEL >= 6
 
 // AES instructions
-bx_define_opcode(BX_IA_AESIMC_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_AESENC_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESENC_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_AESENCLAST_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESENCLAST_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_AESDEC_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESDEC_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_AESDECLAST_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESDECLAST_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_AESKEYGENASSIST_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCLMULQDQ_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCLMULQDQ_VdqHdqWdqIbR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_AESIMC_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_AESENC_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESENC_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_AESENCLAST_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESENCLAST_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_AESDEC_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESDEC_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_AESDECLAST_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESDECLAST_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_AESKEYGENASSIST_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_PCLMULQDQ_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCLMULQDQ_VdqHdqWdqIbR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
 
 // SHA instructions
-bx_define_opcode(BX_IA_SHA1NEXTE_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1NEXTE_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA1MSG1_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1MSG1_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA1MSG2_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1MSG2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA256RNDS2_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA256RNDS2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA256MSG1_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA256MSG1_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA256MSG2_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA256MSG2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA1RNDS4_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1RNDS4_VdqWdqIbR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHA1NEXTE_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1NEXTE_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHA1MSG1_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1MSG1_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHA1MSG2_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1MSG2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHA256RNDS2_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA256RNDS2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHA256MSG1_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA256MSG1_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHA256MSG2_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA256MSG2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHA1RNDS4_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1RNDS4_VdqWdqIbR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 
 #endif
 
@@ -1468,10 +1469,10 @@ bx_define_opcode(BX_IA_MOVQ_PqEq, &BX_CPU_C::MOVQ_PqQqM, &BX_CPU_C::MOVQ_PqEqR,
 bx_define_opcode(BX_IA_MOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::CVTSI2SS_VssEqR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::CVTSI2SD_VsdEqR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GqWsdR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, 0, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GqWsdR, 0, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, 0, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, 0, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVNTI64_MdGd, &BX_CPU_C::MOV64_EdGdM, &BX_CPU_C::BxError, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, 0)
 bx_define_opcode(BX_IA_MOVNTI_MqGq, &BX_CPU_C::MOV_EqGqM, &BX_CPU_C::BxError, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, 0)
 bx_define_opcode(BX_IA_MOV_CR0Rq, NULL, &BX_CPU_C::MOV_CR0Rq, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
@@ -1584,10 +1585,10 @@ bx_define_opcode(BX_IA_V128_VMOVLPD_MqVsd, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::
 bx_define_opcode(BX_IA_V128_VMOVHPD_MqVsd, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VMOVLPD_VpdHpdMq, &BX_CPU_C::VMOVLPD_VpdHpdMq, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VMOVHPD_VpdHpdMq, &BX_CPU_C::VMOVHPD_VpdHpdMq, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VLDDQU_VdqMdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 
@@ -1599,239 +1600,239 @@ bx_define_opcode(BX_IA_V256_VMOVNTPS_MpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU
 bx_define_opcode(BX_IA_V256_VMOVNTPD_MpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V256_VMOVNTDQ_MdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCOMISS_VpsWps, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VUCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCOMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VRSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRSQRTSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VRSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRSQRTPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VRCPSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRCPSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VRCPPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRCPPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VANDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VANDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VANDNPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VANDNPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VXORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VXORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VHADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VHADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VHSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VHSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSHUFPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSHUFPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VADDSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VADDSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VROUNDPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPD_VpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VROUNDSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VROUNDSD_VsdHpdWsdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VROUNDSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VROUNDSS_VssHpsWssIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VDPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDPPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VDPPD_VpdHpdWpdIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::DPPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCOMISS_VpsWps, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VUCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCOMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VRSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRSQRTSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VRSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRSQRTPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VRCPSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRCPSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VRCPPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRCPPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VANDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VANDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VANDNPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VANDNPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VXORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VXORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VHADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VHADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VHSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VHSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSHUFPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSHUFPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VADDSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VADDSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VROUNDPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPD_VpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VROUNDSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VROUNDSD_VsdHpdWsdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VROUNDSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VROUNDSS_VssHpsWssIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VDPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDPPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VDPPD_VpdHpdWpdIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::DPPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
 // SSE alias
-bx_define_opcode(BX_IA_VADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VADDSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VADDSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VADDSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VADDSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VMULPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMULPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMULSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMULSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMULPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMULPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMULSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMULSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSUBSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSUBSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSUBSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSUBSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VDIVPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VDIVPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VDIVSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VDIVSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VDIVPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VDIVPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VDIVSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VDIVSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VMAXPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMAXPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMAXSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMAXSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMAXPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMAXPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMAXSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMAXSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VMINPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMINPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMINSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMINSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMINPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMINPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMINSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VMINSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSQRTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPD_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSQRTSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSQRTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPD_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSQRTSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VCMPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCMPPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCMPSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCMPSS_VssHpsWssIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCMPSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCMPSD_VsdHpdWsdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCMPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCMPPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCMPSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCMPSS_VssHpsWssIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCMPSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCMPSD_VsdHpdWsdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 // SSE alias
 
-bx_define_opcode(BX_IA_V128_VPSRLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSRLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSRLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSRAW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSLLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSLLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSLLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSRLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLW_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSRAW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAW_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSLLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLW_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSRLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLD_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSRAD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSLLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLD_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSRLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSLLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSRLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLDQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSLLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLDQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRAW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSLLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSLLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSLLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLW_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRAW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAW_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSLLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLW_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLD_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRAD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSLLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLD_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSLLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSRLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLDQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSLLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLDQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 
 bx_define_opcode(BX_IA_V128_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VMOVMSKPS_GdVRps, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPS_GdVRps, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VMOVMSKPD_GdVRpd, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPD_GdVRpd, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VUNPCKLPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VUNPCKLPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VUNPCKHPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPUNPCKLBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKLBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPUNPCKLWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKLWD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPUNPCKHBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKHBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPUNPCKHWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKHWD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPEQB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPEQW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPEQD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPEQQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPGTB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPGTW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPGTD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPGTQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSUBSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPADDSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPADDSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSUBUSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBUSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSUBUSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBUSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPADDUSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDUSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPADDUSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDUSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPAVGB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPAVGB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPAVGW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPAVGW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPANDN_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPAND_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPOR_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPXOR_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMULHRSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHRSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMULLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULLW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMULHW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHUW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VUNPCKLPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VUNPCKLPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VUNPCKHPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPUNPCKLBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKLBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPUNPCKLWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKLWD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPUNPCKHBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKHBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPUNPCKHWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKHWD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPEQB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPEQW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPEQD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPEQQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPGTB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPGTW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPGTD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPGTQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSUBSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPADDSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPADDSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSUBUSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBUSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSUBUSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBUSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPADDUSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDUSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPADDUSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDUSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPAVGB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPAVGB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPAVGW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPAVGW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPANDN_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPAND_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPOR_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPXOR_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMULHRSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHRSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMULLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULLW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMULHW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHUW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VMASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVDQU_VdqUdq, BX_ISA_AVX, BX_SRC_NONE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSUBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPADDB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPADDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPADDD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSHUFB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPHADDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPHADDD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPHSUBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPHSUBD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPHADDSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPHSUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMADDWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADDWD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMADDUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADDUBSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSIGNB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGNB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSIGNW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGNW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSIGND_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGND_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VTESTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VTESTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPD_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPTEST_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPTEST_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VBROADCASTSS_VpsMss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_VdqWd, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VBROADCASTSD_VpdMsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWq, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSUBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPADDB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPADDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPADDD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSHUFB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPHADDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPHADDD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPHSUBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPHSUBD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPHADDSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPHSUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMADDWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADDWD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMADDUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADDUBSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSIGNB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGNB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSIGNW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGNW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPSIGND_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGND_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VTESTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VTESTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPD_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPTEST_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPTEST_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VBROADCASTSS_VpsMss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_VdqWd, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VBROADCASTSD_VpdMsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWq, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V256_VBROADCASTF128_VdqMdq, &BX_CPU_C::VBROADCASTF128_VdqMdq, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPABSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSB_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPABSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSW_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPABSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSD_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPACKSSWB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKSSWB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPACKUSWB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKUSWB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPACKUSDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKUSDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPACKSSDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKSSDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPABSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSB_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPABSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSW_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPABSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSD_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPACKSSWB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKSSWB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPACKUSWB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKUSWB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPACKUSDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKUSDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPACKSSDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKSSDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VMASKMOVPS_VpsHpsMps, &BX_CPU_C::VMASKMOVPS_VpsHpsMps, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VMASKMOVPS_MpsHpsVps, &BX_CPU_C::VMASKMOVPS_MpsHpsVps, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXBW_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXBD_VdqWdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVSXBQ_VdqWwR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXWD_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXWQ_VdqWdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXDQ_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXBW_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXBD_VdqWdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVZXBQ_VdqWwR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXWD_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXWQ_VdqWdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXDQ_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMINSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMINSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMINUB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMINUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMAXSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMAXSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMAXUB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMAXUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPHMINPOSUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPERMILPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPERMILPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPERMILPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPERMILPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VBLENDPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VBLENDPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPBLENDW_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPBLENDW_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPALIGNR_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXBW_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXBD_VdqWdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVSXBQ_VdqWwR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXWD_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXWQ_VdqWdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXDQ_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXBW_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXBD_VdqWdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVZXBQ_VdqWwR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXWD_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXWQ_VdqWdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXDQ_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMINSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMINSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMINUB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMINUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMAXSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMAXSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMAXUB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMAXUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPHMINPOSUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPERMILPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPERMILPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPERMILPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPERMILPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VBLENDPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VBLENDPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPBLENDW_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPBLENDW_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPALIGNR_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPERM2F128_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VINSERTF128_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPERM2F128_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VINSERTF128_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V256_VEXTRACTF128_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VBLENDVPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VBLENDVPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VMPSADBW_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VBLENDVPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VBLENDVPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VMPSADBW_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_V128_VPCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPESTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPISTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCMPISTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPESTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPISTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCMPISTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_V128_VAESIMC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VAESENC_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESENC_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VAESENCLAST_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESENCLAST_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VAESDEC_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESDEC_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VAESDECLAST_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESDECLAST_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VAESKEYGENASSIST_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPCLMULQDQ_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCLMULQDQ_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VAESIMC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VAESENC_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESENC_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VAESENCLAST_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESENCLAST_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VAESDEC_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESDEC_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VAESDECLAST_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESDECLAST_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VAESKEYGENASSIST_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPCLMULQDQ_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCLMULQDQ_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
 bx_define_opcode(BX_IA_V128_VMOVD_VdqEd, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVD_VdqEdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VMOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
@@ -1844,170 +1845,170 @@ bx_define_opcode(BX_IA_V128_VPEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, &BX_C
 bx_define_opcode(BX_IA_V128_VPEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_CPU_C::PEXTRW_EwdVdqIbR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VPEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VPEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VCVTPS2PD_VpdWps, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTPS2PD_VpdWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VCVTPS2PD_VpdWps, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VCVTPS2PD_VpdWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPD2DQ_VqWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2DQ_VqWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VCVTDQ2PD_VpdWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTDQ2PD_VpdWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VCVTDQ2PD_VpdWq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VCVTDQ2PD_VpdWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTPD2PS_VpsWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2PS_VpsWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2SS_VssWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2SD_VsdWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTDQ2PS_VpsWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTDQ2PS_VpsWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPS2DQ_VdqWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPS2DQ_VdqWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VCVTPS2PD_VpdWps, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTPS2PD_VpdWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VCVTPS2PD_VpdWps, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VCVTPS2PD_VpdWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPD2DQ_VqWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2DQ_VqWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VCVTDQ2PD_VpdWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTDQ2PD_VpdWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VCVTDQ2PD_VpdWq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VCVTDQ2PD_VpdWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTPD2PS_VpsWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2PS_VpsWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2SS_VssWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2SD_VsdWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTDQ2PS_VpsWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTDQ2PS_VpsWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPS2DQ_VdqWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPS2DQ_VdqWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VCVTSI2SD_VsdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTSI2SD_VsdEdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VCVTSI2SS_VssEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTSI2SS_VssEdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VCVTSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTSI2SD_VsdEqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VCVTSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTSI2SS_VssEqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GqWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GqWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VMOVQ_WqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VMOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VMOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VMOVQ_EqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_EqVqR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_V128_VCVTPH2PS_VpsWps, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_ISA_AVX_F16C, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VCVTPH2PS_VpsWps, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_ISA_AVX_F16C, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VCVTPH2PS_VpsWps, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_ISA_AVX_F16C, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VCVTPH2PS_VpsWps, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_ISA_AVX_F16C, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, BX_ISA_AVX_F16C, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 // AVX
 
 // AVX2
-bx_define_opcode(BX_IA_V256_VPCMPEQB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPCMPEQW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPCMPEQD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPCMPEQQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPCMPGTB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPCMPGTW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPCMPGTD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPCMPGTQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMINSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMINSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMINUB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMINUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMAXSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMAXSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMAXUB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMAXUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSIGNB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGNB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSIGNW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGNW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSIGND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGND_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPANDN_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPAND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPXOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSUBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPADDB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPADDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPABSB_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSB_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPABSW_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSW_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPABSD_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSD_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSUBSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPADDSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPADDSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSUBUSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBUSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSUBUSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBUSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPADDUSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDUSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPADDUSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDUSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPAVGB_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPAVGB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPAVGW_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPAVGW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPHADDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPHADDD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPHSUBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPHSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPHADDSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPHSUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPACKSSWB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKSSWB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPACKUSWB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKUSWB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPACKUSDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKUSDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPACKSSDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKSSDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPUNPCKLBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKLBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPUNPCKLWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKLWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPUNPCKHBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKHBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPUNPCKHWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKHWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMULLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMULHW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMULHRSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHRSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMADDUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPMADDWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMPSADBW_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPBLENDW_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDW_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPCMPEQB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPCMPEQW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPCMPEQD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPCMPEQQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPCMPGTB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPCMPGTW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPCMPGTD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPCMPGTQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMINSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMINSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMINUB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMINUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMAXSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMAXSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMAXUB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMAXUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSIGNB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGNB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSIGNW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGNW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSIGND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGND_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPANDN_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPAND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPXOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSUBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPADDB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPADDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPABSB_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSB_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPABSW_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSW_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPABSD_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSD_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSUBSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPADDSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPADDSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSUBUSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBUSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSUBUSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBUSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPADDUSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDUSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPADDUSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDUSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPAVGB_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPAVGB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPAVGW_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPAVGW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPHADDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPHADDD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPHSUBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPHSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPHADDSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPHSUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPACKSSWB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKSSWB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPACKUSWB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKUSWB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPACKUSDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKUSDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPACKSSDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKSSDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPUNPCKLBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKLBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPUNPCKLWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKLWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPUNPCKHBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKHBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPUNPCKHWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKHWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMULLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMULHW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMULHRSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHRSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMADDUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPMADDWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMPSADBW_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPBLENDW_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDW_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V256_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSHUFB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSHUFB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V256_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRLQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRAW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSLLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSLLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSLLQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRLW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRAW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSLLW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRLD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRAD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSLLD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRLQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSLLQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSRLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLDQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPSLLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLDQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPALIGNR_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRLQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRAW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSLLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSLLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSLLQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRLW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRAW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSLLW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRLD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRAD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSLLD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRLQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSLLQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSRLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLDQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPSLLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLDQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPALIGNR_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VPMOVSXBW256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXBW256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXBD256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXBD256_VdqWqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXBQ256_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVSXBQ256_VdqWdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXWD256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXWD256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXWQ256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXWQ256_VdqWqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVSXDQ256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXDQ256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXBW256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXBW256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXBD256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXBD256_VdqWqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXBQ256_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVZXBQ256_VdqWdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXWD256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXWD256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXWQ256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXWQ256_VdqWqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMOVZXDQ256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXDQ256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXBW256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXBW256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXBD256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXBD256_VdqWqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXBQ256_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVSXBQ256_VdqWdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXWD256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXWD256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXWQ256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXWQ256_VdqWqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVSXDQ256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXDQ256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXBW256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXBW256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXBD256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXBD256_VdqWqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXBQ256_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVZXBQ256_VdqWdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXWD256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXWD256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXWQ256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXWQ256_VdqWqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMOVZXDQ256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXDQ256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_V256_VPERM2I128_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VINSERTI128_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPERM2I128_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VINSERTI128_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V256_VEXTRACTI128_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_ISA_AVX2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V256_VBROADCASTI128_VdqMdq, &BX_CPU_C::VBROADCASTF128_VdqMdq, &BX_CPU_C::BxError, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPBROADCASTB_VdqWb, &BX_CPU_C::LOAD_Wb, &BX_CPU_C::VPBROADCASTB_VdqWb, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPBROADCASTW_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::VPBROADCASTW_VdqWw, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPBROADCASTD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_VdqWd, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPBROADCASTQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWq, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPBROADCASTB_VdqWb, &BX_CPU_C::LOAD_Wb, &BX_CPU_C::VPBROADCASTB_VdqWb, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPBROADCASTW_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::VPBROADCASTW_VdqWw, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPBROADCASTD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_VdqWd, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPBROADCASTQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWq, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VBROADCASTSS_VpsWss, &BX_CPU_C::BxError, &BX_CPU_C::VPBROADCASTD_VdqWd, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V256_VBROADCASTSD_VpdWsd, &BX_CPU_C::BxError, &BX_CPU_C::VPBROADCASTQ_VdqWq, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPBLENDD_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsHpsWpsIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPBLENDD_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsHpsWpsIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
 
 // VexW aliased
 bx_define_opcode(BX_IA_VMASKMOVD_VdqHdqMdq, &BX_CPU_C::VMASKMOVPS_VpsHpsMps, &BX_CPU_C::BxError, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
@@ -2025,90 +2026,90 @@ bx_define_opcode(BX_IA_VGATHERDQ_VdqHdq, &BX_CPU_C::VGATHERDPD_VpdHpd, &BX_CPU_C
 bx_define_opcode(BX_IA_VGATHERQD_VdqHdq, &BX_CPU_C::VGATHERQPS_VpsHps, &BX_CPU_C::BxError, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_VGATHERQQ_VdqHdq, &BX_CPU_C::VGATHERQPD_VpdHpd, &BX_CPU_C::BxError, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VPSRLVD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLVD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSRLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLVQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSLLVD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLVD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSLLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLVQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSRLVD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLVD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSRLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLVQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSLLVD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLVD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSLLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLVQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 // VexW aliased
 
-bx_define_opcode(BX_IA_V256_VPERMQ_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMQ_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPERMD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPERMPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VPERMPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMQ_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSRAVD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAVD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPERMQ_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMQ_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPERMD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPERMPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V256_VPERMPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMQ_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSRAVD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAVD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
 // AVX2
 
 
 // AVX2 FMA - VexW aliased
-bx_define_opcode(BX_IA_VFMADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VFMADD132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADD132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADD213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADD213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADD231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADD231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADD231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VFMADDSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VFMSUBADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VFMSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VFMSUB132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUB132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUB213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUB213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUB231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUB231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUB231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VFNMADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VFNMADD132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADD132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADD213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADD213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADD231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADD231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADD231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VFNMSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB132PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB213PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB213PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB231PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB231PD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VFNMSUB132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUB132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUB213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUB213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUB231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUB231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB132SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB132SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB213SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB213SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB231SS_VpsHssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUB231SD_VpdHsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NNN, BX_PREPARE_AVX)
 // AVX2 FMA - VexW aliased
 
 // BMI1
@@ -2146,126 +2147,126 @@ bx_define_opcode(BX_IA_PDEP_GqEqBq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::PDEP_GqEqBqR,
 // BMI2
 
 // FMA4 (AMD) - VexW aliased
-bx_define_opcode(BX_IA_VFMADDSUBPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSUBPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSUBPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSUBPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBADDPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBADDPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBADDPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBADDPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSS_VssHssVIbWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSS_VssHssWssVIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSD_VsdHsdVIbWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMADDSD_VsdHsdWsdVIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBSS_VssHssVIbWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBSS_VssHssWssVIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBSD_VsdHsdVIbWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFMSUBSD_VsdHsdWsdVIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADDPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADDPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADDPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADDPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADDSS_VssHssVIbWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADDSS_VssHssWssVIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADDSD_VsdHsdVIbWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMADDSD_VsdHsdWsdVIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUBPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUBPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUBPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUBPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUBSS_VssHssVIbWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUBSS_VssHssWssVIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUBSD_VsdHsdVIbWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFNMSUBSD_VsdHsdWsdVIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSUBPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSUBPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSUBPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSUBPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBADDPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBADDPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBADDPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBADDPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSS_VssHssVIbWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSS_VssHssWssVIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSD_VsdHsdVIbWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMADDSD_VsdHsdWsdVIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBSS_VssHssVIbWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBSS_VssHssWssVIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBSD_VsdHsdVIbWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFMSUBSD_VsdHsdWsdVIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADDPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADDPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADDPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADDPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADDSS_VssHssVIbWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADDSS_VssHssWssVIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADDSD_VsdHsdVIbWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMADDSD_VsdHsdWsdVIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUBPS_VpsHpsVIbWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUBPS_VpsHpsWpsVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUBPD_VpdHpdVIbWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUBPD_VpdHpdWpdVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUBSS_VssHssVIbWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUBSS_VssHssWssVIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUBSD_VsdHsdVIbWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFNMSUBSD_VsdHsdWsdVIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
 // FMA4 (AMD) - VexW aliased
 
 // XOP (AMD) - VexW aliased
-bx_define_opcode(BX_IA_VPCMOV_VdqHdqVIbWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMOV_VdqHdqWdqVIb, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPCMOV_VdqHdqWdqVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMOV_VdqHdqWdqVIb, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPPERM_VdqHdqVIbWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPPERM_VdqHdqWdqVIb, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPPERM_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPPERM_VdqHdqWdqVIb, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPERMIL2PS_VdqHdqVIbWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMIL2PS_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPERMIL2PS_VdqHdqWdqVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMIL2PS_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPERMIL2PD_VdqHdqVIbWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMIL2PD_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_RM, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPERMIL2PD_VdqHdqWdqVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMIL2PD_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPCMOV_VdqHdqVIbWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMOV_VdqHdqWdqVIb, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPCMOV_VdqHdqWdqVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMOV_VdqHdqWdqVIb, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPPERM_VdqHdqVIbWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPPERM_VdqHdqWdqVIb, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPPERM_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPPERM_VdqHdqWdqVIb, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPERMIL2PS_VdqHdqVIbWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMIL2PS_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPERMIL2PS_VdqHdqWdqVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMIL2PS_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPERMIL2PD_VdqHdqVIbWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMIL2PD_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VIB, BX_SRC_VEC_RM, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPERMIL2PD_VdqHdqWdqVIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMIL2PD_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VPSHAB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHAB_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHAW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHAW_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHAD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHAD_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHAQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHAQ_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTB_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTW_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTD_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTQ_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHLB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHLB_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHLW_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHLD_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPSHLQ_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHAB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHAB_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHAW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHAW_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHAD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHAD_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHAQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHAQ_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHAQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTB_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTW_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTD_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTQ_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHLB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHLB_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLB_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHLW_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLW_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHLD_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLD_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPSHLQ_VdqWdqHdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHLQ_VdqWdqHdq, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
 
-bx_define_opcode(BX_IA_VPMACSSWW_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSSWW_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMACSSWD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSSWD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMACSSDQL_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSSDQL_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMACSSDD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSSDD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMACSSDQH_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSSDQH_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMACSWW_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSWW_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMACSWD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSWD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMACSDQL_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSDQL_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMACSDD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSDD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMACSDQH_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSDQH_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMADCSSWD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADCSSWD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPMADCSWD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADCSWD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTB_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTB_VdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTW_VdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTD_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTD_VdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPROTQ_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTQ_VdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPCOMB_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMB_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPCOMW_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMW_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPCOMD_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMD_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPCOMQ_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMQ_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPCOMUB_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMUB_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPCOMUW_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMUW_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPCOMUD_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMUD_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPCOMUQ_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMUQ_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFRCZPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFRCZPS_VpsWpsR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFRCZPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFRCZPD_VpdWpdR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFRCZSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFRCZSS_VssWssR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VFRCZSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFRCZSD_VsdWsdR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDBW_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDBD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDBD_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDBQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDBQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDWD_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDWQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDWQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDDQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDUBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUBW_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDUBD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUBD_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDUBQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUBQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDUWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUWD_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDUWQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUWQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHADDUDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUDQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHSUBBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBBW_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHSUBWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBWD_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VPHSUBDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBDQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMACSSWW_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSSWW_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMACSSWD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSSWD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMACSSDQL_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSSDQL_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMACSSDD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSSDD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMACSSDQH_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSSDQH_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMACSWW_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSWW_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMACSWD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSWD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMACSDQL_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSDQL_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMACSDD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSDD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMACSDQH_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMACSDQH_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMADCSSWD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADCSSWD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPMADCSWD_VdqHdqWdqVIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADCSWD_VdqHdqWdqVIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTB_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTB_VdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTW_VdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTD_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTD_VdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPROTQ_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPROTQ_VdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPCOMB_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMB_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPCOMW_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMW_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPCOMD_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMD_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPCOMQ_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMQ_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPCOMUB_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMUB_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPCOMUW_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMUW_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPCOMUD_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMUD_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPCOMUQ_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCOMUQ_VdqHdqWdqIbR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFRCZPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFRCZPS_VpsWpsR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFRCZPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFRCZPD_VpdWpdR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFRCZSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFRCZSS_VssWssR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VFRCZSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFRCZSD_VsdWsdR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDBW_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDBD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDBD_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDBQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDBQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDWD_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDWQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDWQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDDQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDUBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUBW_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDUBD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUBD_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDUBQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUBQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDUWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUWD_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDUWQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUWQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHADDUDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDUDQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHSUBBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBBW_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHSUBWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBWD_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VPHSUBDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBDQ_VdqWdqR, BX_ISA_XOP, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
 // XOP (AMD) - VexW aliased
 
 // TBM (AMD)
diff --git a/bochs/cpu/load.cc b/bochs/cpu/load.cc
index 8ad3284d4..0f615bf8f 100644
--- a/bochs/cpu/load.cc
+++ b/bochs/cpu/load.cc
@@ -61,7 +61,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wb(bxInstruction_c *i)
 #if BX_CPU_LEVEL >= 6
   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
   Bit8u val_8 = read_virtual_byte(i->seg(), eaddr);
-  BX_WRITE_XMM_REG_LO_BYTE(BX_TMP_REGISTER, val_8);
+  BX_WRITE_XMM_REG_LO_BYTE(BX_VECTOR_TMP_REGISTER, val_8);
 
   return BX_CPU_CALL_METHOD(i->execute2(), (i));
 #endif
@@ -72,7 +72,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Ww(bxInstruction_c *i)
 #if BX_CPU_LEVEL >= 6
   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
   Bit16u val_16 = read_virtual_word(i->seg(), eaddr);
-  BX_WRITE_XMM_REG_LO_WORD(BX_TMP_REGISTER, val_16);
+  BX_WRITE_XMM_REG_LO_WORD(BX_VECTOR_TMP_REGISTER, val_16);
 
   return BX_CPU_CALL_METHOD(i->execute2(), (i));
 #endif
@@ -83,7 +83,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wss(bxInstruction_c *i)
 #if BX_CPU_LEVEL >= 6
   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
   Bit32u val_32 = read_virtual_dword(i->seg(), eaddr);
-  BX_WRITE_XMM_REG_LO_DWORD(BX_TMP_REGISTER, val_32);
+  BX_WRITE_XMM_REG_LO_DWORD(BX_VECTOR_TMP_REGISTER, val_32);
 
   return BX_CPU_CALL_METHOD(i->execute2(), (i));
 #endif
@@ -94,7 +94,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wsd(bxInstruction_c *i)
 #if BX_CPU_LEVEL >= 6
   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
   Bit64u val_64 = read_virtual_qword(i->seg(), eaddr);
-  BX_WRITE_XMM_REG_LO_QWORD(BX_TMP_REGISTER, val_64);
+  BX_WRITE_XMM_REG_LO_QWORD(BX_VECTOR_TMP_REGISTER, val_64);
 
   return BX_CPU_CALL_METHOD(i->execute2(), (i));
 #endif
@@ -108,7 +108,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wdq(bxInstruction_c *i)
   if (BX_CPU_THIS_PTR mxcsr.get_MM())
     read_virtual_xmmword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_TMP_REGISTER));
   else
-    read_virtual_xmmword_aligned(i->seg(), eaddr, &BX_READ_XMM_REG(BX_TMP_REGISTER));
+    read_virtual_xmmword_aligned(i->seg(), eaddr, &BX_READ_XMM_REG(BX_VECTOR_TMP_REGISTER));
 
   return BX_CPU_CALL_METHOD(i->execute2(), (i));
 #endif
@@ -118,7 +118,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOADU_Wdq(bxInstruction_c *i)
 {
 #if BX_CPU_LEVEL >= 6
   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
-  read_virtual_xmmword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_TMP_REGISTER));
+  read_virtual_xmmword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_VECTOR_TMP_REGISTER));
 
   return BX_CPU_CALL_METHOD(i->execute2(), (i));
 #endif