Fixed bug [ 912496 ] IDIV can cause simulator divide error
This commit is contained in:
Stanislav Shwartsman
parent
91ac899439
commit
729e0abd2a
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: mult16.cc,v 1.13 2004-08-14 19:34:02 sshwarts Exp $
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// $Id: mult16.cc,v 1.14 2004-08-18 19:27:52 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -35,7 +35,6 @@ BX_CPU_C::MUL_AXEw(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16, product_16h, product_16l;
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Bit32u product_32;
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bx_bool temp_flag;
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op1_16 = AX;
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@ -49,12 +48,10 @@ BX_CPU_C::MUL_AXEw(bxInstruction_c *i)
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}
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product_32 = ((Bit32u) op1_16) * ((Bit32u) op2_16);
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product_16l = (product_32 & 0xFFFF);
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product_16h = product_32 >> 16;
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/* now write product back to destination */
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AX = product_16l;
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DX = product_16h;
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@ -62,11 +59,10 @@ BX_CPU_C::MUL_AXEw(bxInstruction_c *i)
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* MUL affects the following flags: C,O
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*/
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temp_flag = (product_16h != 0);
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bx_bool temp_flag = (product_16h != 0);
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SET_FLAGS_OxxxxC(temp_flag, temp_flag);
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}
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void
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BX_CPU_C::IMUL_AXEw(bxInstruction_c *i)
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{
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@ -86,12 +82,10 @@ BX_CPU_C::IMUL_AXEw(bxInstruction_c *i)
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}
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product_32 = ((Bit32s) op1_16) * ((Bit32s) op2_16);
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product_16l = (product_32 & 0xFFFF);
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product_16h = product_32 >> 16;
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/* now write product back to destination */
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AX = product_16l;
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DX = product_16h;
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@ -112,7 +106,6 @@ BX_CPU_C::IMUL_AXEw(bxInstruction_c *i)
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}
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}
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void
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BX_CPU_C::DIV_AXEw(bxInstruction_c *i)
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{
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@ -130,16 +123,15 @@ BX_CPU_C::DIV_AXEw(bxInstruction_c *i)
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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if (op2_16 == 0) {
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if (op2_16 == 0)
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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quotient_32 = op1_32 / op2_16;
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remainder_16 = op1_32 % op2_16;
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quotient_16l = quotient_32 & 0xFFFF;
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if (quotient_32 != quotient_16l) {
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if (quotient_32 != quotient_16l)
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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/* set EFLAGS:
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* DIV affects the following flags: O,S,Z,A,P,C are undefined
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@ -172,16 +164,19 @@ BX_CPU_C::IDIV_AXEw(bxInstruction_c *i)
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read_virtual_word(i->seg(), RMAddr(i), (Bit16u *) &op2_16);
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}
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if (op2_16 == 0) {
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if (op2_16 == 0)
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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/* check MIN_INT divided by -1 case */
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if (op1_32 == BX_MIN_BIT32S && op2_16 == -1)
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exception(BX_DE_EXCEPTION, 0, 0);
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quotient_32 = op1_32 / op2_16;
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remainder_16 = op1_32 % op2_16;
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quotient_16l = quotient_32 & 0xFFFF;
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if (quotient_32 != quotient_16l) {
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if (quotient_32 != quotient_16l)
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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/* set EFLAGS:
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* IDIV affects the following flags: O,S,Z,A,P,C are undefined
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@ -196,7 +191,6 @@ BX_CPU_C::IDIV_AXEw(bxInstruction_c *i)
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DX = remainder_16;
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}
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void
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BX_CPU_C::IMUL_GwEwIw(bxInstruction_c *i)
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{
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: mult32.cc,v 1.13 2004-08-13 20:00:03 sshwarts Exp $
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// $Id: mult32.cc,v 1.14 2004-08-18 19:27:52 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -42,7 +42,6 @@ BX_CPU_C::MUL_EAXEd(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, product_32h, product_32l;
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Bit64u product_64;
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bx_bool temp_flag;
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op1_32 = EAX;
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@ -56,12 +55,10 @@ BX_CPU_C::MUL_EAXEd(bxInstruction_c *i)
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}
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product_64 = ((Bit64u) op1_32) * ((Bit64u) op2_32);
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product_32l = (Bit32u) (product_64 & 0xFFFFFFFF);
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product_32h = (Bit32u) (product_64 >> 32);
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/* now write product back to destination */
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RAX = product_32l;
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RDX = product_32h;
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@ -69,11 +66,10 @@ BX_CPU_C::MUL_EAXEd(bxInstruction_c *i)
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* MUL affects the following flags: C,O
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*/
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temp_flag = (product_32h != 0);
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bx_bool temp_flag = (product_32h != 0);
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SET_FLAGS_OxxxxC(temp_flag, temp_flag);
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}
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void
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BX_CPU_C::IMUL_EAXEd(bxInstruction_c *i)
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{
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@ -93,12 +89,10 @@ BX_CPU_C::IMUL_EAXEd(bxInstruction_c *i)
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}
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product_64 = ((Bit64s) op1_32) * ((Bit64s) op2_32);
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product_32l = (Bit32u) (product_64 & 0xFFFFFFFF);
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product_32h = (Bit32u) (product_64 >> 32);
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/* now write product back to destination */
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RAX = product_32l;
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RDX = product_32h;
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@ -119,7 +113,6 @@ BX_CPU_C::IMUL_EAXEd(bxInstruction_c *i)
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}
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}
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void
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BX_CPU_C::DIV_EAXEd(bxInstruction_c *i)
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{
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@ -159,7 +152,6 @@ BX_CPU_C::DIV_EAXEd(bxInstruction_c *i)
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RDX = remainder_32;
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}
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void
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BX_CPU_C::IDIV_EAXEd(bxInstruction_c *i)
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{
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@ -177,9 +169,12 @@ BX_CPU_C::IDIV_EAXEd(bxInstruction_c *i)
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read_virtual_dword(i->seg(), RMAddr(i), (Bit32u *) &op2_32);
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}
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if (op2_32 == 0) {
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if (op2_32 == 0)
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exception(BX_DE_EXCEPTION, 0, 0);
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/* check MIN_INT divided by -1 case */
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if (op1_64 == BX_MIN_BIT64S && op2_32 == -1)
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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quotient_64 = op1_64 / op2_32;
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remainder_32 = (Bit32s) (op1_64 % op2_32);
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@ -199,7 +194,6 @@ BX_CPU_C::IDIV_EAXEd(bxInstruction_c *i)
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RDX = remainder_32;
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}
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void
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BX_CPU_C::IMUL_GdEdId(bxInstruction_c *i)
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{
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: mult64.cc,v 1.9 2004-04-07 19:46:13 sshwarts Exp $
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// $Id: mult64.cc,v 1.10 2004-08-18 19:27:52 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -25,7 +25,6 @@
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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@ -110,12 +109,9 @@ void long_shr(Bit128u *a)
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unsigned long_sub(Bit128u *a,Bit128u *b)
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{
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Bit64u t;
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int c;
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t = a->lo;
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Bit64u t = a->lo;
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a->lo -= b->lo;
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c = (a->lo > t);
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int c = (a->lo > t);
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t = a -> hi;
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a->hi -= b->hi + c;
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return(a->hi > t);
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@ -214,7 +210,6 @@ BX_CPU_C::MUL_RAXEq(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64;
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Bit128u product_128;
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bx_bool temp_flag;
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op1_64 = RAX;
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@ -241,7 +236,7 @@ BX_CPU_C::MUL_RAXEq(bxInstruction_c *i)
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* MUL affects the following flags: C,O
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*/
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temp_flag = (product_128.hi != 0);
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bx_bool temp_flag = (product_128.hi != 0);
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SET_FLAGS_OxxxxC(temp_flag, temp_flag);
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}
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@ -289,7 +284,6 @@ BX_CPU_C::IMUL_RAXEq(bxInstruction_c *i)
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}
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}
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void
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BX_CPU_C::DIV_RAXEq(bxInstruction_c *i)
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{
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@ -330,7 +324,6 @@ BX_CPU_C::DIV_RAXEq(bxInstruction_c *i)
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RDX = remainder_64;
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}
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void
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BX_CPU_C::IDIV_RAXEq(bxInstruction_c *i)
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{
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@ -352,6 +345,13 @@ BX_CPU_C::IDIV_RAXEq(bxInstruction_c *i)
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if (op2_64 == 0)
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exception(BX_DE_EXCEPTION, 0, 0);
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/* check MIN_INT divided by -1 case */
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if (op2_64 == -1)
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{
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if ((op1_128.ho == BX_CONT64(0x8000000000000000)) && (!op1_128.lo))
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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// quotient_128 = op1_128 / op2_64;
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// remainder_64 = (Bit64s) (op1_128 % op2_64);
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// quotient_64l = (Bit64s) (quotient_128 & 0xFFFFFFFFFFFFFFFF);
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@ -371,7 +371,6 @@ BX_CPU_C::IDIV_RAXEq(bxInstruction_c *i)
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RDX = remainder_64;
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}
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void
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BX_CPU_C::IMUL_GqEqId(bxInstruction_c *i)
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{
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: mult8.cc,v 1.13 2004-08-13 20:00:03 sshwarts Exp $
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// $Id: mult8.cc,v 1.14 2004-08-18 19:27:52 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -34,8 +34,6 @@
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BX_CPU_C::MUL_ALEb(bxInstruction_c *i)
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{
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Bit8u op2, op1;
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Bit16u product_16;
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bx_bool temp_flag;
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op1 = AL;
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@ -48,26 +46,23 @@ BX_CPU_C::MUL_ALEb(bxInstruction_c *i)
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read_virtual_byte(i->seg(), RMAddr(i), &op2);
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}
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product_16 = op1 * op2;
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Bit16u product_16 = op1 * op2;
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/* set EFLAGS:
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* MUL affects the following flags: C,O
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*/
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temp_flag = ((product_16 & 0xFF00) != 0);
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bx_bool temp_flag = ((product_16 & 0xFF00) != 0);
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SET_FLAGS_OxxxxC(temp_flag, temp_flag);
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/* now write product back to destination */
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AX = product_16;
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}
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void
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BX_CPU_C::IMUL_ALEb(bxInstruction_c *i)
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{
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Bit8s op2, op1;
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Bit16s product_16;
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Bit16u upper_bits;
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op1 = AL;
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@ -80,7 +75,7 @@ BX_CPU_C::IMUL_ALEb(bxInstruction_c *i)
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read_virtual_byte(i->seg(), RMAddr(i), (Bit8u *) &op2);
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}
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product_16 = op1 * op2;
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Bit16s product_16 = op1 * op2;
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/* now write product back to destination */
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AX = product_16;
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@ -90,7 +85,7 @@ BX_CPU_C::IMUL_ALEb(bxInstruction_c *i)
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* IMUL r/m8: condition for clearing CF & OF:
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* AL = sign-extend of AL to 16 bits
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*/
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upper_bits = AX & 0xff80;
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Bit16u upper_bits = AX & 0xff80;
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if (upper_bits==0xff80 || upper_bits==0x0000) {
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SET_FLAGS_OxxxxC(0, 0);
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}
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@ -99,7 +94,6 @@ BX_CPU_C::IMUL_ALEb(bxInstruction_c *i)
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}
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}
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void
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BX_CPU_C::DIV_ALEb(bxInstruction_c *i)
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{
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@ -143,7 +137,6 @@ BX_CPU_C::DIV_ALEb(bxInstruction_c *i)
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AH = remainder_8;
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}
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void
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BX_CPU_C::IDIV_ALEb(bxInstruction_c *i)
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{
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@ -161,22 +154,19 @@ BX_CPU_C::IDIV_ALEb(bxInstruction_c *i)
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read_virtual_byte(i->seg(), RMAddr(i), (Bit8u *) &op2);
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}
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if (op2 == 0) {
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if (op2 == 0)
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exception(BX_DE_EXCEPTION, 0, 0);
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/* check MIN_INT divided by -1 case */
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if (op1 == BX_MIN_BIT16S && op2 == -1)
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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quotient_16 = op1 / op2;
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remainder_8 = op1 % op2;
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quotient_8l = quotient_16 & 0xFF;
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if (quotient_16 != quotient_8l) {
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BX_INFO(("quotient_16: %04x, remainder_8: %02x, quotient_8l: %02x",
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(unsigned) quotient_16, (unsigned) remainder_8, (unsigned) quotient_8l));
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AL = quotient_8l;
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AH = remainder_8;
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BX_INFO(("AH: %02x, AL: %02x", (unsigned) AH, (unsigned) AL));
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if (quotient_16 != quotient_8l)
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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/* set EFLAGS:
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* DIV affects the following flags: O,S,Z,A,P,C are undefined
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