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Call #UD exception directly instead of UndefinedOpcode function - for future use

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This commit is contained in:
Stanislav Shwartsman 2008-07-13 15:35:10 +00:00
parent 85686db212
commit 709d74728d
25 changed files with 503 additions and 503 deletions
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14
bochs/cpu/aes.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: aes.cc,v 1.1 2008-05-30 20:37:52 sshwarts Exp $
// $Id: aes.cc,v 1.2 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008 Stanislav Shwartsman
@ -312,7 +312,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESIMC_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("AESIMC_VdqWdq: required AES support, use --enable-aes option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -344,7 +344,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENC_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("AESENC_VdqWdq: required AES support, use --enable-aes option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -375,7 +375,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENCLAST_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("AESENCLAST_VdqWdq: required AES support, use --enable-aes option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -407,7 +407,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDEC_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("AESDEC_VdqWdq: required AES support, use --enable-aes option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -438,7 +438,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDECLAST_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("AESDECLAST_VdqWdq: required AES support, use --enable-aes option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -470,6 +470,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESKEYGENASSIST_VdqWdqIb(bxInstruction_c *
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("AESKEYGENASSIST_VdqWdqIb: required AES support, use --enable-aes option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

10
bochs/cpu/arith16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith16.cc,v 1.68 2008-07-13 09:59:57 sshwarts Exp $
// $Id: arith16.cc,v 1.69 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -375,7 +375,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EwGwM(bxInstruction_c *i)
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
#else
BX_INFO(("XADD_EwGw: not supported on < 80486"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -404,7 +404,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EwGwR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
#else
BX_INFO(("XADD_EwGw: not supported on < 80486"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -572,7 +572,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EwGwM(bxInstruction_c *i)
}
#else
BX_INFO(("CMPXCHG_EwGw: not supported for cpu-level <= 3"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -596,6 +596,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EwGwR(bxInstruction_c *i)
}
#else
BX_INFO(("CMPXCHG_EwGw: not supported for cpu-level <= 3"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

16
bochs/cpu/arith32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith32.cc,v 1.79 2008-07-13 09:59:57 sshwarts Exp $
// $Id: arith32.cc,v 1.80 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -384,13 +384,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CDQ(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_XBTS(bxInstruction_c *i)
{
BX_INFO(("CMPXCHG_XBTS: Generate #UD exception"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_IBTS(bxInstruction_c *i)
{
BX_INFO(("CMPXCHG_IBTS: Generate #UD exception"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdM(bxInstruction_c *i)
@ -417,7 +417,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdM(bxInstruction_c *i)
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
#else
BX_INFO (("XADD_EdGd not supported for cpulevel <= 3"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -446,7 +446,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
#else
BX_INFO (("XADD_EdGd not supported for cpulevel <= 3"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -623,7 +623,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdM(bxInstruction_c *i)
}
#else
BX_INFO(("CMPXCHG_EdGd: not supported for cpulevel <= 3"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -647,7 +647,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdR(bxInstruction_c *i)
}
#else
BX_INFO(("CMPXCHG_EdGd: not supported for cpulevel <= 3"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -677,6 +677,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
#else
BX_INFO(("CMPXCHG8B: not supported for cpulevel <= 4"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

10
bochs/cpu/arith8.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith8.cc,v 1.57 2008-07-13 09:59:57 sshwarts Exp $
// $Id: arith8.cc,v 1.58 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -344,7 +344,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EbGbM(bxInstruction_c *i)
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
#else
BX_INFO(("XADD_EbGb: not supported on < 80486"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -373,7 +373,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EbGbR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
#else
BX_INFO(("XADD_EbGb: not supported on < 80486"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -562,7 +562,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EbGbM(bxInstruction_c *i)
#else
BX_INFO(("CMPXCHG_EbGb: not supported for cpulevel <= 3"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -587,6 +587,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EbGbR(bxInstruction_c *i)
#else
BX_INFO(("CMPXCHG_EbGb: not supported for cpulevel <= 3"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

8
bochs/cpu/bit.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit.cc,v 1.56 2008-05-10 18:10:52 sshwarts Exp $
// $Id: bit.cc,v 1.57 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -262,7 +262,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->opcodeReg(), val32);
#else
BX_INFO(("BSWAP_ERX: required CPU >= 4, use --enable-cpu-level=4 option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -359,7 +359,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEb(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
#else
BX_INFO(("CRC32_GdEb: required SSE4_2 support, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -435,7 +435,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEv(bxInstruction_c *i)
#else
BX_INFO(("CRC32_GdEv: required SSE4_2 support, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

4
bochs/cpu/bit16.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit16.cc,v 1.10 2008-07-13 10:44:34 sshwarts Exp $
// $Id: bit16.cc,v 1.11 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -387,7 +387,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GwEw(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
#else
BX_INFO(("POPCNT_GwEw: required POPCNT support, use --enable-popcnt option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

4
bochs/cpu/bit32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit32.cc,v 1.9 2008-07-13 10:44:34 sshwarts Exp $
// $Id: bit32.cc,v 1.10 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -392,7 +392,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GdEd(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
#else
BX_INFO(("POPCNT_GdEd: required POPCNT support, use --enable-popcnt option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

4
bochs/cpu/bit64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit64.cc,v 1.12 2008-05-10 18:10:52 sshwarts Exp $
// $Id: bit64.cc,v 1.13 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -372,7 +372,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GqEq(bxInstruction_c *i)
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
#else
BX_INFO(("POPCNT_GqEq: required POPCNT support, use --enable-popcnt option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

4
bochs/cpu/cpuid.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpuid.cc,v 1.69 2008-05-30 20:35:07 sshwarts Exp $
// $Id: cpuid.cc,v 1.70 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007 Stanislav Shwartsman
@ -321,7 +321,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CPUID(bxInstruction_c *i)
RDX = 0;
#else
BX_INFO(("CPUID: not available on < 486"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

72
bochs/cpu/data_xfer16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer16.cc,v 1.59 2008-07-13 10:06:07 sshwarts Exp $
// $Id: data_xfer16.cc,v 1.60 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -67,7 +67,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EwSwR(bxInstruction_c *i)
/* Illegal to use nonexisting segments */
if (i->nnn() >= 6) {
BX_INFO(("MOV_EwSw: using of nonexisting segment register %d", i->nnn()));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
Bit16u seg_reg = BX_CPU_THIS_PTR sregs[i->nnn()].selector.value;
@ -85,7 +85,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EwSwM(bxInstruction_c *i)
/* Illegal to use nonexisting segments */
if (i->nnn() >= 6) {
BX_INFO(("MOV_EwSw: using of nonexisting segment register %d", i->nnn()));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -101,7 +101,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_SwEw(bxInstruction_c *i)
/* Attempt to load CS or nonexisting segment register */
if (i->nnn() >= 6 || i->nnn() == BX_SEG_REG_CS) {
BX_INFO(("MOV_EwSw: can't use this segment register %d", i->nnn()));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
if (i->modC0()) {
@ -235,7 +235,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVO_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -246,7 +246,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVO_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -261,7 +261,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVNO_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -272,7 +272,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVNO_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -287,7 +287,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVB_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -298,7 +298,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVB_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -313,7 +313,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVNB_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -324,7 +324,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVNB_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -339,7 +339,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVZ_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -350,7 +350,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVZ_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -365,7 +365,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVNZ_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -376,7 +376,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVNZ_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -391,7 +391,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVBE_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -402,7 +402,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVBE_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -417,7 +417,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVNBE_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -428,7 +428,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVNBE_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -443,7 +443,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVS_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -454,7 +454,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVS_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -469,7 +469,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVNS_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -480,7 +480,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVNS_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -495,7 +495,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVP_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -506,7 +506,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVP_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -521,7 +521,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVNP_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -532,7 +532,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVNP_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -547,7 +547,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVL_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -558,7 +558,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVL_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -573,7 +573,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVNL_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -584,7 +584,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVNL_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -599,7 +599,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVLE_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -610,7 +610,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVLE_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -625,7 +625,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNLE_GwEwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), op2_16);
#else
BX_INFO(("CMOVNLE_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -636,6 +636,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNLE_GwEwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
#else
BX_INFO(("CMOVNLE_GwEw: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

66
bochs/cpu/data_xfer32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer32.cc,v 1.56 2008-07-13 10:06:07 sshwarts Exp $
// $Id: data_xfer32.cc,v 1.57 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -207,7 +207,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVO_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -220,7 +220,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVO_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -237,7 +237,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNO_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -250,7 +250,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNO_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -267,7 +267,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVB_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -280,7 +280,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVB_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -297,7 +297,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNB_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -310,7 +310,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNB_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -327,7 +327,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVZ_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -340,7 +340,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVZ_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -357,7 +357,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNZ_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -370,7 +370,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNZ_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -387,7 +387,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVBE_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -400,7 +400,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVBE_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -417,7 +417,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNBE_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -430,7 +430,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNBE_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -447,7 +447,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVS_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -460,7 +460,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVS_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -477,7 +477,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNS_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -490,7 +490,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNS_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -507,7 +507,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVP_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -520,7 +520,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVP_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -537,7 +537,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNP_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -550,7 +550,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNP_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -567,7 +567,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVL_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -580,7 +580,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVL_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -597,7 +597,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNL_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -610,7 +610,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNL_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -627,7 +627,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVLE_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -640,7 +640,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVLE_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -657,7 +657,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNLE_GdEdM(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNLE_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -670,6 +670,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNLE_GdEdR(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOVNLE_GdEd: --enable-cpu-level=6 required"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

4
bochs/cpu/fetchdecode.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.195 2008-07-13 09:59:57 sshwarts Exp $
// $Id: fetchdecode.cc,v 1.196 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -2951,5 +2951,5 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BxError(bxInstruction_c *i)
BX_DEBUG(("modrm was 0x%02x, nnn was %u, rm was %u", i->modrm(), i->nnn(), i->rm()));
BX_DEBUG(("WARNING: Encountered an unknown instruction (signalling #UD)"));
BX_CPU_THIS_PTR UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}

182
bochs/cpu/mmx.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: mmx.cc,v 1.79 2008-05-10 18:10:52 sshwarts Exp $
// $Id: mmx.cc,v 1.80 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002 Stanislav Shwartsman
@ -91,7 +91,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PSHUFB_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -121,7 +121,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHADDW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -149,7 +149,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHADDD_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -180,7 +180,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHADDSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -214,7 +214,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMADDUBSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PMADDUBSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -245,7 +245,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -275,7 +275,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -303,7 +303,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBD_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -333,7 +333,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGNB_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -363,7 +363,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGNW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -395,7 +395,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGND_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGND_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -431,7 +431,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHRSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PMULHRSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -465,7 +465,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op);
#else
BX_INFO(("PABSB_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -495,7 +495,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op);
#else
BX_INFO(("PABSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -523,7 +523,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op);
#else
BX_INFO(("PABSD_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -560,7 +560,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_PqQqIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PALIGNR_PqQqIb: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -597,7 +597,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLBW_PqQd(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PUNPCKLBW_PqQd: required MMX, configure --enable-mmx"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -628,7 +628,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLWD_PqQd(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PUNPCKLWD_PqQd: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -656,7 +656,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLDQ_PqQd(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PUNPCKLDQ_PqQd: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -691,7 +691,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKSSWB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PACKSSWB_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -726,7 +726,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPGTB_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -757,7 +757,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPGTW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -786,7 +786,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPGTD_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -821,7 +821,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKUSWB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PACKUSWB_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -856,7 +856,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHBW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PUNPCKHBW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -887,7 +887,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHWD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PUNPCKHWD_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -916,7 +916,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHDQ_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PUNPCKHDQ_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -947,7 +947,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKSSDW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PACKSSDW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -975,7 +975,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_PqEd(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op);
#else
BX_INFO(("MOVD_PqEd: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1026,7 +1026,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op);
#else
BX_INFO(("MOVQ_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1058,7 +1058,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFW_PqQqIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PSHUFW_PqQqIb: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1093,7 +1093,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPEQB_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1124,7 +1124,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPEQW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1153,7 +1153,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPEQD_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1165,7 +1165,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::EMMS(bxInstruction_c *i)
FPU_TAG_WORD = 0xffff;
#else
BX_INFO(("EMMS: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1189,7 +1189,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdPd(bxInstruction_c *i)
#else
BX_INFO(("MOVD_EdPd: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1234,7 +1234,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_QqPq(bxInstruction_c *i)
}
#else
BX_INFO(("MOVQ_QqPq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1263,7 +1263,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRW_PqEwIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PINSRW_PqEdIb: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1279,7 +1279,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_GdPqIb(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->nnn(), result);
#else
BX_INFO(("PEXTRW_GdPqIb: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1316,7 +1316,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSRLW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1351,7 +1351,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSRLD_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1384,7 +1384,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLQ_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSRLQ_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1412,7 +1412,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDQ_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PADDQ_PqQq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1448,7 +1448,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULLW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PMULLW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1475,7 +1475,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVMSKB_GdPRq(bxInstruction_c *i)
#else
BX_INFO(("PMOVMSKB_GdPRq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1512,7 +1512,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBUSB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PSUBUSB_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1545,7 +1545,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBUSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PSUBUSW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1580,7 +1580,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINUB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PMINUB_PqQq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1608,7 +1608,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAND_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PAND_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1643,7 +1643,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDUSB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PADDUSB_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1674,7 +1674,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDUSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PADDUSW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1709,7 +1709,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXUB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PMAXUB_PqQq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1737,7 +1737,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PANDN_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PANDN_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1772,7 +1772,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAVGB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PAVGB_PqQq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1820,7 +1820,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PSRAW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1865,7 +1865,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PSRAD_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1896,7 +1896,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAVGW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PAVGW_PqQq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1932,7 +1932,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHUW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PMULHUW_PqQq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1968,7 +1968,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PMULHW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1982,7 +1982,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTQ_MqPq(bxInstruction_c *i)
write_virtual_qword(i->seg(), RMAddr(i), MMXUQ(reg));
#else
BX_INFO(("MOVNTQ_MqPq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2017,7 +2017,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBSB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PSUBSB_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2048,7 +2048,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PSUBSW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2079,7 +2079,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PMINSW_PqQq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2107,7 +2107,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::POR_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("POR_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2142,7 +2142,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDSB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PADDSB_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2173,7 +2173,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PADDSW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2204,7 +2204,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXSW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PMAXSW_PqQq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2232,7 +2232,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PXOR_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PXOR_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2269,7 +2269,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSLLW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2304,7 +2304,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSLLD_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2337,7 +2337,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLQ_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSLLQ_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2365,7 +2365,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULUDQ_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PMULUDQ_PqQq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2405,7 +2405,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMADDWD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PMADDWD_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2443,7 +2443,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSADBW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSADBW_PqQq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2487,7 +2487,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MASKMOVQ_PqPRq(bxInstruction_c *i)
write_RMW_virtual_qword(MMXUQ(tmp));
#else
BX_INFO(("MASKMOVQ_PqPRq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2522,7 +2522,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSUBB_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2553,7 +2553,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSUBW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2582,7 +2582,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSUBD_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2610,7 +2610,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBQ_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSUBQ_PqQq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2645,7 +2645,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PADDB_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2676,7 +2676,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PADDW_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2705,7 +2705,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PADDD_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2731,7 +2731,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLW_PqIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->rm(), op);
#else
BX_INFO(("PSRLW_PqIb: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2768,7 +2768,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAW_PqIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->rm(), result);
#else
BX_INFO(("PSRAW_PqIb: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2794,7 +2794,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLW_PqIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->rm(), op);
#else
BX_INFO(("PSLLW_PqIb: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2818,7 +2818,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLD_PqIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->rm(), op);
#else
BX_INFO(("PSRLD_PqIb: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2852,7 +2852,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAD_PqIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->rm(), result);
#else
BX_INFO(("PSRAD_PqIb: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2876,7 +2876,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLD_PqIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->rm(), op);
#else
BX_INFO(("PSLLD_PqIb: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2900,7 +2900,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLQ_PqIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->rm(), op);
#else
BX_INFO(("PSRLQ_PqIb: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2924,6 +2924,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLQ_PqIb(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->rm(), op);
#else
BX_INFO(("PSLLQ_PqIb: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

4
bochs/cpu/paging.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: paging.cc,v 1.142 2008-06-25 02:28:31 sshwarts Exp $
// $Id: paging.cc,v 1.143 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -576,7 +576,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::INVLPG(bxInstruction_c* i)
TLB_invlpg(laddr);
#else
BX_INFO(("INVLPG: required i486, use --enable-cpu=4 option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

52
bochs/cpu/proc_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.247 2008-07-13 10:44:34 sshwarts Exp $
// $Id: proc_ctrl.cc,v 1.248 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -156,7 +156,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::INVD(bxInstruction_c *i)
#else
BX_INFO(("INVD: required 486 support, use --enable-cpu-level=4 option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -179,7 +179,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::WBINVD(bxInstruction_c *i)
#else
BX_INFO(("WBINVD: required 486 support, use --enable-cpu-level=4 option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -219,7 +219,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CLFLUSH(bxInstruction_c *i)
#else
BX_INFO(("CLFLUSH: not supported, enable with SSE2"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -230,7 +230,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
if (BX_CPU_THIS_PTR cr4.get_DE()) {
if ((i->nnn() & 0xE) == 4) {
BX_ERROR(("MOV_DdRd: access to DR4/DR5 causes #UD"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
}
#endif
@ -335,7 +335,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
default:
BX_ERROR(("MOV_DdRd: #UD - register index out of range"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
}
@ -347,7 +347,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
if (BX_CPU_THIS_PTR cr4.get_DE()) {
if ((i->nnn() & 0xE) == 4) {
BX_ERROR(("MOV_RdDd: access to DR4/DR5 causes #UD"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
}
#endif
@ -395,7 +395,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
default:
BX_ERROR(("MOV_RdDd: #UD - register index out of range"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
BX_WRITE_32BIT_REGZ(i->rm(), val_32);
@ -413,7 +413,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
if (BX_CPU_THIS_PTR cr4.get_DE()) {
if ((i->nnn() & 0xE) == 4) {
BX_ERROR(("MOV_DqRq: access to DR4/DR5 causes #UD"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
}
@ -494,7 +494,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
default:
BX_ERROR(("MOV_DqRq: #UD - register index out of range"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
}
@ -505,7 +505,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
if (BX_CPU_THIS_PTR cr4.get_DE()) {
if ((i->nnn() & 0xE) == 4) {
BX_ERROR(("MOV_RqDq: access to DR4/DR5 causes #UD"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
}
@ -553,7 +553,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
default:
BX_ERROR(("MOV_RqDq: #UD - register index out of range"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
BX_WRITE_64BIT_REG(i->rm(), val_64);
@ -607,7 +607,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
#endif
default:
BX_ERROR(("MOV_CdRd: #UD - control register %d index out of range", i->nnn()));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
}
@ -653,7 +653,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCd(bxInstruction_c *i)
break;
default:
BX_ERROR(("MOV_RdCd: #UD - control register %d index out of range", i->nnn()));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
BX_WRITE_32BIT_REGZ(i->rm(), val_32);
@ -723,7 +723,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
#endif
default:
BX_ERROR(("MOV_CqRq: #UD - control register %d index out of range", i->nnn()));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
}
@ -780,7 +780,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCq(bxInstruction_c *i)
#endif
default:
BX_ERROR(("MOV_RqCq: #UD - control register %d index out of range", i->nnn()));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
BX_WRITE_64BIT_REG(i->rm(), val_64);
@ -847,7 +847,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_TdRd(bxInstruction_c *i)
#else
// Pentium+ does not have TRx. They were redesigned using the MSRs.
BX_INFO(("MOV_TdRd: causes #UD"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -858,7 +858,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdTd(bxInstruction_c *i)
#else
// Pentium+ does not have TRx. They were redesigned using the MSRs.
BX_INFO(("MOV_RdTd: causes #UD"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1390,7 +1390,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPMC(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0, 0);
}
#else
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1426,7 +1426,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDTSC(bxInstruction_c *i)
}
#else
BX_INFO(("RDTSC: Pentium CPU required, use --enable-cpu=5"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1630,7 +1630,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDMSR(bxInstruction_c *i)
}
#else
BX_INFO(("RDMSR: Pentium CPU required, use --enable-cpu-level=5"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1863,7 +1863,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::WRMSR(bxInstruction_c *i)
}
#else
BX_INFO(("WRMSR: Pentium CPU required, use --enable-cpu-level=5"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1940,7 +1940,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MONITOR(bxInstruction_c *i)
#else
BX_INFO(("MONITOR: use --enable-monitor-mwait to enable MONITOR/MWAIT support"));
UndefinedOpcode (i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1994,7 +1994,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MWAIT(bxInstruction_c *i)
#else
BX_INFO(("MWAIT: use --enable-monitor-mwait to enable MONITOR/MWAIT support"));
UndefinedOpcode (i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2093,7 +2093,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSENTER(bxInstruction_c *i)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
#else
BX_INFO(("SYSENTER: use --enable-sep to enable SYSENTER/SYSEXIT support"));
UndefinedOpcode (i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2204,7 +2204,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSEXIT(bxInstruction_c *i)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
#else
BX_INFO(("SYSEXIT: use --enable-sep to enable SYSENTER/SYSEXIT support"));
UndefinedOpcode (i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

20
bochs/cpu/protect_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: protect_ctrl.cc,v 1.88 2008-06-12 19:14:39 sshwarts Exp $
// $Id: protect_ctrl.cc,v 1.89 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -36,7 +36,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ARPL_EwGw(bxInstruction_c *i)
if (real_mode() || v8086_mode()) {
BX_DEBUG(("ARPL: not recognized in real or virtual-8086 mode"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
/* op1_16 is a register or memory reference */
@ -77,7 +77,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LAR_GvEw(bxInstruction_c *i)
if (real_mode() || v8086_mode()) {
BX_ERROR(("LAR: not recognized in real or virtual-8086 mode"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
if (i->modC0()) {
@ -185,7 +185,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LSL_GvEw(bxInstruction_c *i)
if (real_mode() || v8086_mode()) {
BX_ERROR(("LSL: not recognized in real or virtual-8086 mode"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
if (i->modC0()) {
@ -267,7 +267,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SLDT_Ew(bxInstruction_c *i)
{
if (real_mode() || v8086_mode()) {
BX_ERROR(("SLDT: not recognized in real or virtual-8086 mode"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
Bit16u val16 = BX_CPU_THIS_PTR ldtr.selector.value;
@ -290,7 +290,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::STR_Ew(bxInstruction_c *i)
{
if (real_mode() || v8086_mode()) {
BX_ERROR(("STR: not recognized in real or virtual-8086 mode"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
Bit16u val16 = BX_CPU_THIS_PTR tr.selector.value;
@ -322,7 +322,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LLDT_Ew(bxInstruction_c *i)
if (real_mode() || v8086_mode()) {
BX_ERROR(("LLDT: not recognized in real or virtual-8086 mode"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
if (CPL != 0) {
@ -411,7 +411,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LTR_Ew(bxInstruction_c *i)
if (real_mode() || v8086_mode()) {
BX_ERROR(("LTR: not recognized in real or virtual-8086 mode"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
if (CPL != 0) {
@ -514,7 +514,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VERR_Ew(bxInstruction_c *i)
if (real_mode() || v8086_mode()) {
BX_ERROR(("VERR: not recognized in real or virtual-8086 mode"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
if (i->modC0()) {
@ -603,7 +603,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VERW_Ew(bxInstruction_c *i)
if (real_mode() || v8086_mode()) {
BX_ERROR(("VERW: not recognized in real or virtual-8086 mode"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
if (i->modC0()) {

4
bochs/cpu/smm.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: smm.cc,v 1.40 2008-05-26 21:46:39 sshwarts Exp $
// $Id: smm.cc,v 1.41 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006 Stanislav Shwartsman
@ -69,7 +69,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSM(bxInstruction_c *i)
/* If we are not in System Management Mode, then #UD should be generated */
if (! BX_CPU_THIS_PTR smm_mode()) {
BX_INFO(("RSM not in System Management Mode !"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
invalidate_prefetch_q();

238
bochs/cpu/sse.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse.cc,v 1.59 2008-05-10 22:20:05 sshwarts Exp $
// $Id: sse.cc,v 1.60 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -63,7 +63,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PSHUFB_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -98,7 +98,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHADDW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -128,7 +128,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHADDD_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -164,7 +164,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHADDSW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -198,7 +198,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMADDUBSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMADDUBSW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -234,7 +234,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBSW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -269,7 +269,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -299,7 +299,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBD_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -329,7 +329,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGNB_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -359,7 +359,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGNW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -389,7 +389,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGND_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGND_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -424,7 +424,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHRSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMULHRSW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -466,7 +466,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("PABSB_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -500,7 +500,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("PABSW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -530,7 +530,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("PABSD_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -560,7 +560,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PBLENDVB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PBLENDVB_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -592,7 +592,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BLENDVPS_VpsWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("BLENDVPS_VpsWps: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -622,7 +622,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BLENDVPD_VpdWpd(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("BLENDVPD_VpdWpd: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -655,7 +655,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PTEST_VdqWdq(bxInstruction_c *i)
#else
BX_INFO(("PTEST_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -684,7 +684,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULDQ_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMULDQ_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -716,7 +716,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQQ_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPEQQ_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -751,7 +751,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKUSDW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PACKUSDW_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -783,7 +783,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTQ_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPGTQ_VdqWdq: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -813,7 +813,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINSB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMINSB_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -844,7 +844,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINSD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMINSD_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -879,7 +879,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINUW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMINUW_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -910,7 +910,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINUD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMINUD_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -940,7 +940,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXSB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMAXSB_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -971,7 +971,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXSD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMAXSD_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1006,7 +1006,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXUW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMAXUW_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1037,7 +1037,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXUD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMAXUD_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1073,7 +1073,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULLD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMULLD_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1110,7 +1110,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHMINPOSUW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHMINPOSUW_VdqWdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1142,7 +1142,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BLENDPS_VpsWpsIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("BLENDPS_VpsWpsIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1172,7 +1172,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BLENDPD_VpdWpdIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("BLENDPD_VpdWpdIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1208,7 +1208,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PBLENDW_VdqWdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PBLENDW_VdqWdqIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1232,7 +1232,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRB_HbdUdqIb(bxInstruction_c *i)
}
#else
BX_INFO(("PEXTRB_HbdUdqIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1256,7 +1256,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_HwdUdqIb(bxInstruction_c *i)
}
#else
BX_INFO(("PEXTRW_HwdUdqIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1300,7 +1300,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRD_HdUdqIb(bxInstruction_c *i)
}
#else
BX_INFO(("PEXTRD_HdUdqIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1324,7 +1324,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRACTPS_HdUpsIb(bxInstruction_c *i)
}
#else
BX_INFO(("EXTRACTPS_HdUpsIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1353,7 +1353,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRB_VdqEbIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PINSRB_VdqEbIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1389,7 +1389,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::INSERTPS_VpsWssIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("INSERTPS_VpsWssIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1440,7 +1440,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRD_VdqEdIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PINSRD_VdqEdIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1482,7 +1482,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MPSADBW_VdqWdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("MPSADBW_VdqWdqIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1527,7 +1527,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLBW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PUNPCKLBW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1562,7 +1562,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLWD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PUNPCKLWD_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1594,7 +1594,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::UNPCKLPS_VpsWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("UNPCKLPS_VpsWdq: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1638,7 +1638,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKSSWB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PACKSSWB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1668,7 +1668,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPGTB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1703,7 +1703,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPGTW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1734,7 +1734,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPGTD_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1778,7 +1778,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKUSWB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PACKUSWB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1821,7 +1821,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHBW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PUNPCKHBW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1856,7 +1856,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHWD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PUNPCKHWD_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1888,7 +1888,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::UNPCKHPS_VpsWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("UNPCKHPS_VpsWdq: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1924,7 +1924,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKSSDW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PACKSSDW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
/* UNPCKLPD: 66 0F 14 */
@ -1952,7 +1952,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLQDQ_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PUNPCKLQDQ_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1982,7 +1982,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHQDQ_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PUNPCKHQDQ_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2014,7 +2014,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFD_VdqWdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PSHUFD_VdqWdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2047,7 +2047,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFHW_VdqWdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PSHUFHW_VdqWdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2080,7 +2080,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFLW_VdqWdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PSHUFLW_VdqWdqIb: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2110,7 +2110,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPEQB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2145,7 +2145,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPEQW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2176,7 +2176,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPEQD_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2206,7 +2206,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRW_VdqEwIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PINSRW_VdqEdIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2223,7 +2223,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_GdUdqIb(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->nnn(), result);
#else
BX_INFO(("PEXTRW_GdUdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2255,7 +2255,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHUFPS_VpsWpsIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("SHUFPS_VpsWpsIb: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2285,7 +2285,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHUFPD_VpdWpdIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("SHUFPD_VpdWpdIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2330,7 +2330,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSRLW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2371,7 +2371,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSRLD_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2410,7 +2410,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLQ_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSRLQ_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2439,7 +2439,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDQ_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PADDQ_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2483,7 +2483,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULLW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMULLW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2519,7 +2519,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBUSB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PSUBUSB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2555,7 +2555,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBUSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PSUBUSW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2585,7 +2585,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINUB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMINUB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2616,7 +2616,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ANDPS_VpsWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("ANDPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2646,7 +2646,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDUSB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PADDUSB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2681,7 +2681,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDUSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PADDUSW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2711,7 +2711,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXUB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMAXUB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2742,7 +2742,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ANDNPS_VpsWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("ANDNPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2772,7 +2772,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAVGB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PAVGB_VdqWdq: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2834,7 +2834,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PSRAW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2884,7 +2884,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PSRAD_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2919,7 +2919,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAVGW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PAVGW_VdqWdq: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2963,7 +2963,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHUW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMULHUW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3007,7 +3007,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMULHW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3037,7 +3037,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBSB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSUBSB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3072,7 +3072,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSUBSW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3107,7 +3107,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMINSW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3138,7 +3138,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ORPS_VpsWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("ORPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3168,7 +3168,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDSB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PADDSB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3203,7 +3203,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PADDSW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3238,7 +3238,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXSW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMAXSW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3269,7 +3269,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XORPS_VpsWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("XORPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3314,7 +3314,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSLLW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3355,7 +3355,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSLLD_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3394,7 +3394,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLQ_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSLLQ_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3423,7 +3423,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULUDQ_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMULUDQ_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3461,7 +3461,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMADDWD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMADDWD_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3509,7 +3509,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSADBW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSADBW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3539,7 +3539,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSUBB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3574,7 +3574,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSUBW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3605,7 +3605,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSUBD_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3634,7 +3634,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBQ_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSUBQ_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3664,7 +3664,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PADDB_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3699,7 +3699,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PADDW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3730,7 +3730,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PADDD_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3762,7 +3762,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLW_UdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), op);
#else
BX_INFO(("PSRLW_UdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3811,7 +3811,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAW_UdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), result);
#else
BX_INFO(("PSRAW_UdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3843,7 +3843,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLW_UdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), op);
#else
BX_INFO(("PSLLW_UdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3871,7 +3871,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLD_UdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), op);
#else
BX_INFO(("PSRLD_UdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3908,7 +3908,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAD_UdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), result);
#else
BX_INFO(("PSRAD_UdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3936,7 +3936,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLD_UdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), op);
#else
BX_INFO(("PSLLD_UdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3962,7 +3962,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLQ_UdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), op);
#else
BX_INFO(("PSRLQ_UdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3985,7 +3985,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLDQ_UdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), result);
#else
BX_INFO(("PSRLDQ_UdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -4011,7 +4011,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLQ_UdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), op);
#else
BX_INFO(("PSLLQ_UdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -4034,6 +4034,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLDQ_UdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), result);
#else
BX_INFO(("PSLLDQ_UdqIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

102
bochs/cpu/sse_move.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_move.cc,v 1.92 2008-06-14 16:55:45 sshwarts Exp $
// $Id: sse_move.cc,v 1.93 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -135,7 +135,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LDMXCSR(bxInstruction_c *i)
BX_MXCSR_REGISTER = new_mxcsr;
#else
BX_INFO(("LDMXCSR: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -152,7 +152,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::STMXCSR(bxInstruction_c *i)
write_virtual_dword(i->seg(), RMAddr(i), mxcsr);
#else
BX_INFO(("STMXCSR: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -271,7 +271,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
/* do not touch reserved fields */
#else
BX_INFO(("FXSAVE: required P6 support, use --enable-cpu-level=6 option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -382,7 +382,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
#else
BX_INFO(("FXRSTOR: required P6 support, use --enable-cpu-level=6 option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -416,7 +416,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_VpsWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("MOVUPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -441,7 +441,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_WpsVps(bxInstruction_c *i)
}
#else
BX_INFO(("MOVUPS_WpsVps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -469,7 +469,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_VpsWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("MOVAPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -494,7 +494,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_WpsVps(bxInstruction_c *i)
}
#else
BX_INFO(("MOVAPS_WpsVps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -526,7 +526,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("MOVSS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -552,7 +552,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_WssVss(bxInstruction_c *i)
}
#else
BX_INFO(("MOVSS_WssVss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -583,7 +583,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_VsdWsd(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("MOVSD_VsdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -609,7 +609,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_WsdVsd(bxInstruction_c *i)
}
#else
BX_INFO(("MOVSD_WsdVsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -635,7 +635,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), val64);
#else
BX_INFO(("MOVLPS_VpsMq: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -664,7 +664,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDDUP_VpdWq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("MOVDDUP_VpdWq: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -694,7 +694,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSLDUP_VpsWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("MOVSLDUP_VpsWps: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -724,7 +724,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSHDUP_VpsWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("MOVHLDUP_VpsWps: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -738,7 +738,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVLPS_MqVps(bxInstruction_c *i)
write_virtual_qword(i->seg(), RMAddr(i), BX_XMM_REG_LO_QWORD(i->nnn()));
#else
BX_INFO(("MOVLPS_MqVps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -764,7 +764,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVHPS_VpsMq(bxInstruction_c *i)
BX_WRITE_XMM_REG_HI_QWORD(i->nnn(), val64);
#else
BX_INFO(("MOVHPS_VpsMq: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -778,7 +778,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
write_virtual_qword(i->seg(), RMAddr(i), BX_XMM_REG_HI_QWORD(i->nnn()));
#else
BX_INFO(("MOVHPS_MqVps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -796,7 +796,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LDDQU_VdqMdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("LDDQU_VdqMdq: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -838,7 +838,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MASKMOVDQU_VdqUdq(bxInstruction_c *i)
#else
BX_INFO(("MASKMOVDQU_VdqUdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -859,7 +859,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->rm(), val32);
#else
BX_INFO(("MOVMSKPS_GdVRps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -878,7 +878,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPD_GdVRpd(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->rm(), val32);
#else
BX_INFO(("MOVMSKPD_GdVRpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -908,7 +908,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_VdqEd(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("MOVD_VdqEd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -940,7 +940,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VdqEq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("MOVQ_VdqEq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -965,7 +965,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdVd(bxInstruction_c *i)
}
#else
BX_INFO(("MOVD_EdVd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -990,7 +990,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_EqVq(bxInstruction_c *i)
}
#else
BX_INFO(("MOVQ_EqVq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1020,7 +1020,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("MOVQ_VqWq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1044,7 +1044,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_WqVq(bxInstruction_c *i)
}
#else
BX_INFO(("MOVQ_WqVq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1061,7 +1061,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDQ2Q_PqVRq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->rm(), mm);
#else
BX_INFO(("MOVDQ2Q_PqVRq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1081,7 +1081,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ2DQ_VdqQq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->rm(), op);
#else
BX_INFO(("MOVQ2DQ_VdqQq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1116,7 +1116,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVMSKB_GdUdq(bxInstruction_c *i)
#else
BX_INFO(("PMOVMSKB_GdUdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1132,7 +1132,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTI_MdGd(bxInstruction_c *i)
write_virtual_dword(i->seg(), RMAddr(i), BX_READ_32BIT_REG(i->nnn()));
#else
BX_INFO(("MOVNTI_MdGd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1146,7 +1146,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTI_MqGq(bxInstruction_c *i)
write_virtual_qword_64(i->seg(), RMAddr(i), BX_READ_64BIT_REG(i->nnn()));
#else
BX_INFO(("MOVNTI_MqGq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1163,7 +1163,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTPS_MpsVps(bxInstruction_c *i)
write_virtual_dqword_aligned(i->seg(), RMAddr(i), (Bit8u *)(&BX_READ_XMM_REG(i->nnn())));
#else
BX_INFO(("MOVNTPS_MpsVps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1204,7 +1204,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBW_VdqWq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVSXBW_VdqWq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1235,7 +1235,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBD_VdqWd(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVSXBD_VdqWd: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1264,7 +1264,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBQ_VdqWw(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVSXBQ_VdqWw: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1295,7 +1295,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWD_VdqWq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVSXWD_VdqWq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1324,7 +1324,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWQ_VdqWd(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVSXWQ_VdqWd: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1353,7 +1353,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXDQ_VdqWq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVSXDQ_VdqWq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1364,7 +1364,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTDQA_VdqMdq(bxInstruction_c *i)
/* source must be memory reference */
if (i->modC0()) {
BX_INFO(("MOVNTDQA_VdqMdq: must be memory reference"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
}
BX_CPU_THIS_PTR prepareSSE();
@ -1380,7 +1380,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTDQA_VdqMdq(bxInstruction_c *i)
#else
BX_INFO(("MOVNTDQA_VdqMdq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1415,7 +1415,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBW_VdqWq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVZXBW_VdqWq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1446,7 +1446,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBD_VdqWd(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVZXBD_VdqWd: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1475,7 +1475,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBQ_VdqWw(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVZXBQ_VdqWw: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1506,7 +1506,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWD_VdqWq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVZXWD_VdqWq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1535,7 +1535,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWQ_VdqWd(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVZXWQ_VdqWd: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1564,7 +1564,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXDQ_VdqWq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMOVZXDQ_VdqWq: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1627,7 +1627,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_VdqWdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PALIGNR_VdqWdqIb: required SSE3E, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

142
bochs/cpu/sse_pfp.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_pfp.cc,v 1.48 2008-05-10 18:10:53 sshwarts Exp $
// $Id: sse_pfp.cc,v 1.49 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -111,7 +111,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result.xmm64u(0));
#else
BX_INFO(("CVTPI2PS_VpsQq: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -146,7 +146,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("CVTPI2PD_VpdQd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -203,7 +203,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEd(bxInstruction_c *i)
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result);
#else
BX_INFO(("CVTSI2SD_VsdEd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -262,7 +262,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), result);
#else
BX_INFO(("CVTSI2SS_VssEd: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -309,7 +309,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPS2PI_PqWps(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("CVTTPS2PI_PqWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -353,7 +353,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPD2PI_PqWpd(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("CVTTPD2PI_PqWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -402,7 +402,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSD2SI_GdWsd(bxInstruction_c *i)
#else
BX_INFO(("CVTTSD2SI_GdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -451,7 +451,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSS2SI_GdWss(bxInstruction_c *i)
#else
BX_INFO(("CVTTSS2SI_GdWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -499,7 +499,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2PI_PqWps(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("CVTPS2PI_PqWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -544,7 +544,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2PI_PqWpd(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("CVTPD2PI_PqWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -593,7 +593,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SI_GdWsd(bxInstruction_c *i)
#else
BX_INFO(("CVTSD2SI_GdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -642,7 +642,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SI_GdWss(bxInstruction_c *i)
#else
BX_INFO(("CVTSS2SI_GdWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -688,7 +688,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2PD_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("CVTPS2PD_VpsWps: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -734,7 +734,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2PS_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("CVTPD2PS_VpdWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -772,7 +772,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SS_VsdWsd(bxInstruction_c *i)
#else
BX_INFO(("CVTSD2SS_VsdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -808,7 +808,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SD_VssWss(bxInstruction_c *i)
#else
BX_INFO(("CVTSS2SD_VssWss: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -848,7 +848,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTDQ2PS_VpsWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("CVTDQ2PS_VpsWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -895,7 +895,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2DQ_VdqWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("CVTPS2DQ_VdqWps: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -941,7 +941,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPS2DQ_VdqWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("CVTTPS2DQ_VdqWps: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -984,7 +984,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPD2DQ_VqWpd(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("CVTTPD2DQ_VqWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1028,7 +1028,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2DQ_VqWpd(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("CVTPD2DQ_VqWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1064,7 +1064,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTDQ2PD_VpdWq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("CVTDQ2PD_VpdWq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1104,7 +1104,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISS_VssWss(bxInstruction_c *i)
BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
#else
BX_INFO(("UCOMISS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1144,7 +1144,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsd(bxInstruction_c *i)
BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
#else
BX_INFO(("UCOMISD_VsdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1184,7 +1184,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISS_VpsWps(bxInstruction_c *i)
BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
#else
BX_INFO(("COMISS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1224,7 +1224,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISD_VpdWpd(bxInstruction_c *i)
BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
#else
BX_INFO(("COMISD_VpdWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1271,7 +1271,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("SQRTPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1314,7 +1314,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTPD_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("SQRTPD_VpdWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1349,7 +1349,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTSD_VsdWsd(bxInstruction_c *i)
#else
BX_INFO(("SQRTSD_VsdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1384,7 +1384,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTSS_VssWss(bxInstruction_c *i)
#else
BX_INFO(("SQRTSS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1435,7 +1435,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("ADDPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1480,7 +1480,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDPD_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("ADDPD_VpdWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1521,7 +1521,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSD_VsdWsd(bxInstruction_c *i)
#else
BX_INFO(("ADDSD_VsdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1562,7 +1562,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSS_VssWss(bxInstruction_c *i)
#else
BX_INFO(("ADDSS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1613,7 +1613,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MULPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("MULPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1658,7 +1658,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MULPD_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("MULPD_VpdWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1699,7 +1699,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MULSD_VsdWsd(bxInstruction_c *i)
#else
BX_INFO(("MULSD_VsdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1740,7 +1740,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MULSS_VssWss(bxInstruction_c *i)
#else
BX_INFO(("MULSS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1791,7 +1791,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("SUBPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1836,7 +1836,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBPD_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("SUBPD_VpdWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1877,7 +1877,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBSD_VsdWsd(bxInstruction_c *i)
#else
BX_INFO(("SUBSD_VsdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1918,7 +1918,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBSS_VssWss(bxInstruction_c *i)
#else
BX_INFO(("SUBSS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -1974,7 +1974,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MINPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("MINPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2022,7 +2022,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MINPD_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("MINPD_VpdWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2064,7 +2064,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MINSD_VsdWsd(bxInstruction_c *i)
#else
BX_INFO(("MINSD_VsdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2106,7 +2106,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MINSS_VssWss(bxInstruction_c *i)
#else
BX_INFO(("MINSS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2157,7 +2157,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("DIVPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2202,7 +2202,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVPD_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("DIVPD_VpdWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2243,7 +2243,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVSD_VsdWsd(bxInstruction_c *i)
#else
BX_INFO(("DIVSD_VsdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2284,7 +2284,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVSS_VssWss(bxInstruction_c *i)
#else
BX_INFO(("DIVSS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2340,7 +2340,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("MAXPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2388,7 +2388,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXPD_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("MAXPD_VpdWpd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2430,7 +2430,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXSD_VsdWsd(bxInstruction_c *i)
#else
BX_INFO(("MAXSD_VsdWsd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2472,7 +2472,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXSS_VssWss(bxInstruction_c *i)
#else
BX_INFO(("MAXSS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2517,7 +2517,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HADDPD_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("HADDPD_VpdWpd: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2568,7 +2568,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HADDPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("HADDPS_VpsWps: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2613,7 +2613,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HSUBPD_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("HSUBPD_VpdWpd: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2664,7 +2664,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HSUBPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("HSUBPS_VpsWps: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2742,7 +2742,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPPS_VpsWpsIb(bxInstruction_c *i)
#else
BX_INFO(("CMPPS_VpsWpsIb: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2808,7 +2808,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPPD_VpdWpdIb(bxInstruction_c *i)
#else
BX_INFO(("CMPPD_VpdWpdIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2868,7 +2868,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPSD_VsdWsdIb(bxInstruction_c *i)
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result);
#else
BX_INFO(("CMPSD_VsdWsdIb: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2928,7 +2928,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPSS_VssWssIb(bxInstruction_c *i)
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), result);
#else
BX_INFO(("CMPSS_VssWssIb: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -2973,7 +2973,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSUBPD_VpdWpd(bxInstruction_c *i)
#else
BX_INFO(("ADDSUBPD_VpdWpd: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3024,7 +3024,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSUBPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("ADDSUBPS_VpsWps: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3082,7 +3082,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDPS_VpsWpsIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("ROUNDPS_VpsWpsIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3135,7 +3135,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDPD_VpdWpdIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("ROUNDPD_VpdWpdIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3182,7 +3182,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDSS_VssWssIb(bxInstruction_c *i)
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op);
#else
BX_INFO(("ROUNDSS_VssWssIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3227,7 +3227,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDSD_VsdWsdIb(bxInstruction_c *i)
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), op);
#else
BX_INFO(("ROUNDSD_VsdWsdIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3295,7 +3295,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DPPS_VpsWpsIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("DPPS_VpsWpsIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -3351,7 +3351,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DPPD_VpdWpdIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("DPPD_VpdWpdIb: required SSE4, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

10
bochs/cpu/sse_rcp.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_rcp.cc,v 1.18 2008-03-22 21:29:41 sshwarts Exp $
// $Id: sse_rcp.cc,v 1.19 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -369,7 +369,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCPPS_VpsWps(bxInstruction_c *i)
#else
BX_INFO(("RCPPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -399,7 +399,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)
#else
BX_INFO(("RCPSS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -749,7 +749,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)
#else
BX_INFO(("RSQRTSS_VssWss: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -783,6 +783,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSQRTPS_VpsWps(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("RSQRTPS_VpsWps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

10
bochs/cpu/sse_string.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_string.cc,v 1.7 2008-04-18 14:15:58 sshwarts Exp $
// $Id: sse_string.cc,v 1.8 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007 Stanislav Shwartsman
@ -357,7 +357,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRM_VdqWdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(0, result); /* store result XMM0 */
#else
BX_INFO(("PCMPESTRM_VdqWdqIb: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -424,7 +424,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRI_VdqWdqIb(bxInstruction_c *i)
#else
BX_INFO(("PCMPESTRI_VdqWdqIb: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -485,7 +485,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRM_VdqWdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(0, result); /* store result XMM0 */
#else
BX_INFO(("PCMPISTRM_VdqWdqIb: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -543,7 +543,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRI_VdqWdqIb(bxInstruction_c *i)
#else
BX_INFO(("PCMPISTRI_VdqWdqIb: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

10
bochs/cpu/xsave.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: xsave.cc,v 1.11 2008-06-12 19:14:40 sshwarts Exp $
// $Id: xsave.cc,v 1.12 2008-07-13 15:35:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008 Stanislav Shwartsman
@ -147,7 +147,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XSAVE(bxInstruction_c *i)
// skip header update for now, required to know if a CPU feature is in its initial state
#else
BX_INFO(("XSAVE: required XSAVE support, use --enable-xsave option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -288,7 +288,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XRSTOR(bxInstruction_c *i)
}
#else
BX_INFO(("XRSTOR: required XSAVE support, use --enable-xsave option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -312,7 +312,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XGETBV(bxInstruction_c *i)
RAX = BX_CPU_THIS_PTR xcr0.getRegister();
#else
BX_INFO(("XGETBV: required XSAVE support, use --enable-xsave option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -350,6 +350,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XSETBV(bxInstruction_c *i)
BX_CPU_THIS_PTR xcr0.setRegister(EAX);
#else
BX_INFO(("XSETBV: required XSAVE support, use --enable-xsave option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

8
bochs/fpu/fpu_compare.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fpu_compare.cc,v 1.17 2008-05-10 13:34:01 sshwarts Exp $
// $Id: fpu_compare.cc,v 1.18 2008-07-13 15:35:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -157,7 +157,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOMI_ST0_STj(bxInstruction_c *i)
BX_CPU_THIS_PTR the_i387.FPU_pop();
#else
BX_INFO(("FCOMI(P)_ST0_STj: required P6 FPU, configure --enable-fpu, cpu-level=6"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -198,7 +198,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FUCOMI_ST0_STj(bxInstruction_c *i)
BX_CPU_THIS_PTR the_i387.FPU_pop();
#else
BX_INFO(("FUCOMI(P)_ST0_STj: required P6 FPU, configure --enable-fpu, cpu-level=6"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -521,7 +521,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FCMOV_ST0_STj(bxInstruction_c *i)
#else
BX_INFO(("FCMOV_ST0_STj: required P6 FPU, configure --enable-fpu, cpu-level=6"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

8
bochs/fpu/fpu_load_store.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fpu_load_store.cc,v 1.26 2008-07-13 11:22:55 sshwarts Exp $
// $Id: fpu_load_store.cc,v 1.27 2008-07-13 15:35:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -603,7 +603,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FISTTP16(bxInstruction_c *i)
BX_CPU_THIS_PTR the_i387.FPU_pop();
#else
BX_INFO(("FISTTP16: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -639,7 +639,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FISTTP32(bxInstruction_c *i)
BX_CPU_THIS_PTR the_i387.FPU_pop();
#else
BX_INFO(("FISTTP32: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -675,7 +675,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FISTTP64(bxInstruction_c *i)
BX_CPU_THIS_PTR the_i387.FPU_pop();
#else
BX_INFO(("FISTTP64: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}