From 69b829a935a5152555caf464d8797faf29d0f151 Mon Sep 17 00:00:00 2001
From: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
Date: Tue, 12 Apr 2011 06:05:31 +0000
Subject: [PATCH] small fixes

---
 bochs/cpu/avx.cc           |  9 ++++++++-
 bochs/cpu/fetchdecode.cc   |  4 ++--
 bochs/cpu/fetchdecode64.cc |  6 +++---
 bochs/cpu/logical16.cc     | 37 +++++++++++--------------------------
 bochs/cpu/logical32.cc     | 37 +++++++++++--------------------------
 bochs/cpu/logical8.cc      | 35 +++++++++++------------------------
 bochs/cpu/shift16.cc       |  2 +-
 7 files changed, 47 insertions(+), 83 deletions(-)

diff --git a/bochs/cpu/avx.cc b/bochs/cpu/avx.cc
index b02b23d60..7b4a12b17 100644
--- a/bochs/cpu/avx.cc
+++ b/bochs/cpu/avx.cc
@@ -220,7 +220,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLPD_VpdMq(bxInstruction_c *i)
 #endif
 }
 
-
 /* VEX.0F 16 (VEX.W ignore) */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLHPS_VpsWps(bxInstruction_c *i)
 {
@@ -760,6 +759,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERM2F128_VdqWdqIbR(bxInstruction_c *i)
 /* Opcode: VEX.66.0F.38 2C (VEX.W=0) */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsMps(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
   BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), result;
   unsigned len = i->getVL();
 
@@ -784,11 +784,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsMps(bxInstruction_c *i)
   }
 
   BX_WRITE_AVX_REGZ(i->nnn(), result, len);
+#endif
 }
 
 /* Opcode: VEX.66.0F.38 2D (VEX.W=0) */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdMpd(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
   BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), result;
   unsigned len = i->getVL();
 
@@ -813,11 +815,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdMpd(bxInstruction_c *i)
   }
 
   BX_WRITE_AVX_REGZ(i->nnn(), result, len);
+#endif
 }
 
 /* Opcode: VEX.66.0F.38 2C (VEX.W=0) */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsVps(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
   BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), op = BX_READ_AVX_REG(i->nnn());
   unsigned len = i->getVL();
 
@@ -844,11 +848,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsVps(bxInstruction_c *i)
     if (mask.avx32u(n) & 0x80000000)
        write_virtual_dword(i->seg(), (eaddr + 4*n) & i->asize_mask(), op.avx32u(n));
   }
+#endif
 }
 
 /* Opcode: VEX.66.0F.38 2D (VEX.W=0) */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_MpdVpd(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
   BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), op = BX_READ_AVX_REG(i->nnn());
   unsigned len = i->getVL();
 
@@ -875,6 +881,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_MpdVpd(bxInstruction_c *i)
     if (mask.avx32u(2*n+1) & 0x80000000)
        write_virtual_qword(i->seg(), (eaddr + 8*n) & i->asize_mask(), op.avx64u(n));
   }
+#endif
 }
 
 #endif
diff --git a/bochs/cpu/fetchdecode.cc b/bochs/cpu/fetchdecode.cc
index 92cef4c86..2c8809251 100644
--- a/bochs/cpu/fetchdecode.cc
+++ b/bochs/cpu/fetchdecode.cc
@@ -441,7 +441,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
 #else
   /* 0F 05 /w */ { 0, BX_IA_ERROR },
 #endif
-  /* 0F 06 /w */ { 0, BX_IA_CLTS },
+  /* 0F 06 /w */ { BxTraceEnd, BX_IA_CLTS },
 #if BX_SUPPORT_X86_64
   /* 0F 07 /w */ { BxTraceEnd, BX_IA_SYSRET },
 #else
@@ -986,7 +986,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
 #else
   /* 0F 05 /d */ { 0, BX_IA_ERROR },
 #endif
-  /* 0F 06 /d */ { 0, BX_IA_CLTS },
+  /* 0F 06 /d */ { BxTraceEnd, BX_IA_CLTS },
 #if BX_SUPPORT_X86_64
   /* 0F 07 /d */ { BxTraceEnd, BX_IA_SYSRET },
 #else
diff --git a/bochs/cpu/fetchdecode64.cc b/bochs/cpu/fetchdecode64.cc
index f5ea13f22..c1023fe96 100644
--- a/bochs/cpu/fetchdecode64.cc
+++ b/bochs/cpu/fetchdecode64.cc
@@ -402,7 +402,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
   /* 0F 03 /w */ { 0, BX_IA_LSL_GvEw },
   /* 0F 04 /w */ { 0, BX_IA_ERROR },
   /* 0F 05 /w */ { BxTraceEnd, BX_IA_SYSCALL },
-  /* 0F 06 /w */ { 0, BX_IA_CLTS },
+  /* 0F 06 /w */ { BxTraceEnd, BX_IA_CLTS },
   /* 0F 07 /w */ { BxTraceEnd, BX_IA_SYSRET },
   /* 0F 08 /w */ { BxTraceEnd, BX_IA_INVD },
   /* 0F 09 /w */ { BxTraceEnd, BX_IA_WBINVD },
@@ -917,7 +917,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
   /* 0F 03 /d */ { 0, BX_IA_LSL_GvEw },
   /* 0F 04 /d */ { 0, BX_IA_ERROR },
   /* 0F 05 /d */ { BxTraceEnd, BX_IA_SYSCALL },
-  /* 0F 06 /d */ { 0, BX_IA_CLTS },
+  /* 0F 06 /d */ { BxTraceEnd, BX_IA_CLTS },
   /* 0F 07 /d */ { BxTraceEnd, BX_IA_SYSRET },
   /* 0F 08 /d */ { BxTraceEnd, BX_IA_INVD },
   /* 0F 09 /d */ { BxTraceEnd, BX_IA_WBINVD },
@@ -1432,7 +1432,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
   /* 0F 03 /q */ { 0, BX_IA_LSL_GvEw },
   /* 0F 04 /q */ { 0, BX_IA_ERROR },
   /* 0F 05 /q */ { BxTraceEnd, BX_IA_SYSCALL },
-  /* 0F 06 /q */ { 0, BX_IA_CLTS },
+  /* 0F 06 /q */ { BxTraceEnd, BX_IA_CLTS },
   /* 0F 07 /q */ { BxTraceEnd, BX_IA_SYSRET },
   /* 0F 08 /q */ { BxTraceEnd, BX_IA_INVD },
   /* 0F 09 /q */ { BxTraceEnd, BX_IA_WBINVD },
diff --git a/bochs/cpu/logical16.cc b/bochs/cpu/logical16.cc
index a00016e9d..02a54daf7 100644
--- a/bochs/cpu/logical16.cc
+++ b/bochs/cpu/logical16.cc
@@ -52,13 +52,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GwEwR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_AXIw(bxInstruction_c *i)
 {
-  Bit16u op1_16;
+  Bit16u op_16 = AX ^ i->Iw();
+  AX = op_16;
 
-  op1_16 = AX;
-  op1_16 ^= i->Iw();
-  AX = op1_16;
-
-  SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
+  SET_FLAGS_OSZAPC_LOGIC_16(op_16);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwIwM(bxInstruction_c *i)
@@ -149,14 +146,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GwEwR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_AXIw(bxInstruction_c *i)
 {
-  Bit16u op1_16, op2_16;
+  Bit16u op_16 = AX | i->Iw();
+  AX = op_16;
 
-  op1_16 = AX;
-  op2_16 = i->Iw();
-  op1_16 |= op2_16;
-  AX = op1_16;
-
-  SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
+  SET_FLAGS_OSZAPC_LOGIC_16(op_16);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwGwM(bxInstruction_c *i)
@@ -187,14 +180,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GwEwR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_AXIw(bxInstruction_c *i)
 {
-  Bit16u op1_16, op2_16;
+  Bit16u op_16 = AX & i->Iw();
+  AX = op_16;
 
-  op1_16 = AX;
-  op2_16 = i->Iw();
-  op1_16 &= op2_16;
-  AX = op1_16;
-
-  SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
+  SET_FLAGS_OSZAPC_LOGIC_16(op_16);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwIwM(bxInstruction_c *i)
@@ -231,13 +220,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_AXIw(bxInstruction_c *i)
 {
-  Bit16u op1_16, op2_16;
+  Bit16u op_16 = AX & i->Iw();
 
-  op1_16 = AX;
-  op2_16 = i->Iw();
-  op1_16 &= op2_16;
-
-  SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
+  SET_FLAGS_OSZAPC_LOGIC_16(op_16);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwIwR(bxInstruction_c *i)
diff --git a/bochs/cpu/logical32.cc b/bochs/cpu/logical32.cc
index 341f9092c..e811f5bd7 100644
--- a/bochs/cpu/logical32.cc
+++ b/bochs/cpu/logical32.cc
@@ -57,13 +57,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GdEdR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EAXId(bxInstruction_c *i)
 {
-  Bit32u op1_32;
+  Bit32u op_32 = EAX ^ i->Id();
+  RAX = op_32;
 
-  op1_32 = EAX;
-  op1_32 ^= i->Id();
-  RAX = op1_32;
-
-  SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
+  SET_FLAGS_OSZAPC_LOGIC_32(op_32);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdIdM(bxInstruction_c *i)
@@ -154,14 +151,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GdEdR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EAXId(bxInstruction_c *i)
 {
-  Bit32u op1_32, op2_32;
+  Bit32u op_32 = EAX | i->Id();
+  RAX = op_32;
 
-  op1_32 = EAX;
-  op2_32 = i->Id();
-  op1_32 |= op2_32;
-  RAX = op1_32;
-
-  SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
+  SET_FLAGS_OSZAPC_LOGIC_32(op_32);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdGdM(bxInstruction_c *i)
@@ -192,14 +185,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GdEdR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EAXId(bxInstruction_c *i)
 {
-  Bit32u op1_32, op2_32;
+  Bit32u op_32 = EAX & i->Id();
+  RAX = op_32;
 
-  op1_32 = EAX;
-  op2_32 = i->Id();
-  op1_32 &= op2_32;
-  RAX = op1_32;
-
-  SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
+  SET_FLAGS_OSZAPC_LOGIC_32(op_32);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdIdM(bxInstruction_c *i)
@@ -237,13 +226,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
 {
-  Bit32u op1_32, op2_32;
+  Bit32u op_32 = EAX & i->Id();
 
-  op1_32 = EAX;
-  op2_32 = i->Id();
-  op1_32 &= op2_32;
-
-  SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
+  SET_FLAGS_OSZAPC_LOGIC_32(op_32);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdIdR(bxInstruction_c *i)
diff --git a/bochs/cpu/logical8.cc b/bochs/cpu/logical8.cc
index 465081f7e..37ae3ec67 100644
--- a/bochs/cpu/logical8.cc
+++ b/bochs/cpu/logical8.cc
@@ -52,11 +52,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GbEbR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_ALIb(bxInstruction_c *i)
 {
-  Bit8u op1 = AL;
-  op1 ^= i->Ib();
-  AL = op1;
+  Bit8u op_8 = AL ^ i->Ib();
+  AL = op_8;
 
-  SET_FLAGS_OSZAPC_LOGIC_8(op1);
+  SET_FLAGS_OSZAPC_LOGIC_8(op_8);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EbIbM(bxInstruction_c *i)
@@ -151,14 +150,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GbEbR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_ALIb(bxInstruction_c *i)
 {
-  Bit8u op1, op2;
+  Bit8u op_8 = AL | i->Ib();
+  AL = op_8;
 
-  op1 = AL;
-  op2 = i->Ib();
-  op1 |= op2;
-  AL = op1;
-
-  SET_FLAGS_OSZAPC_LOGIC_8(op1);
+  SET_FLAGS_OSZAPC_LOGIC_8(op_8);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EbGbM(bxInstruction_c *i)
@@ -189,14 +184,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GbEbR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_ALIb(bxInstruction_c *i)
 {
-  Bit8u op1, op2;
+  Bit8u op_8 = AL & i->Ib();
+  AL = op_8;
 
-  op1 = AL;
-  op2 = i->Ib();
-  op1 &= op2;
-  AL = op1;
-
-  SET_FLAGS_OSZAPC_LOGIC_8(op1);
+  SET_FLAGS_OSZAPC_LOGIC_8(op_8);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EbIbM(bxInstruction_c *i)
@@ -236,13 +227,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbGbR(bxInstruction_c *i)
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_ALIb(bxInstruction_c *i)
 {
-  Bit8u op1, op2;
+  Bit8u op_8 = AL & i->Ib();
 
-  op1 = AL;
-  op2 = i->Ib();
-  op1 &= op2;
-
-  SET_FLAGS_OSZAPC_LOGIC_8(op1);
+  SET_FLAGS_OSZAPC_LOGIC_8(op_8);
 }
 
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbIbR(bxInstruction_c *i)
diff --git a/bochs/cpu/shift16.cc b/bochs/cpu/shift16.cc
index b9da7e1a8..887245e2c 100644
--- a/bochs/cpu/shift16.cc
+++ b/bochs/cpu/shift16.cc
@@ -429,7 +429,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EwM(bxInstruction_c *i)
   if (! count) return;
 
   Bit16u result_16 = (op1_16 >> count) | (getB_CF() << (16 - count)) |
-              (op1_16 << (17 - count));
+                     (op1_16 << (17 - count));
 
   write_RMW_virtual_word(result_16);