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updates for CPUID definitions

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This commit is contained in:
Stanislav Shwartsman 2024-10-12 18:07:28 +03:00
parent b5665c39da
commit 67a9bffb42
2 changed files with 36 additions and 29 deletions
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11
bochs/cpu/cpuid.h
View File

@ -554,7 +554,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [18:18] LKGS instruction support // [18:18] LKGS instruction support
// [19:19] WRMSRNS instruction // [19:19] WRMSRNS instruction
// [20:20] NMI source reporting // [20:20] NMI source reporting
// [21:21] AMX-FB16 support // [21:21] AMX-FP16 support
// [22:22] HRESET and CPUID leaf 0x20 support // [22:22] HRESET and CPUID leaf 0x20 support
// [23:23] AVX IFMA support // [23:23] AVX IFMA support
// [25:24] reserved // [25:24] reserved
@ -601,11 +601,15 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// ----------------------------- // -----------------------------
// [0:0] IA32_PPIN and IA32_PPIN_CTL MSRs // [0:0] IA32_PPIN and IA32_PPIN_CTL MSRs
// [1:1] TSE: PBNDKB instruction and existence of the IA32_TSE_CAPABILITY MSR // [1:1] TSE: PBNDKB instruction and existence of the IA32_TSE_CAPABILITY MSR
// [2:2] reserved
// [3:3] CPUIDMAXVAL_LIM_RMV: IA32_MISC_ENABLE[22] cannot be set to 1 to limit the value returned by CPUID.00H:EAX[7:0]
// [31:1] reserved // [31:1] reserved
// ... // ...
#define BX_CPUID_STD7_SUBLEAF1_EBX_PPIN (1 << 0) #define BX_CPUID_STD7_SUBLEAF1_EBX_PPIN (1 << 0)
#define BX_CPUID_STD7_SUBLEAF1_EBX_TSE (1 << 1) #define BX_CPUID_STD7_SUBLEAF1_EBX_TSE (1 << 1)
#define BX_CPUID_STD7_SUBLEAF1_EBX_RESERVED2 (1 << 2)
#define BX_CPUID_STD7_SUBLEAF1_EBX_CPUIDMAXVAL_LIM_RMV (1 << 3)
// ... // ...
// CPUID defines - features CPUID[0x00000007].ECX [subleaf 1] // CPUID defines - features CPUID[0x00000007].ECX [subleaf 1]
@ -630,7 +634,8 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [16:16] reserved // [16:16] reserved
// [17:17] Flexible UIRET: UIRET sets UIF to the RFLAGS[1] image loaded from the stack // [17:17] Flexible UIRET: UIRET sets UIF to the RFLAGS[1] image loaded from the stack
// [18:18] CET_SSS // [18:18] CET_SSS
// [22:19] reserved // [19:19] AVX10 support and CPUID leaf 0x24
// [22:20] reserved
// [23:23] MWAIT and CPUID LEAF5 support // [23:23] MWAIT and CPUID LEAF5 support
// [31:24] reserved // [31:24] reserved
@ -653,7 +658,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED16 (1 << 16) #define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED16 (1 << 16)
#define BX_CPUID_STD7_SUBLEAF1_EDX_UIRET_UIF (1 << 17) #define BX_CPUID_STD7_SUBLEAF1_EDX_UIRET_UIF (1 << 17)
#define BX_CPUID_STD7_SUBLEAF1_EDX_CET_SSS (1 << 18) #define BX_CPUID_STD7_SUBLEAF1_EDX_CET_SSS (1 << 18)
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED19 (1 << 19) #define BX_CPUID_STD7_SUBLEAF1_EDX_AVX10 (1 << 19)
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED20 (1 << 20) #define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED20 (1 << 20)
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED21 (1 << 21) #define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED21 (1 << 21)
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED22 (1 << 22) #define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED22 (1 << 22)

54
bochs/cpu/crregs.h
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@ -88,32 +88,33 @@ struct bx_cr0_t {
#if BX_CPU_LEVEL >= 5 #if BX_CPU_LEVEL >= 5
#define BX_CR4_VME_MASK (1 << 0) #define BX_CR4_VME_MASK (1 << 0)
#define BX_CR4_PVI_MASK (1 << 1) #define BX_CR4_PVI_MASK (1 << 1)
#define BX_CR4_TSD_MASK (1 << 2) #define BX_CR4_TSD_MASK (1 << 2)
#define BX_CR4_DE_MASK (1 << 3) #define BX_CR4_DE_MASK (1 << 3)
#define BX_CR4_PSE_MASK (1 << 4) #define BX_CR4_PSE_MASK (1 << 4)
#define BX_CR4_PAE_MASK (1 << 5) #define BX_CR4_PAE_MASK (1 << 5)
#define BX_CR4_MCE_MASK (1 << 6) #define BX_CR4_MCE_MASK (1 << 6)
#define BX_CR4_PGE_MASK (1 << 7) #define BX_CR4_PGE_MASK (1 << 7)
#define BX_CR4_PCE_MASK (1 << 8) #define BX_CR4_PCE_MASK (1 << 8)
#define BX_CR4_OSFXSR_MASK (1 << 9) #define BX_CR4_OSFXSR_MASK (1 << 9)
#define BX_CR4_OSXMMEXCPT_MASK (1 << 10) #define BX_CR4_OSXMMEXCPT_MASK (1 << 10)
#define BX_CR4_UMIP_MASK (1 << 11) #define BX_CR4_UMIP_MASK (1 << 11)
#define BX_CR4_LA57_MASK (1 << 12) #define BX_CR4_LA57_MASK (1 << 12)
#define BX_CR4_VMXE_MASK (1 << 13) #define BX_CR4_VMXE_MASK (1 << 13)
#define BX_CR4_SMXE_MASK (1 << 14) #define BX_CR4_SMXE_MASK (1 << 14)
#define BX_CR4_FSGSBASE_MASK (1 << 16) #define BX_CR4_FSGSBASE_MASK (1 << 16)
#define BX_CR4_PCIDE_MASK (1 << 17) #define BX_CR4_PCIDE_MASK (1 << 17)
#define BX_CR4_OSXSAVE_MASK (1 << 18) #define BX_CR4_OSXSAVE_MASK (1 << 18)
#define BX_CR4_KEYLOCKER_MASK (1 << 19) #define BX_CR4_KEYLOCKER_MASK (1 << 19)
#define BX_CR4_SMEP_MASK (1 << 20) #define BX_CR4_SMEP_MASK (1 << 20)
#define BX_CR4_SMAP_MASK (1 << 21) #define BX_CR4_SMAP_MASK (1 << 21)
#define BX_CR4_PKE_MASK (1 << 22) #define BX_CR4_PKE_MASK (1 << 22)
#define BX_CR4_CET_MASK (1 << 23) #define BX_CR4_CET_MASK (1 << 23)
#define BX_CR4_PKS_MASK (1 << 24) #define BX_CR4_PKS_MASK (1 << 24)
#define BX_CR4_UINTR_MASK (1 << 25) #define BX_CR4_UINTR_MASK (1 << 25)
#define BX_CR4_LASS_MASK (1 << 27) #define BX_CR4_LASS_MASK (1 << 27)
#define BX_CR4_LAM_SUPERVISOR_MASK (1 << 28)
struct bx_cr4_t { struct bx_cr4_t {
Bit32u val32; // 32bit value of register Bit32u val32; // 32bit value of register
@ -148,6 +149,7 @@ struct bx_cr4_t {
IMPLEMENT_CRREG_ACCESSORS(PKS, 24); IMPLEMENT_CRREG_ACCESSORS(PKS, 24);
IMPLEMENT_CRREG_ACCESSORS(UINTR, 25); IMPLEMENT_CRREG_ACCESSORS(UINTR, 25);
IMPLEMENT_CRREG_ACCESSORS(LASS, 27); IMPLEMENT_CRREG_ACCESSORS(LASS, 27);
IMPLEMENT_CRREG_ACCESSORS(LAM_SUPERVISOR, 28);
BX_CPP_INLINE Bit32u get32() const { return val32; } BX_CPP_INLINE Bit32u get32() const { return val32; }
BX_CPP_INLINE void set32(Bit32u val) { val32 = val; } BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }