- uploaded 64bits-registers-extension patch from Kevin
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Christophe Bothamy
parent
88cf989396
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590
bochs/patches/patch.64bits-registers-kevin
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590
bochs/patches/patch.64bits-registers-kevin
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@ -0,0 +1,590 @@
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----------------------------------------------------------------------
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Patch name: patch.64bits-registers-kevin
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Author: Kevin Lawton
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Date: August 20th, 2002
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Detailed description:
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In response to some developers list talk about extending bochs to
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x86-64 (AMD's "Hammer"), I took the 1st step to extending the
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8 general registers to 64 bits. The upper dwords are unused
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at the moment.
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There weren't many needed changes. These mods work fine
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for me. I tested only on a small endian machine (x86), but
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coded the one endian dependent part (in "cpu.h") for
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big endian. Someone with a big-endian machine, please test.
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Behaviour shouldn't change at all with these mods. If these
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test OK for all, might want to commit them.
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-Kevin
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Some quick notes on these mods for the curious.
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The width of the registers went to 64 bits, of course.
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I decided also to increase the height of the register
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file to 64 registers from 8. X86-64 only increased
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to 16 general registers, but spare ones can be used for
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scratch calculations - especially if the decode/execute
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logic is changed to a pseudo-op / threaded interpreter
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model as was discussed on this list.
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Maybe 32 is enough. It's only one #define for now. Anyways,
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for kicks, I went through on paper, a pseudo-op format which
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would be dense enough and yet flexible enough. I think the key
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is to keep it simple and dense - which translated to CISC-like -
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especially for x86 only architectures (x86-32/64).
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A simple threaded interpreter model, with each 32-bit pseudo-op
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having some bits for the handler routine (actually just an offset
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of a GNU "goto" target from a reference goto), and some operand bits
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to express things like source & dest registers etc looks reasonable.
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Other data can be loaded and operated on in the scratch registers.
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Also, I think a new model can be shimmed into the old one, such
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that initially very few instructions would be implemented by
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the model - most would fall back to the original code. Then
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the new model can be filled out at will.
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-Kevin
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Patch was created with:
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cvs diff -u
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Apply patch to what version:
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cvs checked out on August 20th, 2002
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Instructions:
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To patch, go to main bochs directory.
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Type "patch -p0 < THIS_PATCH_FILE".
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----------------------------------------------------------------------
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Index: debug/dbg_main.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/debug/dbg_main.cc,v
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retrieving revision 1.47
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diff -u -r1.47 dbg_main.cc
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--- debug/dbg_main.cc 5 Aug 2002 16:35:08 -0000 1.47
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+++ debug/dbg_main.cc 20 Aug 2002 10:37:01 -0000
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@@ -25,10 +25,10 @@
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// define shortcuts to get register from the default CPU
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-#define EBP (BX_CPU(dbg_cpu)->gen_reg[5].erx)
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+#define EBP (BX_CPU(dbg_cpu)->regFile[5].dwords.low.val32)
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#define EIP (BX_CPU(dbg_cpu)->eip)
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-#define ESP (BX_CPU(dbg_cpu)->gen_reg[4].erx)
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-#define SP (BX_CPU(dbg_cpu)->gen_reg[4].word.rx)
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+#define ESP (BX_CPU(dbg_cpu)->regFile[4].dwords.low.val32)
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+#define SP (BX_CPU(dbg_cpu)->regFile[4].dwords.low.words.low.val16)
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extern "C" {
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#include <signal.h>
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@@ -2085,14 +2085,14 @@
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if( BX_CPU(dbg_cpu)->trace_reg )
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fprintf( stderr,
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"eax: %08X\tecx: %08X\tedx: %08X\tebx: %08X\tesp: %08X\tebp: %08X\tesi: %08X\tedi: %08X\ncf=%u af=%u zf=%u sf=%u of=%u pf=%u tf=%u if=%u df=%u iopl=%u nt=%u rf=%u vm=%u\n",
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- BX_CPU(which_cpu)->gen_reg[0],
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- BX_CPU(which_cpu)->gen_reg[1],
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- BX_CPU(which_cpu)->gen_reg[2],
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- BX_CPU(which_cpu)->gen_reg[3],
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- BX_CPU(which_cpu)->gen_reg[4],
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- BX_CPU(which_cpu)->gen_reg[5],
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- BX_CPU(which_cpu)->gen_reg[6],
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- BX_CPU(which_cpu)->gen_reg[7],
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+ BX_CPU(which_cpu)->regFile[0].dwords.low.val32,
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+ BX_CPU(which_cpu)->regFile[1].dwords.low.val32,
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+ BX_CPU(which_cpu)->regFile[2].dwords.low.val32,
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+ BX_CPU(which_cpu)->regFile[3].dwords.low.val32,
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+ BX_CPU(which_cpu)->regFile[4].dwords.low.val32,
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+ BX_CPU(which_cpu)->regFile[5].dwords.low.val32,
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+ BX_CPU(which_cpu)->regFile[6].dwords.low.val32,
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+ BX_CPU(which_cpu)->regFile[7].dwords.low.val32,
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!!BX_CPU(which_cpu)->get_CF(),
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!!BX_CPU(which_cpu)->get_AF(),
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!!BX_CPU(which_cpu)->get_ZF(),
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Index: fpu/wmFPUemu_glue.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/fpu/wmFPUemu_glue.cc,v
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retrieving revision 1.9
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diff -u -r1.9 wmFPUemu_glue.cc
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--- fpu/wmFPUemu_glue.cc 15 Sep 2001 06:55:14 -0000 1.9
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+++ fpu/wmFPUemu_glue.cc 20 Aug 2002 10:37:01 -0000
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@@ -172,7 +172,7 @@
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{
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// define to set AX in the current CPU -- not ideal.
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#undef AX
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-#define AX (fpu_cpu_ptr->gen_reg[0].word.rx)
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+#define AX (fpu_cpu_ptr->regFile[0].dwords.low.words.low.val16)
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AX = val16;
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#undef AX
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//BX_DEBUG(( "fpu_set_ax(0x%04x)", (unsigned) val16));
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Index: cpu/arith16.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/arith16.cc,v
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retrieving revision 1.6
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diff -u -r1.6 arith16.cc
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--- cpu/arith16.cc 3 Oct 2001 13:10:37 -0000 1.6
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+++ cpu/arith16.cc 20 Aug 2002 10:37:01 -0000
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@@ -38,7 +38,7 @@
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{
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Bit16u rx;
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- rx = ++ BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx;
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+ rx = ++ BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.words.low.val16;
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SET_FLAGS_OSZAP_16(0, 0, rx, BX_INSTR_INC16);
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}
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@@ -47,7 +47,7 @@
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{
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Bit16u rx;
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- rx = -- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx;
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+ rx = -- BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.words.low.val16;
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SET_FLAGS_OSZAP_16(0, 0, rx, BX_INSTR_DEC16);
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}
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Index: cpu/arith32.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/arith32.cc,v
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retrieving revision 1.7
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diff -u -r1.7 arith32.cc
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--- cpu/arith32.cc 17 Nov 2001 22:22:03 -0000 1.7
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+++ cpu/arith32.cc 20 Aug 2002 10:37:01 -0000
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@@ -38,7 +38,7 @@
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{
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Bit32u erx;
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- erx = ++ BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx;
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+ erx = ++ BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.val32;
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SET_FLAGS_OSZAP_32(0, 0, erx, BX_INSTR_INC32);
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}
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@@ -47,7 +47,7 @@
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{
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Bit32u erx;
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- erx = -- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx;
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+ erx = -- BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.val32;
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SET_FLAGS_OSZAP_32(0, 0, erx, BX_INSTR_DEC32);
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}
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Index: cpu/cpu.h
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
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retrieving revision 1.22
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diff -u -r1.22 cpu.h
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--- cpu/cpu.h 5 Jun 2002 21:51:30 -0000 1.22
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+++ cpu/cpu.h 20 Aug 2002 10:37:01 -0000
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@@ -99,49 +99,49 @@
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*/
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// access to 8 bit general registers
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-#define AL (BX_CPU_THIS_PTR gen_reg[0].word.byte.rl)
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-#define CL (BX_CPU_THIS_PTR gen_reg[1].word.byte.rl)
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-#define DL (BX_CPU_THIS_PTR gen_reg[2].word.byte.rl)
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-#define BL (BX_CPU_THIS_PTR gen_reg[3].word.byte.rl)
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-#define AH (BX_CPU_THIS_PTR gen_reg[0].word.byte.rh)
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-#define CH (BX_CPU_THIS_PTR gen_reg[1].word.byte.rh)
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-#define DH (BX_CPU_THIS_PTR gen_reg[2].word.byte.rh)
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-#define BH (BX_CPU_THIS_PTR gen_reg[3].word.byte.rh)
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+#define AL (BX_CPU_THIS_PTR regFile[0].dwords.low.words.low.bytes.low)
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+#define CL (BX_CPU_THIS_PTR regFile[1].dwords.low.words.low.bytes.low)
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+#define DL (BX_CPU_THIS_PTR regFile[2].dwords.low.words.low.bytes.low)
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+#define BL (BX_CPU_THIS_PTR regFile[3].dwords.low.words.low.bytes.low)
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+#define AH (BX_CPU_THIS_PTR regFile[0].dwords.low.words.low.bytes.high)
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+#define CH (BX_CPU_THIS_PTR regFile[1].dwords.low.words.low.bytes.high)
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+#define DH (BX_CPU_THIS_PTR regFile[2].dwords.low.words.low.bytes.high)
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+#define BH (BX_CPU_THIS_PTR regFile[3].dwords.low.words.low.bytes.high)
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// access to 16 bit general registers
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-#define AX (BX_CPU_THIS_PTR gen_reg[0].word.rx)
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-#define CX (BX_CPU_THIS_PTR gen_reg[1].word.rx)
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-#define DX (BX_CPU_THIS_PTR gen_reg[2].word.rx)
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-#define BX (BX_CPU_THIS_PTR gen_reg[3].word.rx)
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-#define SP (BX_CPU_THIS_PTR gen_reg[4].word.rx)
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-#define BP (BX_CPU_THIS_PTR gen_reg[5].word.rx)
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-#define SI (BX_CPU_THIS_PTR gen_reg[6].word.rx)
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-#define DI (BX_CPU_THIS_PTR gen_reg[7].word.rx)
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+#define AX (BX_CPU_THIS_PTR regFile[0].dwords.low.words.low.val16)
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+#define CX (BX_CPU_THIS_PTR regFile[1].dwords.low.words.low.val16)
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+#define DX (BX_CPU_THIS_PTR regFile[2].dwords.low.words.low.val16)
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+#define BX (BX_CPU_THIS_PTR regFile[3].dwords.low.words.low.val16)
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+#define SP (BX_CPU_THIS_PTR regFile[4].dwords.low.words.low.val16)
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+#define BP (BX_CPU_THIS_PTR regFile[5].dwords.low.words.low.val16)
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+#define SI (BX_CPU_THIS_PTR regFile[6].dwords.low.words.low.val16)
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+#define DI (BX_CPU_THIS_PTR regFile[7].dwords.low.words.low.val16)
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// access to 16 bit instruction pointer
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#define IP (* (Bit16u *) (((Bit8u *) &BX_CPU_THIS_PTR eip) + BX_REG16_OFFSET))
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// accesss to 32 bit general registers
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-#define EAX BX_CPU_THIS_PTR gen_reg[0].erx
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-#define ECX BX_CPU_THIS_PTR gen_reg[1].erx
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-#define EDX BX_CPU_THIS_PTR gen_reg[2].erx
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-#define EBX BX_CPU_THIS_PTR gen_reg[3].erx
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-#define ESP BX_CPU_THIS_PTR gen_reg[4].erx
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-#define EBP BX_CPU_THIS_PTR gen_reg[5].erx
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-#define ESI BX_CPU_THIS_PTR gen_reg[6].erx
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-#define EDI BX_CPU_THIS_PTR gen_reg[7].erx
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+#define EAX BX_CPU_THIS_PTR regFile[0].dwords.low.val32
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+#define ECX BX_CPU_THIS_PTR regFile[1].dwords.low.val32
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+#define EDX BX_CPU_THIS_PTR regFile[2].dwords.low.val32
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+#define EBX BX_CPU_THIS_PTR regFile[3].dwords.low.val32
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+#define ESP BX_CPU_THIS_PTR regFile[4].dwords.low.val32
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+#define EBP BX_CPU_THIS_PTR regFile[5].dwords.low.val32
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+#define ESI BX_CPU_THIS_PTR regFile[6].dwords.low.val32
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+#define EDI BX_CPU_THIS_PTR regFile[7].dwords.low.val32
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// access to 32 bit instruction pointer
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#define EIP BX_CPU_THIS_PTR eip
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#define BX_READ_8BIT_REG(index) (((index) < 4) ? \
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- (BX_CPU_THIS_PTR gen_reg[index].word.byte.rl) : \
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- (BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh))
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-#define BX_READ_16BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].word.rx)
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-#define BX_READ_32BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].erx)
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+ (BX_CPU_THIS_PTR regFile[index].dwords.low.words.low.bytes.low) : \
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+ (BX_CPU_THIS_PTR regFile[(index)-4].dwords.low.words.low.bytes.high))
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+#define BX_READ_16BIT_REG(index) (BX_CPU_THIS_PTR regFile[index].dwords.low.words.low.val16)
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+#define BX_READ_32BIT_REG(index) (BX_CPU_THIS_PTR regFile[index].dwords.low.val32)
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#define BX_READ_16BIT_BASE_REG(var, index) {\
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var = *BX_CPU_THIS_PTR _16bit_base_reg[index];\
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@@ -153,15 +153,15 @@
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#define BX_WRITE_8BIT_REG(index, val) {\
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if ((index) < 4) \
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- BX_CPU_THIS_PTR gen_reg[index].word.byte.rl = val; \
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+ BX_CPU_THIS_PTR regFile[index].dwords.low.words.low.bytes.low = val; \
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else \
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- BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh = val; \
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+ BX_CPU_THIS_PTR regFile[(index)-4].dwords.low.words.low.bytes.high = val; \
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}
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#define BX_WRITE_16BIT_REG(index, val) {\
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- BX_CPU_THIS_PTR gen_reg[index].word.rx = val; \
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+ BX_CPU_THIS_PTR regFile[index].dwords.low.words.low.val16 = val; \
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}
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#define BX_WRITE_32BIT_REG(index, val) {\
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- BX_CPU_THIS_PTR gen_reg[index].erx = val; \
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+ BX_CPU_THIS_PTR regFile[index].dwords.low.val32 = val; \
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}
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@@ -527,37 +527,45 @@
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#ifdef BX_BIG_ENDIAN
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-typedef struct {
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- union {
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- Bit32u erx;
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- struct {
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- Bit16u word_filler;
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- union {
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- Bit16u rx;
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- struct {
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- Bit8u rh;
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- Bit8u rl;
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- } byte;
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- };
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- } word;
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- };
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- } bx_gen_reg_t;
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+typedef union {
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+ Bit64u val64;
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+ struct {
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+ Bit32u high;
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+ union {
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+ Bit32u val32;
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+ struct {
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+ Bit16u high;
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+ union {
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+ Bit16u val16;
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+ struct {
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+ Bit8u high;
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+ Bit8u low;
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+ } bytes;
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+ } low;
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+ } words;
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+ } low;
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+ } dwords;
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+ } regFileEntry_t;
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#else
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-typedef struct {
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- union {
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- Bit32u erx;
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- struct {
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- union {
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- Bit16u rx;
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- struct {
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- Bit8u rl;
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- Bit8u rh;
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- } byte;
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- };
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- Bit16u word_filler;
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- } word;
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- };
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- } bx_gen_reg_t;
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+typedef union {
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+ Bit64u val64;
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+ struct {
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+ union {
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+ Bit32u val32;
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+ struct {
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+ union {
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+ Bit16u val16;
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+ struct {
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+ Bit8u low;
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+ Bit8u high;
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+ } bytes;
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+ } low;
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+ Bit16u high;
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+ } words;
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+ } low;
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+ Bit32u high;
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+ } dwords;
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+ } regFileEntry_t;
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#endif
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@@ -713,16 +721,20 @@
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char name[64];
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- // General register set
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- // eax: accumulator
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- // ebx: base
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- // ecx: count
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- // edx: data
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- // ebp: base pointer
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- // esi: source index
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- // edi: destination index
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- // esp: stack pointer
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- bx_gen_reg_t gen_reg[8];
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+ // Register File. 1st 8 match with x86 general register set. The
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+ // remaining ones are available for the interpreter.
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+ // regFile[0] (eax): accumulator
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+ // regFile[1] (ebx): base
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+ // regFile[2] (ecx): count
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+ // regFile[3] (edx): data
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+ // regFile[4] (ebp): base pointer
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+ // regFile[5] (esi): source index
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+ // regFile[6] (edi): destination index
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+ // regFile[7] (esp): stack pointer
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+ // regFile[8 .. RegFileHeight-1] : working registers for interpreter
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+
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+#define RegFileHeight 64
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+ regFileEntry_t regFile[RegFileHeight];
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Bit32u eip; // instruction pointer
|
||||
#if BX_CPU_LEVEL > 0
|
||||
@@ -731,27 +743,6 @@
|
||||
// each fetch/execute cycle.
|
||||
Bit32u prev_eip;
|
||||
#endif
|
||||
- // A few pointer to functions for use by the dynamic translation
|
||||
- // code. Keep them close to the gen_reg declaration, so I can
|
||||
- // use an 8bit offset to access them.
|
||||
-
|
||||
-#if BX_DYNAMIC_TRANSLATION
|
||||
- BxDTShim_t DTWrite8vShim;
|
||||
- BxDTShim_t DTWrite16vShim;
|
||||
- BxDTShim_t DTWrite32vShim;
|
||||
- BxDTShim_t DTRead8vShim;
|
||||
- BxDTShim_t DTRead16vShim;
|
||||
- BxDTShim_t DTRead32vShim;
|
||||
- BxDTShim_t DTReadRMW8vShim;
|
||||
- BxDTShim_t DTReadRMW16vShim;
|
||||
- BxDTShim_t DTReadRMW32vShim;
|
||||
- BxDTShim_t DTWriteRMW8vShim;
|
||||
- BxDTShim_t DTWriteRMW16vShim;
|
||||
- BxDTShim_t DTWriteRMW32vShim;
|
||||
- BxDTShim_t DTSetFlagsOSZAPCPtr;
|
||||
- BxDTShim_t DTIndBrHandler;
|
||||
- BxDTShim_t DTDirBrHandler;
|
||||
-#endif
|
||||
|
||||
// status and control flags register set
|
||||
Bit32u lf_flags_status;
|
||||
@@ -826,7 +817,7 @@
|
||||
// for accessing registers by index number
|
||||
Bit16u *_16bit_base_reg[8];
|
||||
Bit16u *_16bit_index_reg[8];
|
||||
- Bit32u empty_register;
|
||||
+ regFileEntry_t empty_register;
|
||||
|
||||
// for decoding instructions; accessing seg reg's by index
|
||||
unsigned sreg_mod00_rm16[8];
|
||||
Index: cpu/data_xfer16.cc
|
||||
===================================================================
|
||||
RCS file: /cvsroot/bochs/bochs/cpu/data_xfer16.cc,v
|
||||
retrieving revision 1.6
|
||||
diff -u -r1.6 data_xfer16.cc
|
||||
--- cpu/data_xfer16.cc 3 Oct 2001 13:10:37 -0000 1.6
|
||||
+++ cpu/data_xfer16.cc 20 Aug 2002 10:37:01 -0000
|
||||
@@ -37,7 +37,7 @@
|
||||
void
|
||||
BX_CPU_C::MOV_RXIw(BxInstruction_t *i)
|
||||
{
|
||||
- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx = i->Iw;
|
||||
+ BX_WRITE_16BIT_REG(i->b1 & 0x07, i->Iw);
|
||||
}
|
||||
|
||||
void
|
||||
@@ -46,8 +46,8 @@
|
||||
Bit16u temp16;
|
||||
|
||||
temp16 = AX;
|
||||
- AX = BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx;
|
||||
- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx = temp16;
|
||||
+ AX = BX_READ_16BIT_REG(i->b1 & 0x07);
|
||||
+ BX_WRITE_16BIT_REG(i->b1 & 0x07, temp16);
|
||||
}
|
||||
|
||||
|
||||
Index: cpu/data_xfer32.cc
|
||||
===================================================================
|
||||
RCS file: /cvsroot/bochs/bochs/cpu/data_xfer32.cc,v
|
||||
retrieving revision 1.6
|
||||
diff -u -r1.6 data_xfer32.cc
|
||||
--- cpu/data_xfer32.cc 3 Oct 2001 13:10:37 -0000 1.6
|
||||
+++ cpu/data_xfer32.cc 20 Aug 2002 10:37:01 -0000
|
||||
@@ -41,14 +41,14 @@
|
||||
Bit32u temp32;
|
||||
|
||||
temp32 = EAX;
|
||||
- EAX = BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx;
|
||||
- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx = temp32;
|
||||
+ EAX = BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.val32;
|
||||
+ BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.val32 = temp32;
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::MOV_ERXId(BxInstruction_t *i)
|
||||
{
|
||||
- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx = i->Id;
|
||||
+ BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.val32 = i->Id;
|
||||
}
|
||||
|
||||
void
|
||||
Index: cpu/data_xfer8.cc
|
||||
===================================================================
|
||||
RCS file: /cvsroot/bochs/bochs/cpu/data_xfer8.cc,v
|
||||
retrieving revision 1.5
|
||||
diff -u -r1.5 data_xfer8.cc
|
||||
--- cpu/data_xfer8.cc 3 Oct 2001 13:10:37 -0000 1.5
|
||||
+++ cpu/data_xfer8.cc 20 Aug 2002 10:37:01 -0000
|
||||
@@ -37,13 +37,13 @@
|
||||
void
|
||||
BX_CPU_C::MOV_RLIb(BxInstruction_t *i)
|
||||
{
|
||||
- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x03].word.byte.rl = i->Ib;
|
||||
+ BX_CPU_THIS_PTR regFile[i->b1 & 0x03].dwords.low.words.low.bytes.low = i->Ib;
|
||||
}
|
||||
|
||||
void
|
||||
BX_CPU_C::MOV_RHIb(BxInstruction_t *i)
|
||||
{
|
||||
- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x03].word.byte.rh = i->Ib;
|
||||
+ BX_CPU_THIS_PTR regFile[i->b1 & 0x03].dwords.low.words.low.bytes.high = i->Ib;
|
||||
}
|
||||
|
||||
|
||||
Index: cpu/init.cc
|
||||
===================================================================
|
||||
RCS file: /cvsroot/bochs/bochs/cpu/init.cc,v
|
||||
retrieving revision 1.16
|
||||
diff -u -r1.16 init.cc
|
||||
--- cpu/init.cc 5 Jun 2002 21:51:30 -0000 1.16
|
||||
+++ cpu/init.cc 20 Aug 2002 10:37:01 -0000
|
||||
@@ -63,26 +63,26 @@
|
||||
you can assume there's always a base & index register used. For
|
||||
modes which don't really use them, point to an empty (zeroed) register.
|
||||
*/
|
||||
- empty_register = 0;
|
||||
+ empty_register.val64 = 0;
|
||||
|
||||
// 16bit address mode base register, used for mod-rm decoding
|
||||
|
||||
- _16bit_base_reg[0] = &gen_reg[BX_16BIT_REG_BX].word.rx;
|
||||
- _16bit_base_reg[1] = &gen_reg[BX_16BIT_REG_BX].word.rx;
|
||||
- _16bit_base_reg[2] = &gen_reg[BX_16BIT_REG_BP].word.rx;
|
||||
- _16bit_base_reg[3] = &gen_reg[BX_16BIT_REG_BP].word.rx;
|
||||
+ _16bit_base_reg[0] = ®File[BX_16BIT_REG_BX].dwords.low.words.low.val16;
|
||||
+ _16bit_base_reg[1] = ®File[BX_16BIT_REG_BX].dwords.low.words.low.val16;
|
||||
+ _16bit_base_reg[2] = ®File[BX_16BIT_REG_BP].dwords.low.words.low.val16;
|
||||
+ _16bit_base_reg[3] = ®File[BX_16BIT_REG_BP].dwords.low.words.low.val16;
|
||||
_16bit_base_reg[4] = (Bit16u*) &empty_register;
|
||||
_16bit_base_reg[5] = (Bit16u*) &empty_register;
|
||||
- _16bit_base_reg[6] = &gen_reg[BX_16BIT_REG_BP].word.rx;
|
||||
- _16bit_base_reg[7] = &gen_reg[BX_16BIT_REG_BX].word.rx;
|
||||
+ _16bit_base_reg[6] = ®File[BX_16BIT_REG_BP].dwords.low.words.low.val16;
|
||||
+ _16bit_base_reg[7] = ®File[BX_16BIT_REG_BX].dwords.low.words.low.val16;
|
||||
|
||||
// 16bit address mode index register, used for mod-rm decoding
|
||||
- _16bit_index_reg[0] = &gen_reg[BX_16BIT_REG_SI].word.rx;
|
||||
- _16bit_index_reg[1] = &gen_reg[BX_16BIT_REG_DI].word.rx;
|
||||
- _16bit_index_reg[2] = &gen_reg[BX_16BIT_REG_SI].word.rx;
|
||||
- _16bit_index_reg[3] = &gen_reg[BX_16BIT_REG_DI].word.rx;
|
||||
- _16bit_index_reg[4] = &gen_reg[BX_16BIT_REG_SI].word.rx;
|
||||
- _16bit_index_reg[5] = &gen_reg[BX_16BIT_REG_DI].word.rx;
|
||||
+ _16bit_index_reg[0] = ®File[BX_16BIT_REG_SI].dwords.low.words.low.val16;
|
||||
+ _16bit_index_reg[1] = ®File[BX_16BIT_REG_DI].dwords.low.words.low.val16;
|
||||
+ _16bit_index_reg[2] = ®File[BX_16BIT_REG_SI].dwords.low.words.low.val16;
|
||||
+ _16bit_index_reg[3] = ®File[BX_16BIT_REG_DI].dwords.low.words.low.val16;
|
||||
+ _16bit_index_reg[4] = ®File[BX_16BIT_REG_SI].dwords.low.words.low.val16;
|
||||
+ _16bit_index_reg[5] = ®File[BX_16BIT_REG_DI].dwords.low.words.low.val16;
|
||||
_16bit_index_reg[6] = (Bit16u*) &empty_register;
|
||||
_16bit_index_reg[7] = (Bit16u*) &empty_register;
|
||||
|
||||
Index: cpu/stack16.cc
|
||||
===================================================================
|
||||
RCS file: /cvsroot/bochs/bochs/cpu/stack16.cc,v
|
||||
retrieving revision 1.7
|
||||
diff -u -r1.7 stack16.cc
|
||||
--- cpu/stack16.cc 3 Oct 2001 13:10:37 -0000 1.7
|
||||
+++ cpu/stack16.cc 20 Aug 2002 10:37:01 -0000
|
||||
@@ -39,7 +39,7 @@
|
||||
void
|
||||
BX_CPU_C::PUSH_RX(BxInstruction_t *i)
|
||||
{
|
||||
- push_16( BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx );
|
||||
+ push_16( BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.words.low.val16 );
|
||||
}
|
||||
|
||||
void
|
||||
@@ -48,7 +48,7 @@
|
||||
Bit16u rx;
|
||||
|
||||
pop_16(&rx);
|
||||
- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx = rx;
|
||||
+ BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.words.low.val16 = rx;
|
||||
}
|
||||
|
||||
void
|
||||
Index: cpu/stack32.cc
|
||||
===================================================================
|
||||
RCS file: /cvsroot/bochs/bochs/cpu/stack32.cc,v
|
||||
retrieving revision 1.8
|
||||
diff -u -r1.8 stack32.cc
|
||||
--- cpu/stack32.cc 5 Mar 2002 15:50:17 -0000 1.8
|
||||
+++ cpu/stack32.cc 20 Aug 2002 10:37:01 -0000
|
||||
@@ -63,7 +63,7 @@
|
||||
void
|
||||
BX_CPU_C::PUSH_ERX(BxInstruction_t *i)
|
||||
{
|
||||
- push_32(BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx);
|
||||
+ push_32(BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.val32);
|
||||
}
|
||||
|
||||
void
|
||||
@@ -72,7 +72,7 @@
|
||||
Bit32u erx;
|
||||
|
||||
pop_32(&erx);
|
||||
- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx = erx;
|
||||
+ BX_CPU_THIS_PTR regFile[i->b1 & 0x07].dwords.low.val32 = erx;
|
||||
}
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user