mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Small disasm fixes

Browse Source
This commit is contained in:
Stanislav Shwartsman 2005-10-23 20:43:32 +00:00
parent 34ec2c532a
commit 5af5d80602
6 changed files with 42 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
bochs/disasm/dis_decode.cc
View File

@ -80,8 +80,8 @@ static const unsigned char instruction_has_modrm[512] = {
unsigned disassembler::disasm(bx_bool is_32,
bx_address base, bx_address ip, Bit8u *instr, char *disbuf)
{
i32bit_opsize = is_32;
i32bit_addrsize = is_32;
os_32 = is_32;
as_32 = is_32;
db_eip = ip;
db_base = base; // cs linear base (base for PM & cs<<4 for RM & VM)
Bit8u *instruction_begin = instruction = instr;
@ -129,12 +129,12 @@ unsigned disassembler::disasm(bx_bool is_32,
break;
case 0x66:
i32bit_opsize = !is_32;
os_32 = !is_32;
sse_prefix |= SSE_PREFIX_66;
break;
case 0x67:
i32bit_addrsize = !is_32;
as_32 = !is_32;
break;
case 0xf0: // lock

22
bochs/disasm/dis_groups.cc
View File

@ -8,7 +8,7 @@
// 16/32-bit general purpose register
void disassembler::REG32 (unsigned attr)
{
if (i32bit_opsize)
if (os_32)
dis_sprintf("%s", general_32bit_regname[attr]);
else
dis_sprintf("%s", general_16bit_regname[attr]);
@ -87,7 +87,7 @@ void disassembler::OP_X (unsigned attr)
{
const char *esi, *seg;
if (i32bit_addrsize)
if (as_32)
esi = general_32bit_regname[eSI_REG];
else
esi = general_16bit_regname[eSI_REG];
@ -109,7 +109,7 @@ void disassembler::OP_Y (unsigned attr)
{
const char *edi;
if (i32bit_addrsize)
if (as_32)
edi = general_32bit_regname[eDI_REG];
else
edi = general_16bit_regname[eDI_REG];
@ -133,7 +133,7 @@ void disassembler::OP_O (unsigned attr)
print_datasize(attr);
if (i32bit_addrsize) {
if (as_32) {
Bit32u imm32 = fetch_dword();
dis_sprintf("%s:0x%x", seg, (unsigned) imm32);
}
@ -147,7 +147,7 @@ void disassembler::Jb (unsigned attr)
{
Bit8s imm8; /* JMP rel8 is signed */
imm8 = (Bit8s) fetch_byte();
if (i32bit_opsize) {
if (os_32) {
#if BX_DEBUGGER
char *Sym=bx_dbg_disasm_symbolic_address((Bit32u)(imm8+db_eip), db_base);
if(Sym) {
@ -172,7 +172,7 @@ void disassembler::Jb (unsigned attr)
void disassembler::Jv (unsigned attr)
{
if (i32bit_opsize) {
if (os_32) {
Bit32s imm32; /* JMP rel32 is signed */
imm32 = (Bit32s) fetch_dword();
#if BX_DEBUGGER
@ -201,7 +201,7 @@ void disassembler::Jv (unsigned attr)
void disassembler::Ap (unsigned attr)
{
if (i32bit_opsize)
if (os_32)
{
Bit32u imm32 = fetch_dword();
Bit16u cs_selector = fetch_word();
@ -234,7 +234,7 @@ void disassembler::Ew (unsigned attr)
void disassembler::Ev (unsigned attr)
{
if (i32bit_opsize)
if (os_32)
Ed(attr);
else
Ew(attr);
@ -256,7 +256,7 @@ void disassembler::Gb (unsigned attr)
void disassembler::Gv (unsigned attr)
{
if (i32bit_opsize)
if (os_32)
dis_sprintf("%s", general_32bit_regname[nnn]);
else
dis_sprintf("%s", general_16bit_regname[nnn]);
@ -318,7 +318,7 @@ void disassembler::Id (unsigned attr)
void disassembler::Iv (unsigned attr)
{
if (i32bit_opsize)
if (os_32)
Id(attr);
else
Iw(attr);
@ -327,7 +327,7 @@ void disassembler::Iv (unsigned attr)
// sign extended immediate
void disassembler::sIb(unsigned attr)
{
if (i32bit_opsize)
if (os_32)
{
Bit32u imm32 = (Bit8s) fetch_byte();
if (intel_mode)

33
bochs/disasm/dis_tables.h
View File

@ -108,8 +108,7 @@
#define Yv &disassembler::OP_Y, V_SIZE
// mov
#define Ob &disassembler::OP_O, B_SIZE
#define Ov &disassembler::OP_O, V_SIZE
#define OX &disassembler::OP_O, 0
// immediate
#define I1 &disassembler::I1, 0
@ -2160,15 +2159,15 @@ static BxDisasmOpcodeInfo_t BxDisasmOpcodes[256*2] = {
/* 03 */ { "addV", 0, Gv, Ev, XX },
/* 04 */ { "addB", 0, AL, Ib, XX },
/* 05 */ { "addV", 0, eAX, Iv, XX },
/* 06 */ { "push", 0, ES, XX, XX },
/* 07 */ { "pop", 0, ES, XX, XX },
/* 06 */ { "pushV", 0, ES, XX, XX },
/* 07 */ { "popV", 0, ES, XX, XX },
/* 08 */ { "orB", 0, Eb, Gb, XX },
/* 09 */ { "orV", 0, Ev, Gv, XX },
/* 0A */ { "orB", 0, Gb, Eb, XX },
/* 0B */ { "orV", 0, Gv, Ev, XX },
/* 0C */ { "orB", 0, AL, Ib, XX },
/* 0D */ { "orV", 0, eAX, Iv, XX },
/* 0E */ { "push", 0, CS, XX, XX },
/* 0E */ { "pushV", 0, CS, XX, XX },
/* 0F */ { "(error)", 0, XX, XX, XX }, // 2 byte escape
/* 10 */ { "adcB", 0, Eb, Gb, XX },
/* 11 */ { "adcV", 0, Ev, Gv, XX },
@ -2176,16 +2175,16 @@ static BxDisasmOpcodeInfo_t BxDisasmOpcodes[256*2] = {
/* 13 */ { "adcV", 0, Gv, Ev, XX },
/* 14 */ { "adcB", 0, AL, Ib, XX },
/* 15 */ { "adcV", 0, eAX, Iv, XX },
/* 16 */ { "push", 0, SS, XX, XX },
/* 17 */ { "pop", 0, SS, XX, XX },
/* 16 */ { "pushV", 0, SS, XX, XX },
/* 17 */ { "popV", 0, SS, XX, XX },
/* 18 */ { "sbbB", 0, Eb, Gb, XX },
/* 19 */ { "sbbV", 0, Ev, Gv, XX },
/* 1A */ { "sbbB", 0, Gb, Eb, XX },
/* 1B */ { "sbbV", 0, Gv, Ev, XX },
/* 1C */ { "sbbB", 0, AL, Ib, XX },
/* 1D */ { "sbbV", 0, eAX, Iv, XX },
/* 1E */ { "push", 0, DS, XX, XX },
/* 1F */ { "pop", 0, DS, XX, XX },
/* 1E */ { "pushV", 0, DS, XX, XX },
/* 1F */ { "popV", 0, DS, XX, XX },
/* 20 */ { "andB", 0, Eb, Gb, XX },
/* 21 */ { "andV", 0, Ev, Gv, XX },
/* 22 */ { "andB", 0, Gb, Eb, XX },
@ -2314,10 +2313,10 @@ static BxDisasmOpcodeInfo_t BxDisasmOpcodes[256*2] = {
/* 9D */ { "popfD", 0, XX, XX, XX },
/* 9E */ { "sahf", 0, XX, XX, XX },
/* 9F */ { "lahf", 0, XX, XX, XX },
/* A0 */ { "movB", 0, AL, Ob, XX },
/* A1 */ { "movV", 0, eAX, Ov, XX },
/* A2 */ { "movB", 0, Ob, AL, XX },
/* A3 */ { "movV", 0, Ov, eAX, XX },
/* A0 */ { "movB", 0, AL, OX, XX },
/* A1 */ { "movV", 0, eAX, OX, XX },
/* A2 */ { "movB", 0, OX, AL, XX },
/* A3 */ { "movV", 0, OX, eAX, XX },
/* A4 */ { "movsb", 0, Yb, Xb, XX },
/* A5 */ { "movsS", 0, Yv, Xv, XX },
/* A6 */ { "cmpsb", 0, Yb, Xb, XX },
@ -2572,16 +2571,16 @@ static BxDisasmOpcodeInfo_t BxDisasmOpcodes[256*2] = {
/* 0F 9D */ { "setnlB", 0, Eb, XX, XX },
/* 0F 9E */ { "setleB", 0, Eb, XX, XX },
/* 0F 9F */ { "setnleB", 0, Eb, XX, XX },
/* 0F A0 */ { "push", 0, FS, XX, XX },
/* 0F A1 */ { "pop", 0, FS, XX, XX },
/* 0F A0 */ { "pushV", 0, FS, XX, XX },
/* 0F A1 */ { "popV", 0, FS, XX, XX },
/* 0F A2 */ { "cpuid", 0, XX, XX, XX },
/* 0F A3 */ { "btV", 0, Ev, Gv, XX },
/* 0F A4 */ { "shldV", 0, Ev, Gv, Ib },
/* 0F A5 */ { "shldV", 0, Ev, Gv, CL },
/* 0F A6 */ { INVALID },
/* 0F A7 */ { INVALID },
/* 0F A8 */ { "push", 0, GS, XX, XX },
/* 0F A9 */ { "pop", 0, GS, XX, XX },
/* 0F A8 */ { "pushV", 0, GS, XX, XX },
/* 0F A9 */ { "popV", 0, GS, XX, XX },
/* 0F AA */ { "rsm", 0, XX, XX, XX },
/* 0F AB */ { "btsV", 0, Ev, Gv, XX },
/* 0F AC */ { "shrdV", 0, Ev, Gv, Ib },

8
bochs/disasm/disasm.h
View File

@ -160,11 +160,11 @@ private:
private:
bx_bool i32bit_opsize;
bx_bool i32bit_addrsize;
bx_bool os_32;
bx_bool as_32;
#if BX_DISASM_SUPPORT_X86_64
bx_bool i64bit_opsize;
bx_bool i64bit_addrsize;
bx_bool os_64;
bx_bool as_64;
#endif
Bit8u modrm, mod, nnn, rm;

4
bochs/disasm/resolve.cc
View File

@ -6,7 +6,7 @@ void disassembler::decode_modrm()
modrm = fetch_byte();
BX_DECODE_MODRM(modrm, mod, nnn, rm);
if (i32bit_addrsize)
if (as_32)
{
/* use 32bit addressing modes. orthogonal base & index registers,
scaling available, etc. */
@ -194,7 +194,7 @@ void disassembler::print_datasize(unsigned mode)
dis_sprintf("dword ptr ");
break;
case V_SIZE:
if (i32bit_opsize)
if (os_32)
dis_sprintf("dword ptr ");
else
dis_sprintf("word ptr ");

10
bochs/disasm/syntax.cc
View File

@ -210,14 +210,14 @@ void disassembler::print_disassembly_intel(const BxDisasmOpcodeInfo_t *entry)
break;
case 'S': // string
if (i32bit_opsize)
if (os_32)
dis_putc('d');
else
dis_putc('w');
break;
case 'D':
if (i32bit_opsize)
if (os_32)
dis_putc('d');
break;
@ -282,7 +282,7 @@ void disassembler::print_disassembly_att(const BxDisasmOpcodeInfo_t *entry)
case 'S':
case 'V':
if (i32bit_opsize)
if (os_32)
dis_putc('l');
else
dis_putc('w');
@ -318,7 +318,7 @@ void disassembler::print_disassembly_att(const BxDisasmOpcodeInfo_t *entry)
dis_putc('q');
else if (entry->Op1Attr == V_SIZE)
{
if (i32bit_opsize)
if (os_32)
dis_putc('l');
else
dis_putc('w');
@ -328,7 +328,7 @@ void disassembler::print_disassembly_att(const BxDisasmOpcodeInfo_t *entry)
break;
case 'D':
if (i32bit_opsize)
if (os_32)
dis_putc('l');
break;