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Fixed two calls to dtranslate_linear in paging.cc to use

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BX_READ not 0.  BX_READ was 10.  While I was at it, I did
change BX_{READ,WRITE,RW} to {0,1,2} rather than {10,11,12}
in case that helps optimize code.

There may be more paging checks we should do before changing
any state, to avoid receiving a page fault in the middle.
I put some extra comments in there.
This commit is contained in:
Kevin Lawton 2002-09-09 21:59:10 +00:00
parent 293cbc01ea
commit 59d00a46a3
2 changed files with 27 additions and 21 deletions
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8
bochs/bochs.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bochs.h,v 1.90 2002-09-09 07:19:23 cbothamy Exp $
// $Id: bochs.h,v 1.91 2002-09-09 21:59:09 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -492,9 +492,9 @@ extern bx_debug_t bx_dbg;
#define BX_FLOPPY_LAST 15 // last one
#define BX_READ 10
#define BX_WRITE 11
#define BX_RW 12
#define BX_READ 0
#define BX_WRITE 1
#define BX_RW 2

40
bochs/cpu/tasking.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: tasking.cc,v 1.10 2002-09-09 19:48:58 uid94540 Exp $
// $Id: tasking.cc,v 1.11 2002-09-09 21:59:10 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -164,7 +164,8 @@ BX_CPU_C::task_switch(bx_selector_t *tss_selector,
// The following checks are made before calling task_switch(), for
// JMP & CALL only. These checks are NOT made for exceptions, interrupts, & IRET
// JMP & CALL only. These checks are NOT made for exceptions,
// interrupts, & IRET.
//
// 1) TSS DPL must be >= CPL
// 2) TSS DPL must be >= TSS selector RPL
@ -219,15 +220,21 @@ BX_CPU_C::task_switch(bx_selector_t *tss_selector,
// Check that old TSS, new TSS, and all segment descriptors
// used in the task switch are paged in.
if (BX_CPU_THIS_PTR cr0.pg) {
//BX_RW, BX_READ, BX_WRITE
// Old TSS
(void) dtranslate_linear(obase32, 0, /*rw*/ BX_WRITE);
(void) dtranslate_linear(obase32+old_TSS_max, 0, /*rw*/ BX_WRITE);
(void) dtranslate_linear(obase32, 0, BX_WRITE);
(void) dtranslate_linear(obase32+old_TSS_max, 0, BX_WRITE);
// New TSS
(void) dtranslate_linear(nbase32, 0, /*rw*/ 0);
(void) dtranslate_linear(nbase32+new_TSS_max, 0, /*rw*/ 0);
(void) dtranslate_linear(nbase32, 0, BX_READ);
(void) dtranslate_linear(nbase32+new_TSS_max, 0, BX_READ);
// ??? Humm, we check the new TSS region with READ above,
// but sometimes we need to write the link field in that
// region. We also sometimes update other fields, perhaps
// we need to WRITE check them here also, so that we keep
// the written state consistent (ie, we don't encounter a
// page fault in the middle).
//
// ??? fix RW above
// ??? touch old/new TSS descriptors here when necessary.
}
@ -316,13 +323,12 @@ if (ss_descriptor.u.segment.d_b && (tss_descriptor->type<9)) {
// effect on Busy bit of old task
if ( (source==BX_TASK_FROM_JUMP) || (source==BX_TASK_FROM_IRET) ) {
// Bit is cleared
access_linear(BX_CPU_THIS_PTR gdtr.base +
BX_CPU_THIS_PTR tr.selector.index*8 + 4,
4, 0, BX_READ, &temp32);
Bit32u laddr;
laddr = BX_CPU_THIS_PTR gdtr.base +
(BX_CPU_THIS_PTR tr.selector.index<<3) + 4;
access_linear(laddr, 4, 0, BX_READ, &temp32);
temp32 &= ~0x00000200;
access_linear(BX_CPU_THIS_PTR gdtr.base +
BX_CPU_THIS_PTR tr.selector.index*8 + 4,
4, 0, BX_WRITE, &temp32);
access_linear(laddr, 4, 0, BX_WRITE, &temp32);
}
@ -432,11 +438,11 @@ if ( source==BX_TASK_FROM_CALL_OR_INT ) {
if ( (source==BX_TASK_FROM_JUMP) || (source==BX_TASK_FROM_CALL_OR_INT) ) {
// set the new task's busy bit
access_linear(BX_CPU_THIS_PTR gdtr.base + tss_selector->index*8 + 4,
4, 0, BX_READ, &dword2);
Bit32u laddr;
laddr = BX_CPU_THIS_PTR gdtr.base + (tss_selector->index<<3) + 4;
access_linear(laddr, 4, 0, BX_READ, &dword2);
dword2 |= 0x00000200;
access_linear(BX_CPU_THIS_PTR gdtr.base + tss_selector->index*8 + 4,
4, 0, BX_WRITE, &dword2);
access_linear(laddr, 4, 0, BX_WRITE, &dword2);
}