- calculate horizontal and vertical frequency from CRT for more accurate retrace
timing (TODO: length of retrace signals should be calculated, too)
This commit is contained in:
Volker Ruppert
parent
2f5be164d2
commit
55854afa86
@ -156,6 +156,8 @@ void bx_vgacore_c::init_standard_vga(void)
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BX_VGA_THIS s.plane_shift = 16;
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BX_VGA_THIS s.dac_shift = 2;
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BX_VGA_THIS s.last_bpp = 8;
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BX_VGA_THIS s.htotal_usec = 31;
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BX_VGA_THIS s.vtotal_usec = 14285;
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BX_VGA_THIS s.max_xres = 800;
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BX_VGA_THIS s.max_yres = 600;
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@ -378,6 +380,7 @@ void bx_vgacore_c::after_restore_state(void)
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BX_VGA_THIS s.last_xres = BX_VGA_THIS s.max_xres;
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BX_VGA_THIS s.last_yres = BX_VGA_THIS s.max_yres;
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BX_VGA_THIS redraw_area(0, 0, BX_VGA_THIS s.max_xres, BX_VGA_THIS s.max_yres);
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BX_VGA_THIS calculate_retrace_timing();
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BX_VGA_THIS update();
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bx_gui->flush();
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}
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@ -421,6 +424,24 @@ void bx_vgacore_c::determine_screen_dimensions(unsigned *piHeight, unsigned *piW
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}
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}
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void bx_vgacore_c::calculate_retrace_timing()
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{
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Bit32u dot_clock[4] = {25175000, 28322000, 25175000, 25175000};
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Bit32u htotal, clock, cwidth, vtotal, hfreq, vfreq;
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htotal = BX_VGA_THIS s.CRTC.reg[0] + 5;
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htotal <<= BX_VGA_THIS s.x_dotclockdiv2;
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cwidth = ((BX_VGA_THIS s.sequencer.reg1 & 0x01) == 1) ? 8 : 9;
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clock = dot_clock[BX_VGA_THIS s.misc_output.clock_select];
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hfreq = clock / (htotal * cwidth);
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BX_VGA_THIS s.htotal_usec = 1000000 / hfreq;
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vtotal = BX_VGA_THIS s.CRTC.reg[6] + ((BX_VGA_THIS s.CRTC.reg[7] & 0x01) << 8) +
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((BX_VGA_THIS s.CRTC.reg[7] & 0x20) << 4) + 2;
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vfreq = hfreq / vtotal;
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BX_VGA_THIS s.vtotal_usec = 1000000 / vfreq;
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BX_DEBUG(("hfreq = %.1f kHz / vfreq = %d Hz", ((double)hfreq / 1000), vfreq));
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}
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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@ -432,9 +453,8 @@ Bit32u bx_vgacore_c::read_handler(void *this_ptr, Bit32u address, unsigned io_le
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Bit32u bx_vgacore_c::read(Bit32u address, unsigned io_len)
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{
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bx_bool horiz_retrace = 0, vert_retrace = 0;
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Bit64u usec;
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Bit16u ret16, vertres;
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Bit64u display_usec, line_usec;
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Bit16u ret16;
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Bit8u retval;
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#if defined(VGA_TRACE_FEATURE)
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@ -475,27 +495,16 @@ Bit32u bx_vgacore_c::read(Bit32u address, unsigned io_len)
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// 1 = display is not in the display mode; either the
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// horizontal or vertical retrace period is active
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// using 72 Hz vertical frequency
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usec = bx_pc_system.time_usec();
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switch ((BX_VGA_THIS s.misc_output.vert_sync_pol << 1) | BX_VGA_THIS s.misc_output.horiz_sync_pol)
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{
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case 0: vertres = 200; break;
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case 1: vertres = 400; break;
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case 2: vertres = 350; break;
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default: vertres = 480; break;
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}
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if ((usec % 13888) < 70) {
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vert_retrace = 1;
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}
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if ((usec % (13888 / vertres)) == 0) {
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horiz_retrace = 1;
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}
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retval = 0;
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if (horiz_retrace || vert_retrace)
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retval = 0x01;
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if (vert_retrace)
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retval |= 0x08;
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display_usec = bx_pc_system.time_usec() % BX_VGA_THIS s.vtotal_usec;
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if (display_usec < 70) {
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retval |= 0x09;
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} else {
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line_usec = display_usec % BX_VGA_THIS s.htotal_usec;
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if (line_usec == 0) {
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retval |= 0x01;
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}
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}
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/* reading this port resets the flip-flop to address mode */
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BX_VGA_THIS s.attribute_ctrl.flip_flop = 0;
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@ -930,6 +939,7 @@ void bx_vgacore_c::write(Bit32u address, Bit32u value, unsigned io_len, bx_bool
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BX_DEBUG((" vert_sync_pol = %u",
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(unsigned) BX_VGA_THIS s.misc_output.vert_sync_pol));
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#endif
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calculate_retrace_timing();
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break;
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case 0x03c3: // VGA enable
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@ -974,6 +984,7 @@ void bx_vgacore_c::write(Bit32u address, Bit32u value, unsigned io_len, bx_bool
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}
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BX_VGA_THIS s.sequencer.reg1 = value & 0x3d;
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BX_VGA_THIS s.x_dotclockdiv2 = ((value & 0x08) > 0);
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calculate_retrace_timing();
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break;
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case 2: /* sequencer: map mask register */
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BX_VGA_THIS s.sequencer.map_mask = (value & 0x0f);
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@ -1182,12 +1193,17 @@ void bx_vgacore_c::write(Bit32u address, Bit32u value, unsigned io_len, bx_bool
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if (value != BX_VGA_THIS s.CRTC.reg[BX_VGA_THIS s.CRTC.address]) {
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BX_VGA_THIS s.CRTC.reg[BX_VGA_THIS s.CRTC.address] = value;
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switch (BX_VGA_THIS s.CRTC.address) {
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case 0x00:
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case 0x06:
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calculate_retrace_timing();
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break;
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case 0x07:
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BX_VGA_THIS s.vertical_display_end &= 0xff;
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if (BX_VGA_THIS s.CRTC.reg[0x07] & 0x02) BX_VGA_THIS s.vertical_display_end |= 0x100;
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if (BX_VGA_THIS s.CRTC.reg[0x07] & 0x40) BX_VGA_THIS s.vertical_display_end |= 0x200;
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BX_VGA_THIS s.line_compare &= 0x2ff;
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if (BX_VGA_THIS s.CRTC.reg[0x07] & 0x10) BX_VGA_THIS s.line_compare |= 0x100;
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calculate_retrace_timing();
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needs_update = 1;
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break;
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case 0x08:
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@ -1223,6 +1239,7 @@ void bx_vgacore_c::write(Bit32u address, Bit32u value, unsigned io_len, bx_bool
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case 0x12:
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BX_VGA_THIS s.vertical_display_end &= 0x300;
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BX_VGA_THIS s.vertical_display_end |= BX_VGA_THIS s.CRTC.reg[0x12];
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calculate_retrace_timing();
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break;
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case 0x13:
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case 0x14:
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@ -1344,6 +1361,7 @@ void bx_vgacore_c::update(void)
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static unsigned cs_counter = 1;
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static bx_bool cs_visible = 0;
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bx_bool cs_toggle = 0;
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Bit64u display_usec;
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cs_counter--;
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/* no screen update necessary */
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@ -1369,10 +1387,11 @@ void bx_vgacore_c::update(void)
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|| (BX_VGA_THIS s.sequencer.reg1 & 0x20))
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return;
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/* skip screen update if the vertical retrace is in progress
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(using 72 Hz vertical frequency) */
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if ((bx_pc_system.time_usec() % 13888) < 70)
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/* skip screen update if the vertical retrace is in progress */
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display_usec = bx_pc_system.time_usec() % BX_VGA_THIS s.vtotal_usec;
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if (display_usec < 70) {
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return;
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}
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// fields that effect the way video memory is serialized into screen output:
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// GRAPHICS CONTROLLER:
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@ -96,6 +96,7 @@ protected:
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bx_bool get_dac_palette(Bit8u **palette_ptr, Bit8u shift);
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void update(void);
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void determine_screen_dimensions(unsigned *piHeight, unsigned *piWidth);
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void calculate_retrace_timing(void);
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struct {
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struct {
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@ -204,13 +205,19 @@ protected:
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Bit16u charmap_address;
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bx_bool x_dotclockdiv2;
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bx_bool y_doublescan;
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// h/v retrace timing
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Bit32u htotal_usec;
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Bit32u vtotal_usec;
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// shift values for extensions
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Bit8u plane_shift;
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Bit32u plane_offset;
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Bit8u dac_shift;
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// last active resolution and bpp
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Bit16u last_xres;
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Bit16u last_yres;
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Bit8u last_bpp;
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Bit8u last_msl;
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// maximum resolution and number of tiles
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Bit16u max_xres;
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Bit16u max_yres;
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Bit16u num_x_tiles;
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