- fixed the vga memory read/write functions in text mode
- text mode cursor feature added
This commit is contained in:
Volker Ruppert
parent
5b13f74356
commit
5427df8b36
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: vga.cc,v 1.18 2001-10-03 13:10:38 bdenney Exp $
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// $Id: vga.cc,v 1.19 2001-12-13 18:34:30 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -665,7 +665,7 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, Boolean no_log)
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{
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unsigned i;
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Boolean prev_video_enabled;
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Bit8u prev_memory_mapping;
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Bit8u charmap1, charmap2, prev_memory_mapping;
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Boolean prev_graphics_alpha, prev_chain_odd_even;
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Boolean needs_update;
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@ -906,6 +906,11 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01;
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break;
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case 3: /* sequencer: character map select register */
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BX_VGA_THIS s.sequencer.char_map_select = value;
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charmap1 = value & 0x13;
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if (charmap1 > 3) charmap1 = (charmap1 & 3) + 4;
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charmap2 = (value & 0x2C) >> 2;
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if (charmap2 > 3) charmap2 = (charmap2 & 3) + 4;
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BX_INFO(("char map select: #1=%d / #2=%d (unused)", charmap1, charmap2));
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break;
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case 4: /* sequencer: memory mode register */
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BX_VGA_THIS s.sequencer.extended_mem = (value >> 1) & 0x01;
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@ -1305,6 +1310,7 @@ bx_vga_c::update(void)
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else { // text mode
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unsigned long start_address;
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unsigned long cursor_address, cursor_x, cursor_y;
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Bit16u cursor_state;
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switch (BX_VGA_THIS s.graphics_ctrl.memory_mapping) {
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@ -1323,12 +1329,13 @@ bx_vga_c::update(void)
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cursor_x = ((cursor_address - start_address)/2) % 80;
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cursor_y = ((cursor_address - start_address)/2) / 80;
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}
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cursor_state = (bx_vga.s.CRTC.reg[0x0a] << 8) | bx_vga.s.CRTC.reg[0x0b];
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bx_gui.text_update(BX_VGA_THIS s.text_snapshot,
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&BX_VGA_THIS s.vga_memory[0x10000 + start_address],
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cursor_x, cursor_y, 25);
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&BX_VGA_THIS s.vga_memory[start_address],
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cursor_x, cursor_y, cursor_state, 25);
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// screen updated, copy new VGA memory contents into text snapshot
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memcpy(BX_VGA_THIS s.text_snapshot,
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&BX_VGA_THIS s.vga_memory[0x10000 + start_address],
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&BX_VGA_THIS s.vga_memory[start_address],
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2*80*25);
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BX_VGA_THIS s.vga_mem_updated = 0;
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break;
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@ -1358,12 +1365,13 @@ bx_vga_c::update(void)
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cursor_x = ((cursor_address - start_address)/2) % 80;
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cursor_y = ((cursor_address - start_address)/2) / 80;
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}
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cursor_state = (bx_vga.s.CRTC.reg[0x0a] << 8) | bx_vga.s.CRTC.reg[0x0b];
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bx_gui.text_update(BX_VGA_THIS s.text_snapshot,
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&BX_VGA_THIS s.vga_memory[0x18000 + start_address],
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cursor_x, cursor_y, rows);
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&BX_VGA_THIS s.vga_memory[start_address],
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cursor_x, cursor_y, cursor_state, rows);
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// screen updated, copy new VGA memory contents into text snapshot
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memcpy(BX_VGA_THIS s.text_snapshot,
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&BX_VGA_THIS s.vga_memory[0x18000 + start_address],
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&BX_VGA_THIS s.vga_memory[start_address],
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2*80*rows);
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BX_VGA_THIS s.vga_mem_updated = 0;
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break;
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@ -1421,64 +1429,76 @@ bx_vga_c::mem_read(Bit32u addr)
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return(0xff);
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// addr between 0xA0000 and 0xAFFFF
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offset = addr - 0xA0000;
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if ( BX_VGA_THIS s.sequencer.chain_four ) {
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offset = addr - 0xA0000;
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// Mode 13h: 320 x 200 256 color mode: chained pixel representation
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return( BX_VGA_THIS s.vga_memory[(offset & ~0x03) + (offset % 4)*65536] );
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}
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/* addr between 0xA0000 and 0xAFFFF */
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switch (BX_VGA_THIS s.graphics_ctrl.read_mode) {
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case 0: /* read mode 0 */
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offset = addr - 0xA0000;
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BX_VGA_THIS s.graphics_ctrl.latch[0] = BX_VGA_THIS s.vga_memory[ offset];
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BX_VGA_THIS s.graphics_ctrl.latch[1] = BX_VGA_THIS s.vga_memory[1*65536 + offset];
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BX_VGA_THIS s.graphics_ctrl.latch[2] = BX_VGA_THIS s.vga_memory[2*65536 + offset];
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BX_VGA_THIS s.graphics_ctrl.latch[3] = BX_VGA_THIS s.vga_memory[3*65536 + offset];
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return(BX_VGA_THIS s.graphics_ctrl.latch[BX_VGA_THIS s.graphics_ctrl.read_map_select]);
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break;
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case 1: /* read mode 1 */
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{
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Bit8u color_compare, color_dont_care;
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Bit8u latch0, latch1, latch2, latch3, retval, pixel_val;
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color_compare = BX_VGA_THIS s.graphics_ctrl.color_compare & 0x0f;
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color_dont_care = BX_VGA_THIS s.graphics_ctrl.color_dont_care & 0x0f;
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offset = addr - 0xA0000;
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latch0 = BX_VGA_THIS s.graphics_ctrl.latch[0] = BX_VGA_THIS s.vga_memory[ offset];
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latch1 = BX_VGA_THIS s.graphics_ctrl.latch[1] = BX_VGA_THIS s.vga_memory[1*65536 + offset];
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latch2 = BX_VGA_THIS s.graphics_ctrl.latch[2] = BX_VGA_THIS s.vga_memory[2*65536 + offset];
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latch3 = BX_VGA_THIS s.graphics_ctrl.latch[3] = BX_VGA_THIS s.vga_memory[3*65536 + offset];
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retval = 0;
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for (unsigned b=0; b<8; b++) {
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pixel_val =
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((latch0 << 0) & 0x01) |
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((latch1 << 1) & 0x02) |
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((latch2 << 2) & 0x04) |
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((latch3 << 3) & 0x08);
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latch0 >>= 1;
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latch1 >>= 1;
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latch2 >>= 1;
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latch3 >>= 1;
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if ( (pixel_val & color_dont_care) ==
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(color_compare & color_dont_care) )
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retval |= (1 << b);
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}
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return(retval);
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}
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break;
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default:
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BX_PANIC(("vga_mem_read: read mode %u ?",
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(unsigned) BX_VGA_THIS s.graphics_ctrl.read_mode));
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return(0);
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}
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return(0);
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}
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else {
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return(BX_VGA_THIS s.vga_memory[addr - 0xa0000]);
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switch (BX_VGA_THIS s.graphics_ctrl.memory_mapping) {
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case 1: // 0xA0000 .. 0xAFFFF
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if (addr > 0xAFFFF) return(0xff);
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offset = addr - 0xA0000;
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break;
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case 2: // 0xB0000 .. 0xB7FFF
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if ((addr < 0xB0000) | (addr > 0xB7FFF)) return(0xff);
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offset = addr - 0xB0000;
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break;
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case 3: // 0xB8000 .. 0xBFFFF
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if (addr < 0xB8000) return(0xff);
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offset = addr - 0xB8000;
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break;
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default: // 0xA0000 .. 0xBFFFF
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offset = addr - 0xA0000;
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}
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if (BX_VGA_THIS s.graphics_ctrl.memory_mapping != 1)
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return(BX_VGA_THIS s.vga_memory[offset]);
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}
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/* addr between 0xA0000 and 0xAFFFF */
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switch (BX_VGA_THIS s.graphics_ctrl.read_mode) {
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case 0: /* read mode 0 */
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BX_VGA_THIS s.graphics_ctrl.latch[0] = BX_VGA_THIS s.vga_memory[ offset];
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BX_VGA_THIS s.graphics_ctrl.latch[1] = BX_VGA_THIS s.vga_memory[1*65536 + offset];
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BX_VGA_THIS s.graphics_ctrl.latch[2] = BX_VGA_THIS s.vga_memory[2*65536 + offset];
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BX_VGA_THIS s.graphics_ctrl.latch[3] = BX_VGA_THIS s.vga_memory[3*65536 + offset];
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return(BX_VGA_THIS s.graphics_ctrl.latch[BX_VGA_THIS s.graphics_ctrl.read_map_select]);
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break;
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case 1: /* read mode 1 */
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{
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Bit8u color_compare, color_dont_care;
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Bit8u latch0, latch1, latch2, latch3, retval, pixel_val;
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color_compare = BX_VGA_THIS s.graphics_ctrl.color_compare & 0x0f;
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color_dont_care = BX_VGA_THIS s.graphics_ctrl.color_dont_care & 0x0f;
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latch0 = BX_VGA_THIS s.graphics_ctrl.latch[0] = BX_VGA_THIS s.vga_memory[ offset];
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latch1 = BX_VGA_THIS s.graphics_ctrl.latch[1] = BX_VGA_THIS s.vga_memory[1*65536 + offset];
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latch2 = BX_VGA_THIS s.graphics_ctrl.latch[2] = BX_VGA_THIS s.vga_memory[2*65536 + offset];
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latch3 = BX_VGA_THIS s.graphics_ctrl.latch[3] = BX_VGA_THIS s.vga_memory[3*65536 + offset];
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retval = 0;
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for (unsigned b=0; b<8; b++) {
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pixel_val =
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((latch0 << 0) & 0x01) |
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((latch1 << 1) & 0x02) |
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((latch2 << 2) & 0x04) |
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((latch3 << 3) & 0x08);
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latch0 >>= 1;
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latch1 >>= 1;
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latch2 >>= 1;
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latch3 >>= 1;
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if ( (pixel_val & color_dont_care) ==
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(color_compare & color_dont_care) )
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retval |= (1 << b);
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}
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return(retval);
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}
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break;
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default:
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return(0);
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}
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}
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@ -1537,198 +1557,218 @@ bx_vga_c::mem_write(Bit32u addr, Bit8u value)
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return;
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}
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/* addr between 0xA0000 and 0xAFFFF */
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switch (BX_VGA_THIS s.graphics_ctrl.write_mode) {
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Bit8u and_mask, bitmask;
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Bit8u set_reset_b[4];
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unsigned i, b;
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}
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else {
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switch (BX_VGA_THIS s.graphics_ctrl.memory_mapping) {
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case 1: // 0xA0000 .. 0xAFFFF
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if (addr > 0xAFFFF) return;
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offset = addr - 0xA0000;
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break;
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case 2: // 0xB0000 .. 0xB7FFF
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if ((addr < 0xB0000) | (addr > 0xB7FFF)) return;
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offset = addr - 0xB0000;
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break;
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case 3: // 0xB8000 .. 0xBFFFF
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if (addr < 0xB8000) return;
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offset = addr - 0xB8000;
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break;
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default: // 0xA0000 .. 0xBFFFF
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offset = addr - 0xA0000;
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}
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if (BX_VGA_THIS s.graphics_ctrl.memory_mapping != 1) {
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BX_VGA_THIS s.vga_memory[offset] = value;
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BX_VGA_THIS s.vga_mem_updated = 1;
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return;
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}
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}
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case 0: /* write mode 0 */
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/* perform rotate on CPU data in case its needed */
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value = (value >> BX_VGA_THIS s.graphics_ctrl.data_rotate) |
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(value << (8 - BX_VGA_THIS s.graphics_ctrl.data_rotate));
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bitmask = BX_VGA_THIS s.graphics_ctrl.bitmask;
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for (i=0; i<4; i++ ) {
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new_val[i] = 0;
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}
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set_reset_b[0] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 0) & 0x01;
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set_reset_b[1] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 1) & 0x01;
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set_reset_b[2] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 2) & 0x01;
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set_reset_b[3] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 3) & 0x01;
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and_mask = 1;
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for (b=0; b<8; b++) {
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if (bitmask & 0x01) { /* bit-mask bit set, perform op */
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for (i=0; i<4; i++) {
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/* derive bit from set/reset register */
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if ( (BX_VGA_THIS s.graphics_ctrl.enable_set_reset >> i) & 0x01 ) {
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new_bit = (set_reset_b[i] << b);
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}
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/* derive bit from rotated CPU data */
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else {
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new_bit = (value & and_mask);
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}
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switch (BX_VGA_THIS s.graphics_ctrl.raster_op) {
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case 0: /* replace */
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new_val[i] |= new_bit;
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break;
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case 1: /* AND with latch data */
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new_val[i] |=
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(new_bit & (BX_VGA_THIS s.graphics_ctrl.latch[i] & and_mask));
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break;
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case 2: /* OR with latch data */
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new_val[i] |=
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(new_bit | (BX_VGA_THIS s.graphics_ctrl.latch[i] & and_mask));
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break;
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case 3: /* XOR with latch data */
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new_val[i] |=
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(new_bit ^ (BX_VGA_THIS s.graphics_ctrl.latch[i] & and_mask));
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break;
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default:
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BX_PANIC(("vga_mem_write: write mode 0: op = %u",
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(unsigned) BX_VGA_THIS s.graphics_ctrl.raster_op));
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}
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/* addr between 0xA0000 and 0xAFFFF */
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switch (BX_VGA_THIS s.graphics_ctrl.write_mode) {
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Bit8u and_mask, bitmask;
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Bit8u set_reset_b[4];
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unsigned i, b;
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case 0: /* write mode 0 */
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/* perform rotate on CPU data in case its needed */
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value = (value >> BX_VGA_THIS s.graphics_ctrl.data_rotate) |
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(value << (8 - BX_VGA_THIS s.graphics_ctrl.data_rotate));
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bitmask = BX_VGA_THIS s.graphics_ctrl.bitmask;
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for (i=0; i<4; i++ ) {
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new_val[i] = 0;
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}
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set_reset_b[0] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 0) & 0x01;
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set_reset_b[1] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 1) & 0x01;
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set_reset_b[2] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 2) & 0x01;
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set_reset_b[3] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 3) & 0x01;
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and_mask = 1;
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for (b=0; b<8; b++) {
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if (bitmask & 0x01) { /* bit-mask bit set, perform op */
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for (i=0; i<4; i++) {
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/* derive bit from set/reset register */
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if ( (BX_VGA_THIS s.graphics_ctrl.enable_set_reset >> i) & 0x01 ) {
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new_bit = (set_reset_b[i] << b);
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}
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/* derive bit from rotated CPU data */
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else {
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new_bit = (value & and_mask);
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}
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}
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else { /* bit-mask bit clear, pass data thru from latch */
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new_val[0] |= (BX_VGA_THIS s.graphics_ctrl.latch[0] & and_mask);
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new_val[1] |= (BX_VGA_THIS s.graphics_ctrl.latch[1] & and_mask);
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new_val[2] |= (BX_VGA_THIS s.graphics_ctrl.latch[2] & and_mask);
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new_val[3] |= (BX_VGA_THIS s.graphics_ctrl.latch[3] & and_mask);
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}
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bitmask >>= 1;
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and_mask <<= 1;
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}
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break;
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case 1: /* write mode 1 */
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for (i=0; i<4; i++ ) {
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new_val[i] = BX_VGA_THIS s.graphics_ctrl.latch[i];
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}
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break;
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case 2: /* write mode 2 */
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if (BX_VGA_THIS s.graphics_ctrl.raster_op)
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BX_PANIC(("vga_mem_write: write mode 2: op = %u",
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(unsigned) BX_VGA_THIS s.graphics_ctrl.raster_op));
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bitmask = BX_VGA_THIS s.graphics_ctrl.bitmask;
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for (i=0; i<4; i++ ) {
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new_val[i] = 0;
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}
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cpu_data_b[0] = (value >> 0) & 0x01;
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cpu_data_b[1] = (value >> 1) & 0x01;
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cpu_data_b[2] = (value >> 2) & 0x01;
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cpu_data_b[3] = (value >> 3) & 0x01;
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and_mask = 1;
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for (b=0; b<8; b++) {
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if (bitmask & 0x01) { /* bit-mask bit set, perform op */
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switch (BX_VGA_THIS s.graphics_ctrl.raster_op) {
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case 0: /* replace: write cpu data unmodified */
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new_val[0] |= cpu_data_b[0] << b;
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new_val[1] |= cpu_data_b[1] << b;
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new_val[2] |= cpu_data_b[2] << b;
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new_val[3] |= cpu_data_b[3] << b;
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case 0: /* replace */
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new_val[i] |= new_bit;
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break;
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case 1: /* AND with latch data */
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new_val[i] |=
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(new_bit & (BX_VGA_THIS s.graphics_ctrl.latch[i] & and_mask));
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break;
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case 2: /* OR with latch data */
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new_val[i] |=
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(new_bit | (BX_VGA_THIS s.graphics_ctrl.latch[i] & and_mask));
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break;
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case 3: /* XOR with latch data */
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new_val[i] |=
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(new_bit ^ (BX_VGA_THIS s.graphics_ctrl.latch[i] & and_mask));
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break;
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case 1: /* AND */
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case 2: /* OR */
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case 3: /* XOR */
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default:
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BX_PANIC(("vga_mem_write: raster_op = %u?",
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BX_PANIC(("vga_mem_write: write mode 0: op = %u",
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(unsigned) BX_VGA_THIS s.graphics_ctrl.raster_op));
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||||
}
|
||||
}
|
||||
else { /* bit-mask bit clear, pass data thru from latch */
|
||||
new_val[0] |= (BX_VGA_THIS s.graphics_ctrl.latch[0] & and_mask);
|
||||
new_val[1] |= (BX_VGA_THIS s.graphics_ctrl.latch[1] & and_mask);
|
||||
new_val[2] |= (BX_VGA_THIS s.graphics_ctrl.latch[2] & and_mask);
|
||||
new_val[3] |= (BX_VGA_THIS s.graphics_ctrl.latch[3] & and_mask);
|
||||
}
|
||||
bitmask >>= 1;
|
||||
and_mask <<= 1;
|
||||
}
|
||||
break;
|
||||
else { /* bit-mask bit clear, pass data thru from latch */
|
||||
new_val[0] |= (BX_VGA_THIS s.graphics_ctrl.latch[0] & and_mask);
|
||||
new_val[1] |= (BX_VGA_THIS s.graphics_ctrl.latch[1] & and_mask);
|
||||
new_val[2] |= (BX_VGA_THIS s.graphics_ctrl.latch[2] & and_mask);
|
||||
new_val[3] |= (BX_VGA_THIS s.graphics_ctrl.latch[3] & and_mask);
|
||||
}
|
||||
bitmask >>= 1;
|
||||
and_mask <<= 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case 3: /* write mode 3 */
|
||||
/* perform rotate on CPU data */
|
||||
value = (value >> BX_VGA_THIS s.graphics_ctrl.data_rotate) |
|
||||
(value << (8 - BX_VGA_THIS s.graphics_ctrl.data_rotate));
|
||||
bitmask = (value & BX_VGA_THIS s.graphics_ctrl.bitmask);
|
||||
for (i=0; i<4; i++ ) {
|
||||
new_val[i] = 0;
|
||||
case 1: /* write mode 1 */
|
||||
for (i=0; i<4; i++ ) {
|
||||
new_val[i] = BX_VGA_THIS s.graphics_ctrl.latch[i];
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: /* write mode 2 */
|
||||
if (BX_VGA_THIS s.graphics_ctrl.raster_op)
|
||||
BX_PANIC(("vga_mem_write: write mode 2: op = %u",
|
||||
(unsigned) BX_VGA_THIS s.graphics_ctrl.raster_op));
|
||||
bitmask = BX_VGA_THIS s.graphics_ctrl.bitmask;
|
||||
for (i=0; i<4; i++ ) {
|
||||
new_val[i] = 0;
|
||||
}
|
||||
cpu_data_b[0] = (value >> 0) & 0x01;
|
||||
cpu_data_b[1] = (value >> 1) & 0x01;
|
||||
cpu_data_b[2] = (value >> 2) & 0x01;
|
||||
cpu_data_b[3] = (value >> 3) & 0x01;
|
||||
and_mask = 1;
|
||||
for (b=0; b<8; b++) {
|
||||
if (bitmask & 0x01) { /* bit-mask bit set, perform op */
|
||||
switch (BX_VGA_THIS s.graphics_ctrl.raster_op) {
|
||||
case 0: /* replace: write cpu data unmodified */
|
||||
new_val[0] |= cpu_data_b[0] << b;
|
||||
new_val[1] |= cpu_data_b[1] << b;
|
||||
new_val[2] |= cpu_data_b[2] << b;
|
||||
new_val[3] |= cpu_data_b[3] << b;
|
||||
break;
|
||||
case 1: /* AND */
|
||||
case 2: /* OR */
|
||||
case 3: /* XOR */
|
||||
default:
|
||||
BX_PANIC(("vga_mem_write: raster_op = %u?",
|
||||
(unsigned) BX_VGA_THIS s.graphics_ctrl.raster_op));
|
||||
}
|
||||
}
|
||||
set_reset_b[0] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 0) & 0x01;
|
||||
set_reset_b[1] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 1) & 0x01;
|
||||
set_reset_b[2] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 2) & 0x01;
|
||||
set_reset_b[3] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 3) & 0x01;
|
||||
and_mask = 1;
|
||||
for (b=0; b<8; b++) {
|
||||
if (bitmask & 0x01) { /* bit-mask bit set, perform op */
|
||||
for (i=0; i<4; i++) {
|
||||
/* derive bit from set/reset register */
|
||||
/* (mch) I can't find any justification for this... */
|
||||
if ( /* (mch) */ 1 || ((BX_VGA_THIS s.graphics_ctrl.enable_set_reset >> i) & 0x01 )) {
|
||||
// (mch) My guess is that the function select logic should go here
|
||||
switch (BX_VGA_THIS s.graphics_ctrl.raster_op) {
|
||||
case 0: // write
|
||||
new_val[i] |= (set_reset_b[i] << b);
|
||||
break;
|
||||
case 1: // AND
|
||||
new_val[i] |= (set_reset_b[i] << b) &
|
||||
(BX_VGA_THIS s.graphics_ctrl.latch[i] & (1 << b));
|
||||
break;
|
||||
case 2: // OR
|
||||
new_val[i] |= (set_reset_b[i] << b) |
|
||||
(BX_VGA_THIS s.graphics_ctrl.latch[i] & (1 << b));
|
||||
break;
|
||||
case 3: // XOR
|
||||
new_val[i] |= (set_reset_b[i] << b) ^
|
||||
(BX_VGA_THIS s.graphics_ctrl.latch[i] & (1 << b));
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* derive bit from rotated CPU data */
|
||||
else {
|
||||
new_val[i] |= (value & and_mask);
|
||||
else { /* bit-mask bit clear, pass data thru from latch */
|
||||
new_val[0] |= (BX_VGA_THIS s.graphics_ctrl.latch[0] & and_mask);
|
||||
new_val[1] |= (BX_VGA_THIS s.graphics_ctrl.latch[1] & and_mask);
|
||||
new_val[2] |= (BX_VGA_THIS s.graphics_ctrl.latch[2] & and_mask);
|
||||
new_val[3] |= (BX_VGA_THIS s.graphics_ctrl.latch[3] & and_mask);
|
||||
}
|
||||
bitmask >>= 1;
|
||||
and_mask <<= 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case 3: /* write mode 3 */
|
||||
/* perform rotate on CPU data */
|
||||
value = (value >> BX_VGA_THIS s.graphics_ctrl.data_rotate) |
|
||||
(value << (8 - BX_VGA_THIS s.graphics_ctrl.data_rotate));
|
||||
bitmask = (value & BX_VGA_THIS s.graphics_ctrl.bitmask);
|
||||
for (i=0; i<4; i++ ) {
|
||||
new_val[i] = 0;
|
||||
}
|
||||
set_reset_b[0] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 0) & 0x01;
|
||||
set_reset_b[1] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 1) & 0x01;
|
||||
set_reset_b[2] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 2) & 0x01;
|
||||
set_reset_b[3] = (BX_VGA_THIS s.graphics_ctrl.set_reset >> 3) & 0x01;
|
||||
and_mask = 1;
|
||||
for (b=0; b<8; b++) {
|
||||
if (bitmask & 0x01) { /* bit-mask bit set, perform op */
|
||||
for (i=0; i<4; i++) {
|
||||
/* derive bit from set/reset register */
|
||||
/* (mch) I can't find any justification for this... */
|
||||
if ( /* (mch) */ 1 || ((BX_VGA_THIS s.graphics_ctrl.enable_set_reset >> i) & 0x01 )) {
|
||||
// (mch) My guess is that the function select logic should go here
|
||||
switch (BX_VGA_THIS s.graphics_ctrl.raster_op) {
|
||||
case 0: // write
|
||||
new_val[i] |= (set_reset_b[i] << b);
|
||||
break;
|
||||
case 1: // AND
|
||||
new_val[i] |= ((set_reset_b[i] << b) &
|
||||
BX_VGA_THIS s.graphics_ctrl.latch[i] & (1 << b));
|
||||
break;
|
||||
case 2: // OR
|
||||
new_val[i] |= (set_reset_b[i] << b) |
|
||||
(BX_VGA_THIS s.graphics_ctrl.latch[i] & (1 << b));
|
||||
break;
|
||||
case 3: // XOR
|
||||
new_val[i] |= ((set_reset_b[i] << b) ^
|
||||
BX_VGA_THIS s.graphics_ctrl.latch[i] & (1 << b));
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* derive bit from rotated CPU data */
|
||||
else {
|
||||
new_val[i] |= (value & and_mask);
|
||||
}
|
||||
}
|
||||
else { /* bit-mask bit clear, pass data thru from latch */
|
||||
new_val[0] |= (BX_VGA_THIS s.graphics_ctrl.latch[0] & and_mask);
|
||||
new_val[1] |= (BX_VGA_THIS s.graphics_ctrl.latch[1] & and_mask);
|
||||
new_val[2] |= (BX_VGA_THIS s.graphics_ctrl.latch[2] & and_mask);
|
||||
new_val[3] |= (BX_VGA_THIS s.graphics_ctrl.latch[3] & and_mask);
|
||||
}
|
||||
bitmask >>= 1;
|
||||
and_mask <<= 1;
|
||||
}
|
||||
break;
|
||||
else { /* bit-mask bit clear, pass data thru from latch */
|
||||
new_val[0] |= (BX_VGA_THIS s.graphics_ctrl.latch[0] & and_mask);
|
||||
new_val[1] |= (BX_VGA_THIS s.graphics_ctrl.latch[1] & and_mask);
|
||||
new_val[2] |= (BX_VGA_THIS s.graphics_ctrl.latch[2] & and_mask);
|
||||
new_val[3] |= (BX_VGA_THIS s.graphics_ctrl.latch[3] & and_mask);
|
||||
}
|
||||
bitmask >>= 1;
|
||||
and_mask <<= 1;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
BX_PANIC(("vga_mem_write: write mode %u ?",
|
||||
(unsigned) BX_VGA_THIS s.graphics_ctrl.write_mode));
|
||||
}
|
||||
|
||||
if (BX_VGA_THIS s.sequencer.map_mask & 0x0f) {
|
||||
BX_VGA_THIS s.vga_mem_updated = 1;
|
||||
if (BX_VGA_THIS s.sequencer.map_mask_bit[0])
|
||||
BX_VGA_THIS s.vga_memory[0*65536 + offset] = new_val[0];
|
||||
if (BX_VGA_THIS s.sequencer.map_mask_bit[1])
|
||||
BX_VGA_THIS s.vga_memory[1*65536 + offset] = new_val[1];
|
||||
if (BX_VGA_THIS s.sequencer.map_mask_bit[2])
|
||||
BX_VGA_THIS s.vga_memory[2*65536 + offset] = new_val[2];
|
||||
if (BX_VGA_THIS s.sequencer.map_mask_bit[3])
|
||||
BX_VGA_THIS s.vga_memory[3*65536 + offset] = new_val[3];
|
||||
{
|
||||
unsigned x_tileno, y_tileno;
|
||||
|
||||
x_tileno = (offset % (BX_VGA_THIS s.scan_bits/8)) / (X_TILESIZE / 8);
|
||||
y_tileno = (offset / (BX_VGA_THIS s.scan_bits/8)) / Y_TILESIZE;
|
||||
BX_VGA_THIS s.vga_tile_updated[x_tileno][y_tileno] = 1;
|
||||
}
|
||||
}
|
||||
default:
|
||||
BX_PANIC(("vga_mem_write: write mode %u ?",
|
||||
(unsigned) BX_VGA_THIS s.graphics_ctrl.write_mode));
|
||||
}
|
||||
else {
|
||||
BX_VGA_THIS s.vga_memory[addr - 0xa0000] = value;
|
||||
|
||||
if (BX_VGA_THIS s.sequencer.map_mask & 0x0f) {
|
||||
BX_VGA_THIS s.vga_mem_updated = 1;
|
||||
if (BX_VGA_THIS s.sequencer.map_mask_bit[0])
|
||||
BX_VGA_THIS s.vga_memory[0*65536 + offset] = new_val[0];
|
||||
if (BX_VGA_THIS s.sequencer.map_mask_bit[1])
|
||||
BX_VGA_THIS s.vga_memory[1*65536 + offset] = new_val[1];
|
||||
if (BX_VGA_THIS s.sequencer.map_mask_bit[2])
|
||||
BX_VGA_THIS s.vga_memory[2*65536 + offset] = new_val[2];
|
||||
if (BX_VGA_THIS s.sequencer.map_mask_bit[3])
|
||||
BX_VGA_THIS s.vga_memory[3*65536 + offset] = new_val[3];
|
||||
|
||||
unsigned x_tileno, y_tileno;
|
||||
|
||||
x_tileno = (offset % (BX_VGA_THIS s.scan_bits/8)) / (X_TILESIZE / 8);
|
||||
y_tileno = (offset / (BX_VGA_THIS s.scan_bits/8)) / Y_TILESIZE;
|
||||
BX_VGA_THIS s.vga_tile_updated[x_tileno][y_tileno] = 1;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user