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- patch updated

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This commit is contained in:
Volker Ruppert 2004-08-01 08:25:26 +00:00
parent a7eef1d526
commit 4fc67c3aac
1 changed files with 387 additions and 174 deletions
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561
bochs/patches/patch.svga_cirrus
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@ -37,7 +37,7 @@ Detailed description:
modified to avoid confliction.
modified access rights from private to protected.
Changes by vruppert (June 25th 2004)
Changes by vruppert (Aug 1st 2004)
- updated for current CVS
- PCI host bridge is now a core plugin and initialized earlier
- plugin version works now (CLGD54xx included in the vga plugin)
@ -50,18 +50,19 @@ Detailed description:
- some vga register now support 16-bit reads
- a bunch of updates sent by suzu295@melu.jp
- ported write mode 4 + 5 and some bufixes from cirrus vga in qemu
- hardware cursor support for sdl added
Patch was created with:
diff -urN
Apply patch to what version:
cvs snapshot on June 25th 2004
cvs snapshot on Aug 1st 2004
Instructions:
To patch, go to main bochs directory.
Type "patch -p0 < THIS_PATCH_FILE".
----------------------------------------------------------------------
diff -urN ../bochs/config.h.in ./config.h.in
--- ../bochs/config.h.in 2004-06-18 19:34:06.000000000 +0200
+++ ./config.h.in 2004-06-19 07:50:43.000000000 +0200
--- ../bochs/config.h.in 2004-07-30 13:49:31.000000000 +0200
+++ ./config.h.in 2004-07-30 15:34:13.000000000 +0200
@@ -266,6 +266,7 @@
#define BX_USE_NE2K_SMF 1 // NE2K
#define BX_USE_EFI_SMF 1 // External FPU IRQ
@ -118,6 +119,109 @@ diff -urN ../bochs/config.h.in ./config.h.in
// Promise VLBIDE DC2300 Support
#define BX_PDC20230C_VLBIDE_SUPPORT 0
diff -urN ../bochs/gui/gui.h ./gui/gui.h
--- ../bochs/gui/gui.h 2004-04-09 17:04:53.000000000 +0200
+++ ./gui/gui.h 2004-07-31 19:22:19.000000000 +0200
@@ -56,6 +56,7 @@
unsigned long cursor_x, unsigned long cursor_y,
bx_vga_tminfo_t tm_info, unsigned rows) = 0;
virtual void graphics_tile_update(Bit8u *snapshot, unsigned x, unsigned y) = 0;
+ virtual void hardware_cursor_update(Bit8u *snapshot, unsigned x, unsigned y, unsigned xs, unsigned ys) {};
virtual void handle_events(void) = 0;
virtual void flush(void) = 0;
virtual void clear_screen(void) = 0;
diff -urN ../bochs/gui/sdl.cc ./gui/sdl.cc
--- ../bochs/gui/sdl.cc 2004-06-20 07:58:08.000000000 +0200
+++ ./gui/sdl.cc 2004-08-01 10:18:35.000000000 +0200
@@ -49,6 +49,7 @@
DECLARE_GUI_VIRTUAL_METHODS()
virtual void set_display_mode (disp_mode_t newmode);
virtual void statusbar_setitem(int element, bx_bool active);
+ virtual void hardware_cursor_update(Bit8u *snapshot, unsigned x, unsigned y, unsigned xs, unsigned ys);
};
// declare one instance of the gui object and call macro to insert the
@@ -102,7 +103,7 @@
static unsigned vga_bpp=8;
unsigned tilewidth, tileheight;
unsigned char menufont[256][8];
-Uint32 palette[256];
+Uint32 palette[258];
Uint32 headerbar_fg, headerbar_bg;
Bit8u old_mousebuttons=0, new_mousebuttons=0;
int old_mousex=0, new_mousex=0;
@@ -704,6 +705,62 @@
}
}
+ void
+bx_sdl_gui_c::hardware_cursor_update(
+ Bit8u *snapshot,
+ unsigned x,
+ unsigned y,
+ unsigned xs,
+ unsigned ys)
+{
+ Uint32 *buf, disp;
+ Uint32 *buf_row;
+ Bit8u *snap_row;
+ int i,j,hwc_x;
+
+ if( sdl_screen )
+ {
+ disp = sdl_screen->pitch/4;
+ buf = (Uint32 *)sdl_screen->pixels + (headerbar_height+y)*disp + x;
+ }
+ else
+ {
+ disp = sdl_fullscreen->pitch/4;
+ buf = (Uint32 *)sdl_fullscreen->pixels + y*disp + x;
+ }
+
+ hwc_x = xs;
+ if ((x + xs) > res_x) xs = res_x - x;
+ if ((y + ys) > res_y) ys = res_y - y;
+ i = ys;
+
+ do
+ {
+ buf_row = buf;
+ snap_row = snapshot;
+ j = xs;
+ do
+ {
+ switch (*snapshot++)
+ {
+ case 1:
+ *buf++ ^= 0xffffffff;
+ break;
+ case 2:
+ *buf++ = palette[0x100];
+ break;
+ case 3:
+ *buf++ = palette[0x101];
+ break;
+ default:
+ buf++;
+ }
+ } while( --j );
+ buf = buf_row + disp;
+ snapshot = snap_row + hwc_x;
+ } while( --i);
+}
+
static Bit32u sdl_sym_to_bx_key (SDLKey sym)
{
switch (sym)
@@ -1092,7 +1149,7 @@
unsigned char palgreen = green & 0xFF;
unsigned char palblue = blue & 0xFF;
- if( index > 255 ) return 0;
+ if( index > 257 ) return 0;
if( sdl_screen )
palette[index] = SDL_MapRGB( sdl_screen->format, palred, palgreen, palblue );
diff -urN ../bochs/iodev/Makefile.in ./iodev/Makefile.in
--- ../bochs/iodev/Makefile.in 2004-02-18 19:29:33.000000000 +0100
+++ ./iodev/Makefile.in 2004-06-06 13:09:58.000000000 +0200
@ -160,8 +264,8 @@ diff -urN ../bochs/iodev/Makefile.in ./iodev/Makefile.in
../plugin.h ../extplugin.h ../ltdl.h ../gui/gui.h ../gui/textconfig.h \
diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
--- ../bochs/iodev/svga_cirrus.cc 1970-01-01 01:00:00.000000000 +0100
+++ ./iodev/svga_cirrus.cc 2004-07-25 19:41:07.000000000 +0200
@@ -0,0 +1,2859 @@
+++ ./iodev/svga_cirrus.cc 2004-08-01 09:51:09.000000000 +0200
@@ -0,0 +1,2959 @@
+//
+// limited PCI/ISA CLGD5446 support.
+//
@ -183,7 +287,6 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+// - painting minimal region
+// - transparent compare.
+// - some bitblt functions
+// - hardware cursor(need palette 256/257 to implement it)
+// - ???
+//
+// some codes are copied from vga.cc and modified.
@ -229,6 +332,8 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+#define ID_CLGD5446 (0x2E<<2)
+
+// sequencer 0x07
+#define CIRRUS_SR7_BPP_VGA 0x00
+#define CIRRUS_SR7_BPP_SVGA 0x01
+#define CIRRUS_SR7_BPP_MASK 0x0e
+#define CIRRUS_SR7_BPP_8 0x00
+#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
@ -279,6 +384,7 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+#define CIRRUS_BLT_START 0x02
+#define CIRRUS_BLT_RESET 0x04
+#define CIRRUS_BLT_FIFOUSED 0x10
+#define CIRRUS_BLT_AUTOSTART 0x80
+
+// control 0x32
+#define CIRRUS_ROP_0 0x00
@ -424,13 +530,17 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ svga_timer_handler);
+
+ // initialize SVGA stuffs.
+#if BX_SUPPORT_SVGA_CIRRUS_PCI
+ BX_CIRRUS_THIS pci_enabled = DEV_is_pci_device("cirrus");
+#else
+ BX_CIRRUS_THIS pci_enabled = 0;
+#endif
+ BX_CIRRUS_THIS svga_init_members();
+#if BX_SUPPORT_SVGA_CIRRUS_PCI
+ if (BX_CIRRUS_THIS pci_enabled) {
+ BX_CIRRUS_THIS svga_init_pcihandlers();
+ }
+#endif // BX_SUPPORT_SVGA_CIRRUS_PCI
+#endif
+}
+
+ void
@ -453,7 +563,6 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ BX_CIRRUS_THIS hidden_dac.lockindex = 0;
+ BX_CIRRUS_THIS hidden_dac.data = 0x00;
+
+ BX_CIRRUS_THIS svga_draw_special = false;
+ BX_CIRRUS_THIS svga_unlock_special = false;
+ BX_CIRRUS_THIS svga_needs_update_tile = true;
+ BX_CIRRUS_THIS svga_needs_update_dispentire = true;
@ -469,6 +578,9 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+
+ svga_reset_bitblt();
+
+ BX_CIRRUS_THIS hw_cursor.x = 0;
+ BX_CIRRUS_THIS hw_cursor.y = 0;
+
+ // memory allocation.
+ BX_CIRRUS_THIS vidmem = new Bit8u[CIRRUS_VIDEO_MEMORY_BYTES];
+ BX_CIRRUS_THIS tilemem = new Bit8u[X_TILESIZE * Y_TILESIZE * 4];
@ -543,7 +655,7 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+{
+ unsigned xi, yi, x1, y1, xmax, ymax;
+
+ if (!BX_CIRRUS_THIS is_svgadraw()) {
+ if ((BX_CIRRUS_THIS sequencer.reg[0x07] & 0x01) == CIRRUS_SR7_BPP_VGA) {
+ BX_CIRRUS_THIS bx_vga_c::redraw_area(x0,y0,width,height);
+ return;
+ }
@ -641,58 +753,55 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ Bit8u
+bx_svga_cirrus_c::mem_read(Bit32u addr)
+{
+ if (!BX_CIRRUS_THIS is_svgadraw()) {
+ if ((BX_CIRRUS_THIS sequencer.reg[0x07] & 0x01) == CIRRUS_SR7_BPP_VGA) {
+ return BX_CIRRUS_THIS bx_vga_c::mem_read(addr);
+ }
+
+#if BX_SUPPORT_SVGA_CIRRUS_PCI
+ if ((addr >= BX_CIRRUS_THIS pci_memaddr) &&
+ (addr < (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256))) {
+ Bit8u *ptr;
+ Bit32u offset;
+ if (BX_CIRRUS_THIS pci_enabled) {
+ if ((addr >= BX_CIRRUS_THIS pci_memaddr) &&
+ (addr < (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256))) {
+ Bit8u *ptr;
+ Bit32u offset;
+
+ // video-to-cpu BLT
+ if (BX_CIRRUS_THIS bitblt.memdst_needed != 0) {
+ ptr = BX_CIRRUS_THIS bitblt.memdst_ptr;
+ if (ptr != BX_CIRRUS_THIS bitblt.memdst_endptr) {
+ BX_CIRRUS_THIS bitblt.memdst_ptr ++;
+ return *ptr;
+ }
+ if (!svga_asyncbitblt_next()) {
+ // video-to-cpu BLT
+ if (BX_CIRRUS_THIS bitblt.memdst_needed != 0) {
+ ptr = BX_CIRRUS_THIS bitblt.memdst_ptr;
+ BX_CIRRUS_THIS bitblt.memdst_ptr ++;
+ return *ptr;
+ if (ptr != BX_CIRRUS_THIS bitblt.memdst_endptr) {
+ BX_CIRRUS_THIS bitblt.memdst_ptr ++;
+ return *ptr;
+ }
+ if (!svga_asyncbitblt_next()) {
+ ptr = BX_CIRRUS_THIS bitblt.memdst_ptr;
+ BX_CIRRUS_THIS bitblt.memdst_ptr ++;
+ return *ptr;
+ }
+ }
+
+ ptr = BX_CIRRUS_THIS vidmem;
+ offset = addr - BX_CIRRUS_THIS pci_memaddr;
+ if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x14) == 0x14) {
+ offset <<= 4;
+ } else if (BX_CIRRUS_THIS control.reg[0x0b] & 0x02) {
+ offset <<= 3;
+ }
+ return *(ptr + offset);
+ }
+ else if ((addr >= (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256)) &&
+ (addr < (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE))) {
+ Bit32u offset = addr - (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256);
+ BX_PANIC(("mem_read: offset = 0x%02x", offset));
+ }
+ else if ((addr >= BX_CIRRUS_THIS pci_mmioaddr) &&
+ ptr = BX_CIRRUS_THIS vidmem;
+ offset = addr - BX_CIRRUS_THIS pci_memaddr;
+ if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x14) == 0x14) {
+ offset <<= 4;
+ } else if (BX_CIRRUS_THIS control.reg[0x0b] & 0x02) {
+ offset <<= 3;
+ }
+ return *(ptr + offset);
+ } else if ((addr >= (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256)) &&
+ (addr < (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE))) {
+ Bit32u offset = addr - (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256);
+ return svga_mmio_blt_read(offset & 0xff);
+ } else if ((addr >= BX_CIRRUS_THIS pci_mmioaddr) &&
+ (addr < (BX_CIRRUS_THIS pci_mmioaddr + CIRRUS_PNPMMIO_SIZE))) {
+ Bit32u offset;
+ Bit32u offset;
+
+ offset = addr - BX_CIRRUS_THIS pci_mmioaddr;
+ if ((BX_CIRRUS_THIS sequencer.reg[0x17] & 0x44) == 0x04) {
+ offset = addr - BX_CIRRUS_THIS pci_mmioaddr;
+ if (offset >= 0x100) {
+ return svga_mmio_blt_read(offset - 0x100);
+ }
+ else {
+ } else {
+ return svga_mmio_vga_read(offset);
+ }
+ }
+ }
+ }
+#endif // BX_SUPPORT_SVGA_CIRRUS_PCI
+
+ if (addr >= 0xA0000 && addr <= 0xAFFFF)
@ -725,7 +834,7 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ } else if (BX_CIRRUS_THIS control.reg[0x0b] & 0x02) {
+ offset <<= 3;
+ }
+ offset &= (CIRRUS_VIDEO_MEMORY_BYTES -1);
+ offset &= (CIRRUS_VIDEO_MEMORY_BYTES - 1);
+ return *(BX_CIRRUS_THIS vidmem + offset);
+ }
+ else {
@ -775,68 +884,65 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ void
+bx_svga_cirrus_c::mem_write(Bit32u addr, Bit8u value)
+{
+ if (!BX_CIRRUS_THIS is_svgadraw()) {
+ if ((BX_CIRRUS_THIS sequencer.reg[0x07] & 0x01) == CIRRUS_SR7_BPP_VGA) {
+ BX_CIRRUS_THIS bx_vga_c::mem_write(addr,value);
+ return;
+ }
+
+#if BX_SUPPORT_SVGA_CIRRUS_PCI
+ if ((addr >= BX_CIRRUS_THIS pci_memaddr) &&
+ (addr < (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256))) {
+ Bit32u offset;
+ Bit8u mode;
+ if (BX_CIRRUS_THIS pci_enabled) {
+ if ((addr >= BX_CIRRUS_THIS pci_memaddr) &&
+ (addr < (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256))) {
+ Bit32u offset;
+ Bit8u mode;
+
+ // cpu-to-video BLT
+ if (BX_CIRRUS_THIS bitblt.memsrc_needed != 0) {
+ *(BX_CIRRUS_THIS bitblt.memsrc_ptr)++ = (value);
+ if (bitblt.memsrc_ptr == BX_CIRRUS_THIS bitblt.memsrc_endptr) {
+ svga_asyncbitblt_next();
+ // cpu-to-video BLT
+ if (BX_CIRRUS_THIS bitblt.memsrc_needed != 0) {
+ *(BX_CIRRUS_THIS bitblt.memsrc_ptr)++ = (value);
+ if (bitblt.memsrc_ptr == BX_CIRRUS_THIS bitblt.memsrc_endptr) {
+ svga_asyncbitblt_next();
+ }
+ return;
+ return;
+ }
+
+ offset = addr - BX_CIRRUS_THIS pci_memaddr;
+ // BX_DEBUG(("write offset 0x%08x,value 0x%02x",offset,value));
+ if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x14) == 0x14) {
+ offset <<= 4;
+ } else if (BX_CIRRUS_THIS control.reg[0x0b] & 0x02) {
+ offset <<= 3;
+ }
+ mode = BX_CIRRUS_THIS control.reg[0x05] & 0x07;
+ if ((mode < 4) || (mode > 5) || ((BX_CIRRUS_THIS control.reg[0x0b] & 0x4) == 0)) {
+ *(BX_CIRRUS_THIS vidmem + offset) = value;
+ } else {
+ if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x14) != 0x14) {
+ mem_write_mode4and5_8bpp(mode, offset, value);
+ offset = addr - BX_CIRRUS_THIS pci_memaddr;
+ // BX_DEBUG(("write offset 0x%08x,value 0x%02x",offset,value));
+ if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x14) == 0x14) {
+ offset <<= 4;
+ } else if (BX_CIRRUS_THIS control.reg[0x0b] & 0x02) {
+ offset <<= 3;
+ }
+ mode = BX_CIRRUS_THIS control.reg[0x05] & 0x07;
+ if ((mode < 4) || (mode > 5) || ((BX_CIRRUS_THIS control.reg[0x0b] & 0x4) == 0)) {
+ *(BX_CIRRUS_THIS vidmem + offset) = value;
+ } else {
+ mem_write_mode4and5_16bpp(mode, offset, value);
+ if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x14) != 0x14) {
+ mem_write_mode4and5_8bpp(mode, offset, value);
+ } else {
+ mem_write_mode4and5_16bpp(mode, offset, value);
+ }
+ }
+ }
+ BX_CIRRUS_THIS svga_needs_update_dispentire = true;
+ return;
+ }
+ else if ((addr >= (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256)) &&
+ (addr < (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE))) {
+ Bit32u offset = addr - (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256);
+ BX_PANIC(("mem_write: offset = 0x%02x", offset));
+ }
+ else if ((addr >= BX_CIRRUS_THIS pci_mmioaddr) &&
+ (addr < (BX_CIRRUS_THIS pci_mmioaddr + CIRRUS_PNPMMIO_SIZE))) {
+ // memory-mapped I/O.
+ Bit32u offset;
+ BX_CIRRUS_THIS svga_needs_update_dispentire = true;
+ return;
+ } else if ((addr >= (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256)) &&
+ (addr < (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE))) {
+ Bit32u offset = addr - (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE - 256);
+ svga_mmio_blt_write(offset & 0xff, value);
+ } else if ((addr >= BX_CIRRUS_THIS pci_mmioaddr) &&
+ (addr < (BX_CIRRUS_THIS pci_mmioaddr + CIRRUS_PNPMMIO_SIZE))) {
+ // memory-mapped I/O.
+ Bit32u offset;
+
+ // BX_DEBUG(("write mmio 0x%08x",addr));
+ offset = addr - BX_CIRRUS_THIS pci_mmioaddr;
+ if ((BX_CIRRUS_THIS sequencer.reg[0x17] & 0x44) == 0x04) {
+ // BX_DEBUG(("write mmio 0x%08x",addr));
+ offset = addr - BX_CIRRUS_THIS pci_mmioaddr;
+ if (offset >= 0x100) {
+ svga_mmio_blt_write(offset - 0x100, value);
+ }
+ else {
+ } else {
+ svga_mmio_vga_write(offset,value);
+ }
+ return;
+ }
+ return;
+ }
+ }
+#endif // BX_SUPPORT_SVGA_CIRRUS_PCI
+
+ if (addr >= 0xA0000 && addr <= 0xAFFFF) {
@ -862,7 +968,7 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ } else if (BX_CIRRUS_THIS control.reg[0x0b] & 0x02) {
+ offset <<= 3;
+ }
+ offset &= (CIRRUS_VIDEO_MEMORY_BYTES -1);
+ offset &= (CIRRUS_VIDEO_MEMORY_BYTES - 1);
+ mode = BX_CIRRUS_THIS control.reg[0x05] & 0x07;
+ if ((mode < 4) || (mode > 5) || ((BX_CIRRUS_THIS control.reg[0x0b] & 0x4) == 0)) {
+ *(BX_CIRRUS_THIS vidmem + offset) = value;
@ -935,7 +1041,7 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ if ((io_len == 2) && ((address & 1) == 0)) {
+ Bit32u value;
+ value = (Bit32u)SVGA_READ(address,1);
+ value = (Bit32u)SVGA_READ(address+1,1) << 8;
+ value |= (Bit32u)SVGA_READ(address+1,1) << 8;
+ return value;
+ }
+
@ -1058,7 +1164,6 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ }
+ break;
+ case 0x03c9: /* PEL Data Register, hidden pel colors 00..0F */
+ // update palette - FIXME !!!
+ BX_CIRRUS_THIS svga_needs_update_dispentire = true;
+
+ if (BX_CIRRUS_THIS sequencer.reg[0x12] & CIRRUS_CURSOR_HIDDENPEL) {
@ -1067,6 +1172,15 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ BX_CIRRUS_THIS hidden_dac.palette[index] = value;
+ BX_CIRRUS_THIS s.pel.write_data_cycle ++;
+ if (BX_CIRRUS_THIS s.pel.write_data_cycle >= 3) {
+ if ((BX_CIRRUS_THIS s.pel.write_data_register & 0xf) == 0x0) {
+ bx_gui->palette_change(0x100, BX_CIRRUS_THIS hidden_dac.palette[0x0]<<2,
+ BX_CIRRUS_THIS hidden_dac.palette[0x1]<<2,
+ BX_CIRRUS_THIS hidden_dac.palette[0x2]<<2);
+ } else if ((BX_CIRRUS_THIS s.pel.write_data_register & 0xf) == 0xf) {
+ bx_gui->palette_change(0x101, BX_CIRRUS_THIS hidden_dac.palette[0xf*3]<<2,
+ BX_CIRRUS_THIS hidden_dac.palette[0xf*3+1]<<2,
+ BX_CIRRUS_THIS hidden_dac.palette[0xf*3+2]<<2);
+ }
+ BX_CIRRUS_THIS s.pel.write_data_cycle = 0;
+ BX_CIRRUS_THIS s.pel.write_data_register++;
+ }
@ -1131,9 +1245,7 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ width = (BX_CIRRUS_THIS crtc.reg[0x01] + 1) * 8;
+ iBpp = 8;
+ iDispBpp = 4;
+ if ((BX_CIRRUS_THIS sequencer.reg[0x07] & 0x1) == 0) {
+ BX_CIRRUS_THIS svga_draw_special = false;
+ } else {
+ if ((BX_CIRRUS_THIS sequencer.reg[0x07] & 0x1) == CIRRUS_SR7_BPP_SVGA) {
+ switch (BX_CIRRUS_THIS sequencer.reg[0x07] & CIRRUS_SR7_BPP_MASK) {
+ case CIRRUS_SR7_BPP_8:
+ iBpp = 8;
@ -1156,7 +1268,6 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ BX_PANIC(("unknown bpp - seqencer.reg[0x07] = %02x",BX_CIRRUS_THIS sequencer.reg[0x07]));
+ break;
+ }
+ BX_CIRRUS_THIS svga_draw_special = true;
+ }
+ BX_INFO(("switched to %u x %u x %u",width,iHeight,iDispBpp));
+
@ -1179,21 +1290,18 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ return;
+ }
+
+ if (BX_CIRRUS_THIS svga_needs_update_mode) {
+ svga_modeupdate();
+ }
+
+ if (!BX_CIRRUS_THIS is_svgadraw()) {
+ if ((BX_CIRRUS_THIS sequencer.reg[0x07] & 0x01) == CIRRUS_SR7_BPP_VGA) {
+ if (BX_CIRRUS_THIS svga_needs_update_mode) {
+// BX_CIRRUS_THIS bx_vga_c::determine_screen_dimensions(&height, &width);
+// bx_gui->dimension_update(width, height);
+// BX_CIRRUS_THIS bx_vga_c::redraw_area(0,0,width,height);
+ BX_CIRRUS_THIS s.vga_mem_updated = 1;
+ BX_CIRRUS_THIS svga_needs_update_mode = false;
+ }
+ BX_CIRRUS_THIS bx_vga_c::update();
+ return;
+ } else {
+ if (BX_CIRRUS_THIS svga_needs_update_mode) {
+ svga_modeupdate();
+ }
+ }
+
+ width = BX_CIRRUS_THIS svga_xres;
+ height = BX_CIRRUS_THIS svga_yres;
@ -1315,6 +1423,81 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ BX_PANIC(("unknown bpp %u",(unsigned)BX_CIRRUS_THIS svga_bpp));
+ break;
+ }
+
+ // hardware cursor
+ Bit8u *hwc_plane0 = BX_CIRRUS_THIS vidmem + CIRRUS_VIDEO_MEMORY_BYTES - 16 * 1024;
+ Bit8u *hwc_plane1;
+ Bit8u hwc_size, hwc_size_y, hwc_offset_y, hwc_b0, hwc_b1;
+
+ if (BX_CIRRUS_THIS sequencer.reg[0x12] & CIRRUS_CURSOR_SHOW) {
+ if (BX_CIRRUS_THIS sequencer.reg[0x12] & CIRRUS_CURSOR_LARGE) {
+ hwc_size = 64;
+ hwc_plane0 += (BX_CIRRUS_THIS sequencer.reg[0x13] & 0x3c) * 256;
+ hwc_plane1 = hwc_plane0 + 8;
+ hwc_offset_y = 16;
+ } else {
+ hwc_size = 32;
+ hwc_plane0 += (BX_CIRRUS_THIS sequencer.reg[0x13] & 0x3f) * 256;
+ hwc_plane1 = hwc_plane0 + 128;
+ hwc_offset_y = 4;
+ }
+ if ((unsigned)(BX_CIRRUS_THIS hw_cursor.y + hwc_size) > BX_CIRRUS_THIS svga_yres) {
+ hwc_size_y = BX_CIRRUS_THIS svga_yres - BX_CIRRUS_THIS hw_cursor.y;
+ } else {
+ hwc_size_y = hwc_size;
+ }
+
+ for (yc=0; yc<hwc_size_y; yc++) {
+ for (xc=0; xc<hwc_size; xc++) {
+ hwc_b0 = (hwc_plane0[yc*hwc_offset_y + (xc>>3)] >> (7 - (xc & 0x7))) & 0x1;
+ hwc_b1 = (hwc_plane1[yc*hwc_offset_y + (xc>>3)] >> (7 - (xc & 0x7))) & 0x1;
+ BX_CIRRUS_THIS hw_cursor.tile[yc*hwc_size + xc] = hwc_b0 | (hwc_b1 << 1);
+ }
+ }
+ bx_gui->hardware_cursor_update(BX_CIRRUS_THIS hw_cursor.tile, BX_CIRRUS_THIS hw_cursor.x,
+ BX_CIRRUS_THIS hw_cursor.y, hwc_size, hwc_size_y);
+ }
+}
+
+ void
+bx_svga_cirrus_c::update_bank_ptr(Bit8u bank_index)
+{
+ unsigned offset;
+ unsigned limit;
+
+ if (BX_CIRRUS_THIS banking_is_dual())
+ offset = BX_CIRRUS_THIS control.reg[0x09 + bank_index];
+ else
+ offset = BX_CIRRUS_THIS control.reg[0x09];
+
+ if (BX_CIRRUS_THIS banking_granularity_is_16k())
+ offset <<= 14;
+ else
+ offset <<= 12;
+
+ if (CIRRUS_VIDEO_MEMORY_BYTES <= offset) {
+ limit = 0;
+ BX_ERROR(("bank offset %08x is invalid",offset));
+ } else {
+ limit = CIRRUS_VIDEO_MEMORY_BYTES - offset;
+ }
+
+ if (!BX_CIRRUS_THIS banking_is_dual() && (bank_index != 0)) {
+ if (limit > 0x8000) {
+ offset += 0x8000;
+ limit -= 0x8000;
+ } else {
+ limit = 0;
+ }
+ }
+
+ if (limit > 0) {
+ BX_CIRRUS_THIS bank_base[bank_index] = offset;
+ BX_CIRRUS_THIS bank_limit[bank_index] = limit;
+ } else {
+ BX_CIRRUS_THIS bank_base[bank_index] = 0;
+ BX_CIRRUS_THIS bank_limit[bank_index] = 0;
+ }
+}
+
+ Bit8u
@ -1519,8 +1702,13 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ case 0x0c:
+ case 0x0d:
+ case 0x0e:
+ case 0x0f:
+ case 0x1b:
+ case 0x1c:
+ case 0x1d:
+ case 0x1e:
+ break;
+ case 0x0f:
+ return;
+ case 0x10: // cursor xpos << 5 (index & 0x3f)
+ case 0x30:
+ case 0x50:
@ -1530,6 +1718,9 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ case 0xd0:
+ case 0xf0:
+ BX_CIRRUS_THIS sequencer.reg[0x10] = value;
+ BX_CIRRUS_THIS hw_cursor.x = (value << 3) | (index >> 5);
+ // FIXME - update only the cursor region.
+ BX_CIRRUS_THIS svga_needs_update_dispentire = true;
+ break;
+ case 0x11: // cursor ypos << 5 (index & 0x3f)
+ case 0x31:
@ -1540,8 +1731,12 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ case 0xd1:
+ case 0xf1:
+ BX_CIRRUS_THIS sequencer.reg[0x11] = value;
+ BX_CIRRUS_THIS hw_cursor.y = (value << 3) | (index >> 5);
+ // FIXME - update only the cursor region.
+ BX_CIRRUS_THIS svga_needs_update_dispentire = true;
+ break;
+ case 0x12:
+ case 0x13:
+ // FIXME - update only the cursor region.
+ BX_CIRRUS_THIS svga_needs_update_dispentire = true;
+ break;
@ -1657,45 +1852,10 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ break;
+ case 0x09: // bank offset #0
+ case 0x0A: // bank offset #1
+ {
+ unsigned offset;
+ unsigned scale;
+ Bit32u new_bank_base = 0;
+ Bit32u new_bank_limit = 0;
+
+ scale = BX_CIRRUS_THIS banking_granularity_is_16k() ? 14 : 12;
+ offset = value << scale;
+ if (offset >= CIRRUS_VIDEO_MEMORY_BYTES) {
+ BX_ERROR(("bank offset %08x is invalid",offset));
+ }
+ else {
+ new_bank_base = offset;
+ new_bank_limit = CIRRUS_VIDEO_MEMORY_BYTES - offset;
+ }
+
+ if (BX_CIRRUS_THIS banking_is_dual()) {
+ BX_CIRRUS_THIS bank_base[index-0x09] = new_bank_base;
+ BX_CIRRUS_THIS bank_limit[index-0x09] = new_bank_limit;
+ }
+ else if (index == 0x09) {
+ BX_CIRRUS_THIS bank_base[0] = new_bank_base;
+ BX_CIRRUS_THIS bank_limit[0] = new_bank_limit;
+ if (new_bank_limit > 0x8000) {
+ BX_CIRRUS_THIS bank_base[1] = new_bank_base + 0x8000;
+ BX_CIRRUS_THIS bank_limit[1] = new_bank_limit - 0x8000;
+ }
+ else {
+ BX_CIRRUS_THIS bank_base[1] = 0;
+ BX_CIRRUS_THIS bank_limit[1] = 0;
+ }
+ }
+
+ }
+ break;
+ case 0x0B:
+ BX_CIRRUS_THIS control.reg[0x0B] = value;
+ svga_write_control(address,0x09,BX_CIRRUS_THIS control.reg[0x09]);
+ svga_write_control(address,0x0A,BX_CIRRUS_THIS control.reg[0x0A]);
+ BX_CIRRUS_THIS control.reg[index] = value;
+ update_bank_ptr(0);
+ update_bank_ptr(1);
+ break;
+
+ case 0x10: // BGCOLOR 0x0000ff00
@ -1731,8 +1891,11 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ case 0x29: // BLT DEST ADDR 0x00ff00
+ break;
+ case 0x2a: // BLT DEST ADDR 0x3f0000
+ value &= 0x3f;
+ break;
+ BX_CIRRUS_THIS control.reg[index] = value & 0x3f;
+ if (BX_CIRRUS_THIS control.reg[0x31] & CIRRUS_BLT_AUTOSTART) {
+ svga_bitblt();
+ }
+ return;
+ case 0x2c: // BLT SRC ADDR 0x0000ff
+ break;
+ case 0x2d: // BLT SRC ADDR 0x00ff00
@ -2301,31 +2464,42 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ goto ignoreblt;
+ }
+
+ if (BX_CIRRUS_THIS bitblt.bltmode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
+ BX_ERROR(("BLT: TRANSPARENTCOMP is not implemented"));
+ goto ignoreblt;
+ if ((BX_CIRRUS_THIS bitblt.bltmode & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
+ (BX_CIRRUS_THIS bitblt.bltmode & (CIRRUS_BLTMODE_MEMSYSDEST |
+ CIRRUS_BLTMODE_TRANSPARENTCOMP |
+ CIRRUS_BLTMODE_PATTERNCOPY |
+ CIRRUS_BLTMODE_COLOREXPAND)) ==
+ (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
+ svga_bitblt_fgcol();
+ svga_bitblt_solidfill(dstaddr);
+ } else {
+
+ if (BX_CIRRUS_THIS bitblt.bltmode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
+ BX_ERROR(("BLT: TRANSPARENTCOMP is not implemented"));
+ goto ignoreblt;
+ }
+
+ if (BX_CIRRUS_THIS bitblt.bltmode & CIRRUS_BLTMODE_BACKWARDS) {
+ BX_CIRRUS_THIS bitblt.dstpitch = -BX_CIRRUS_THIS bitblt.dstpitch;
+ BX_CIRRUS_THIS bitblt.srcpitch = -BX_CIRRUS_THIS bitblt.srcpitch;
+ BX_CIRRUS_THIS bitblt.rop_handler = svga_get_bkwd_rop_handler(BX_CIRRUS_THIS bitblt.bltrop);
+ }
+ else {
+ BX_CIRRUS_THIS bitblt.rop_handler = svga_get_fwd_rop_handler(BX_CIRRUS_THIS bitblt.bltrop);
+ }
+ if (BX_CIRRUS_THIS bitblt.bltmode & CIRRUS_BLTMODE_BACKWARDS) {
+ BX_CIRRUS_THIS bitblt.dstpitch = -BX_CIRRUS_THIS bitblt.dstpitch;
+ BX_CIRRUS_THIS bitblt.srcpitch = -BX_CIRRUS_THIS bitblt.srcpitch;
+ BX_CIRRUS_THIS bitblt.rop_handler = svga_get_bkwd_rop_handler(BX_CIRRUS_THIS bitblt.bltrop);
+ }
+ else {
+ BX_CIRRUS_THIS bitblt.rop_handler = svga_get_fwd_rop_handler(BX_CIRRUS_THIS bitblt.bltrop);
+ }
+
+ // setup bitblt engine.
+ if (BX_CIRRUS_THIS bitblt.bltmode & CIRRUS_BLTMODE_MEMSYSSRC) {
+ svga_setup_bitblt_cputovideo(dstaddr,srcaddr);
+ // setup bitblt engine.
+ if (BX_CIRRUS_THIS bitblt.bltmode & CIRRUS_BLTMODE_MEMSYSSRC) {
+ svga_setup_bitblt_cputovideo(dstaddr,srcaddr);
+ }
+ else if (BX_CIRRUS_THIS bitblt.bltmode & CIRRUS_BLTMODE_MEMSYSDEST) {
+ svga_setup_bitblt_videotocpu(dstaddr,srcaddr);
+ }
+ else {
+ svga_setup_bitblt_videotovideo(dstaddr,srcaddr);
+ }
+ return;
+ }
+ else if (BX_CIRRUS_THIS bitblt.bltmode & CIRRUS_BLTMODE_MEMSYSDEST) {
+ svga_setup_bitblt_videotocpu(dstaddr,srcaddr);
+ }
+ else {
+ svga_setup_bitblt_videotovideo(dstaddr,srcaddr);
+ }
+ return;
+
+ignoreblt:
+ svga_reset_bitblt();
@ -2810,6 +2984,36 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+ return true;
+}
+
+ void
+bx_svga_cirrus_c::svga_bitblt_fgcol()
+{
+ switch (BX_CIRRUS_THIS bitblt.pixelwidth) {
+ case 1:
+ BX_CIRRUS_THIS bitblt.fgcol = BX_CIRRUS_THIS control.shadow_reg1;
+ break;
+ case 2:
+ BX_CIRRUS_THIS bitblt.fgcol = BX_CIRRUS_THIS control.shadow_reg1 |
+ (BX_CIRRUS_THIS control.reg[0x11] << 8);
+ break;
+ case 3:
+ BX_CIRRUS_THIS bitblt.fgcol = BX_CIRRUS_THIS control.shadow_reg1 |
+ (BX_CIRRUS_THIS control.reg[0x11] << 8) | (BX_CIRRUS_THIS control.reg[0x13] << 16);
+ break;
+ default:
+ case 4:
+ BX_CIRRUS_THIS bitblt.fgcol = BX_CIRRUS_THIS control.shadow_reg1 |
+ (BX_CIRRUS_THIS control.reg[0x11] << 8) | (BX_CIRRUS_THIS control.reg[0x13] << 16) |
+ (BX_CIRRUS_THIS control.reg[0x15] << 24);
+ break;
+ }
+}
+
+ void
+bx_svga_cirrus_c::svga_bitblt_solidfill(Bit32u dstaddr)
+{
+ BX_PANIC(("SOLIDFILL is not implemented"));
+}
+
+/////////////////////////////////////////////////////////////////////////
+//
+// Raster operations.
@ -3023,8 +3227,8 @@ diff -urN ../bochs/iodev/svga_cirrus.cc ./iodev/svga_cirrus.cc
+#endif // BX_SUPPORT_SVGA_CIRRUS
diff -urN ../bochs/iodev/svga_cirrus.h ./iodev/svga_cirrus.h
--- ../bochs/iodev/svga_cirrus.h 1970-01-01 01:00:00.000000000 +0100
+++ ./iodev/svga_cirrus.h 2004-07-25 19:21:31.000000000 +0200
@@ -0,0 +1,230 @@
+++ ./iodev/svga_cirrus.h 2004-07-31 21:22:09.000000000 +0200
@@ -0,0 +1,239 @@
+#if BX_SUPPORT_SVGA_CIRRUS
+
+#if !BX_PCI_SUPPORT
@ -3053,7 +3257,7 @@ diff -urN ../bochs/iodev/svga_cirrus.h ./iodev/svga_cirrus.h
+#define CIRRUS_CONTROL_MAX 0x39
+
+// Size of internal cache memory for bitblt. (must be >= 256 and 4-byte aligned)
+#define CIRRUS_BLT_CACHESIZE 256
+#define CIRRUS_BLT_CACHESIZE (2048 * 4)
+
+#if BX_SUPPORT_SVGA_CIRRUS_PCI
+#define CIRRUS_VIDEO_MEMORY_MB 4
@ -3102,6 +3306,8 @@ diff -urN ../bochs/iodev/svga_cirrus.h ./iodev/svga_cirrus.h
+
+ BX_CIRRUS_SMF void svga_init_members();
+
+ // bank memory
+ BX_CIRRUS_SMF void update_bank_ptr(Bit8u bank_index);
+ // 0x3b4-0x3b5,0x3d4-0x3d5
+ BX_CIRRUS_SMF Bit8u svga_read_crtc(Bit32u address, unsigned index);
+ BX_CIRRUS_SMF void svga_write_crtc(Bit32u address, unsigned index, Bit8u value);
@ -3158,6 +3364,8 @@ diff -urN ../bochs/iodev/svga_cirrus.h ./iodev/svga_cirrus.h
+ BX_CIRRUS_SMF void svga_simplebitblt_memsrc();
+
+ BX_CIRRUS_SMF bx_bool svga_asyncbitblt_next();
+ BX_CIRRUS_SMF void svga_bitblt_fgcol();
+ BX_CIRRUS_SMF void svga_bitblt_solidfill(Bit32u dstaddr);
+ BX_CIRRUS_SMF bx_cirrus_bitblt_rop_t svga_get_fwd_rop_handler(Bit8u rop);
+ BX_CIRRUS_SMF bx_cirrus_bitblt_rop_t bx_svga_cirrus_c::svga_get_bkwd_rop_handler(Bit8u rop);
+
@ -3181,7 +3389,6 @@ diff -urN ../bochs/iodev/svga_cirrus.h ./iodev/svga_cirrus.h
+ Bit8u palette[48];
+ } hidden_dac; // 0x3c6
+
+ bx_bool svga_draw_special;
+ bx_bool svga_unlock_special;
+ bx_bool svga_needs_update_tile;
+ bx_bool svga_needs_update_dispentire;
@ -3228,9 +3435,15 @@ diff -urN ../bochs/iodev/svga_cirrus.h ./iodev/svga_cirrus.h
+ int memdst_needed;
+ Bit8u memsrc[CIRRUS_BLT_CACHESIZE];
+ Bit8u memdst[CIRRUS_BLT_CACHESIZE];
+ Bit32u fgcol;
+ } bitblt;
+
+ bx_bool is_svgadraw() { return svga_draw_special; }
+ struct {
+ Bit16u x;
+ Bit16u y;
+ Bit8u tile[64 * 64];
+ } hw_cursor;
+
+ bx_bool is_unlocked() { return svga_unlock_special; }
+
+ bx_bool banking_granularity_is_16k() { return !!(control.reg[0x0B] & 0x20); }