use true/false instead of 0/1 for boolean variables
cleanups in code
This commit is contained in:
Shwartsman
parent
0653c5ba75
commit
4de6c097a4
@ -114,7 +114,7 @@ void bx_biosdev_c::write(Bit32u address, Bit32u value, unsigned io_len)
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case 0x0401:
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if (value==0) {
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// The next message sent to the info port will cause a panic
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BX_BIOS_THIS s.bios_panic_flag = 1;
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BX_BIOS_THIS s.bios_panic_flag = true;
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break;
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} else if (BX_BIOS_THIS s.bios_message_i > 0) {
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// if there are bits of message in the buffer, print them as the
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@ -149,20 +149,20 @@ void bx_biosdev_c::write(Bit32u address, Bit32u value, unsigned io_len)
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} else if ((value & 0xff) == '\n') {
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BX_BIOS_THIS s.bios_message[ BX_BIOS_THIS s.bios_message_i - 1 ] = 0;
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BX_BIOS_THIS s.bios_message_i = 0;
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if (BX_BIOS_THIS s.bios_panic_flag==1)
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if (BX_BIOS_THIS s.bios_panic_flag)
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bioslog->panic("%s", BX_BIOS_THIS s.bios_message);
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else if (address==0x403)
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bioslog->ldebug("%s", BX_BIOS_THIS s.bios_message);
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else
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bioslog->info("%s", BX_BIOS_THIS s.bios_message);
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BX_BIOS_THIS s.bios_panic_flag = 0;
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BX_BIOS_THIS s.bios_panic_flag = false;
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}
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break;
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// 0x501-0x502 are used as panic ports for the vgabios
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case 0x0502:
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if (value==0) {
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BX_BIOS_THIS s.vgabios_panic_flag = 1;
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BX_BIOS_THIS s.vgabios_panic_flag = true;
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break;
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} else if (BX_BIOS_THIS s.vgabios_message_i > 0) {
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// if there are bits of message in the buffer, print them as the
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@ -196,13 +196,13 @@ void bx_biosdev_c::write(Bit32u address, Bit32u value, unsigned io_len)
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} else if ((value & 0xff) == '\n') {
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BX_BIOS_THIS s.vgabios_message[ BX_BIOS_THIS s.vgabios_message_i - 1 ] = 0;
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BX_BIOS_THIS s.vgabios_message_i = 0;
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if (BX_BIOS_THIS s.vgabios_panic_flag==1)
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if (BX_BIOS_THIS s.vgabios_panic_flag)
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vgabioslog->panic("%s", BX_BIOS_THIS s.vgabios_message);
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else if (address==0x503)
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vgabioslog->ldebug("%s", BX_BIOS_THIS s.vgabios_message);
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else
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vgabioslog->info("%s", BX_BIOS_THIS s.vgabios_message);
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BX_BIOS_THIS s.vgabios_panic_flag = 0;
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BX_BIOS_THIS s.vgabios_panic_flag = false;
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}
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break;
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@ -280,7 +280,7 @@ void bx_devices_c::init(BX_MEM_C *newmem)
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}
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for (i=0; i < BX_N_PCI_SLOTS; i++) {
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pci.slot_used[i] = 0; // no device connected
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pci.slot_used[i] = false; // no device connected
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}
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if (chipset == BX_PCI_CHIPSET_I440BX) {
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@ -634,15 +634,15 @@ bool bx_devices_c::register_irq(unsigned irq, const char *name)
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if (irq >= BX_MAX_IRQS) {
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BX_PANIC(("IO device %s registered with IRQ=%d above %u",
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name, irq, (unsigned) BX_MAX_IRQS-1));
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return 0;
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return false;
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}
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if (irq_handler_name[irq]) {
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BX_PANIC(("IRQ %u conflict, %s with %s", irq, irq_handler_name[irq], name));
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return 0;
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return false;
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}
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irq_handler_name[irq] = new char[strlen(name)+1];
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strcpy(irq_handler_name[irq], name);
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return 1;
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return true;
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}
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bool bx_devices_c::unregister_irq(unsigned irq, const char *name)
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@ -650,22 +650,21 @@ bool bx_devices_c::unregister_irq(unsigned irq, const char *name)
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if (irq >= BX_MAX_IRQS) {
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BX_PANIC(("IO device %s tried to unregister IRQ %d above %u",
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name, irq, (unsigned) BX_MAX_IRQS-1));
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return 0;
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return false;
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}
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if (!irq_handler_name[irq]) {
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BX_INFO(("IO device %s tried to unregister IRQ %d, not registered",
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name, irq));
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return 0;
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BX_INFO(("IO device %s tried to unregister IRQ %d, not registered", name, irq));
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return false;
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}
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if (strcmp(irq_handler_name[irq], name)) {
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BX_INFO(("IRQ %u not registered to %s but to %s", irq,
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name, irq_handler_name[irq]));
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return 0;
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return false;
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}
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delete [] irq_handler_name[irq];
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irq_handler_name[irq] = NULL;
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return 1;
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return true;
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}
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bool bx_devices_c::register_io_read_handler(void *this_ptr, bx_read_handler_t f,
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@ -674,16 +673,15 @@ bool bx_devices_c::register_io_read_handler(void *this_ptr, bx_read_handler_t f,
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addr &= 0xffff;
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if (!f)
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return 0;
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return false;
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/* first check if the port already has a handlers != the default handler */
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if (read_port_to_handler[addr] &&
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read_port_to_handler[addr] != &io_read_handlers) { // the default
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BX_ERROR(("IO device address conflict(read) at IO address %Xh",
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(unsigned) addr));
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BX_ERROR(("IO device address conflict(read) at IO address %Xh", (unsigned) addr));
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BX_ERROR((" conflicting devices: %s & %s",
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read_port_to_handler[addr]->handler_name, name));
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return 0;
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return false;
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}
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/* first find existing handle for function or create new one */
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@ -717,7 +715,7 @@ bool bx_devices_c::register_io_read_handler(void *this_ptr, bx_read_handler_t f,
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io_read_handler->usage_count++;
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read_port_to_handler[addr] = io_read_handler;
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return 1; // address mapped successfully
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return true; // address mapped successfully
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}
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bool bx_devices_c::register_io_write_handler(void *this_ptr, bx_write_handler_t f,
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@ -726,16 +724,15 @@ bool bx_devices_c::register_io_write_handler(void *this_ptr, bx_write_handler_t
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addr &= 0xffff;
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if (!f)
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return 0;
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return false;
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/* first check if the port already has a handlers != the default handler */
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if (write_port_to_handler[addr] &&
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write_port_to_handler[addr] != &io_write_handlers) { // the default
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BX_ERROR(("IO device address conflict(write) at IO address %Xh",
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(unsigned) addr));
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BX_ERROR(("IO device address conflict(write) at IO address %Xh", (unsigned) addr));
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BX_ERROR((" conflicting devices: %s & %s",
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write_port_to_handler[addr]->handler_name, name));
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return 0;
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return false;
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}
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/* first find existing handle for function or create new one */
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@ -769,7 +766,7 @@ bool bx_devices_c::register_io_write_handler(void *this_ptr, bx_write_handler_t
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io_write_handler->usage_count++;
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write_port_to_handler[addr] = io_write_handler;
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return 1; // address mapped successfully
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return true; // address mapped successfully
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}
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bool bx_devices_c::register_io_read_handler_range(void *this_ptr, bx_read_handler_t f,
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@ -782,23 +779,24 @@ bool bx_devices_c::register_io_read_handler_range(void *this_ptr, bx_read_handle
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if (end_addr < begin_addr) {
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BX_ERROR(("!!! end_addr < begin_addr !!!"));
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return 0;
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return false;
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}
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if (!f) {
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BX_ERROR(("!!! f == NULL !!!"));
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return 0;
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return false;
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}
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/* first check if the port already has a handlers != the default handler */
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for (addr = begin_addr; addr <= end_addr; addr++)
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for (addr = begin_addr; addr <= end_addr; addr++) {
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if (read_port_to_handler[addr] &&
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read_port_to_handler[addr] != &io_read_handlers) { // the default
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BX_ERROR(("IO device address conflict(read) at IO address %Xh",
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(unsigned) addr));
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BX_ERROR((" conflicting devices: %s & %s",
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read_port_to_handler[addr]->handler_name, name));
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return 0;
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return false;
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}
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}
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/* first find existing handle for function or create new one */
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@ -833,7 +831,7 @@ bool bx_devices_c::register_io_read_handler_range(void *this_ptr, bx_read_handle
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io_read_handler->usage_count += end_addr - begin_addr + 1;
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for (addr = begin_addr; addr <= end_addr; addr++)
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read_port_to_handler[addr] = io_read_handler;
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return 1; // address mapped successfully
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return true; // address mapped successfully
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}
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bool bx_devices_c::register_io_write_handler_range(void *this_ptr, bx_write_handler_t f,
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@ -846,24 +844,25 @@ bool bx_devices_c::register_io_write_handler_range(void *this_ptr, bx_write_hand
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if (end_addr < begin_addr) {
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BX_ERROR(("!!! end_addr < begin_addr !!!"));
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return 0;
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return false;
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}
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if (!f) {
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BX_ERROR(("!!! f == NULL !!!"));
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return 0;
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return false;
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}
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/* first check if the port already has a handlers != the default handler */
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for (addr = begin_addr; addr <= end_addr; addr++)
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for (addr = begin_addr; addr <= end_addr; addr++) {
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if (write_port_to_handler[addr] &&
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write_port_to_handler[addr] != &io_write_handlers) { // the default
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BX_ERROR(("IO device address conflict(read) at IO address %Xh",
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(unsigned) addr));
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BX_ERROR((" conflicting devices: %s & %s",
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write_port_to_handler[addr]->handler_name, name));
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return 0;
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return false;
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}
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}
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/* first find existing handle for function or create new one */
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struct io_handler_struct *curr = &io_write_handlers;
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@ -897,10 +896,9 @@ bool bx_devices_c::register_io_write_handler_range(void *this_ptr, bx_write_hand
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io_write_handler->usage_count += end_addr - begin_addr + 1;
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for (addr = begin_addr; addr <= end_addr; addr++)
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write_port_to_handler[addr] = io_write_handler;
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return 1; // address mapped successfully
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return true; // address mapped successfully
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}
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// Registration of default handlers (mainly be the unmapped device)
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bool bx_devices_c::register_default_io_read_handler(void *this_ptr, bx_read_handler_t f,
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const char *name, Bit8u mask)
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@ -914,7 +912,7 @@ bool bx_devices_c::register_default_io_read_handler(void *this_ptr, bx_read_hand
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strcpy(io_read_handlers.handler_name, name);
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io_read_handlers.mask = mask;
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return 1;
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return true;
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}
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bool bx_devices_c::register_default_io_write_handler(void *this_ptr, bx_write_handler_t f,
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@ -929,11 +927,10 @@ bool bx_devices_c::register_default_io_write_handler(void *this_ptr, bx_write_ha
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strcpy(io_write_handlers.handler_name, name);
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io_write_handlers.mask = mask;
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return 1;
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return true;
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}
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bool bx_devices_c::unregister_io_read_handler(void *this_ptr, bx_read_handler_t f,
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Bit32u addr, Bit8u mask)
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bool bx_devices_c::unregister_io_read_handler(void *this_ptr, bx_read_handler_t f, Bit32u addr, Bit8u mask)
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{
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addr &= 0xffff;
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@ -943,27 +940,27 @@ bool bx_devices_c::unregister_io_read_handler(void *this_ptr, bx_read_handler_t
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if (!io_read_handler) {
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BX_ERROR((">>> NO IO_READ_HANDLER <<<"));
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return 0;
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return false;
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}
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if (io_read_handler == &io_read_handlers) {
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BX_ERROR((">>> CANNOT UNREGISTER THE DEFAULT IO_READ_HANDLER <<<"));
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return 0; // cannot unregister the default handler
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return false; // cannot unregister the default handler
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}
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if (io_read_handler->funct != f) {
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BX_ERROR((">>> NOT THE SAME IO_READ_HANDLER FUNC <<<"));
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return 0;
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return false;
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}
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if (io_read_handler->this_ptr != this_ptr) {
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BX_ERROR((">>> NOT THE SAME IO_READ_HANDLER THIS_PTR <<<"));
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return 0;
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return false;
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}
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if (io_read_handler->mask != mask) {
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BX_ERROR((">>> NOT THE SAME IO_READ_HANDLER MASK <<<"));
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return 0;
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return false;
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}
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read_port_to_handler[addr] = &io_read_handlers; // reset to default
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@ -975,7 +972,7 @@ bool bx_devices_c::unregister_io_read_handler(void *this_ptr, bx_read_handler_t
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delete [] io_read_handler->handler_name;
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delete io_read_handler;
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}
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return 1;
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return true;
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}
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bool bx_devices_c::unregister_io_write_handler(void *this_ptr, bx_write_handler_t f,
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@ -986,19 +983,19 @@ bool bx_devices_c::unregister_io_write_handler(void *this_ptr, bx_write_handler_
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struct io_handler_struct *io_write_handler = write_port_to_handler[addr];
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if (!io_write_handler)
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return 0;
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return false;
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if (io_write_handler == &io_write_handlers)
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return 0; // cannot unregister the default handler
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return false; // cannot unregister the default handler
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if (io_write_handler->funct != f)
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return 0;
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return false;
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if (io_write_handler->this_ptr != this_ptr)
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return 0;
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return false;
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if (io_write_handler->mask != mask)
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return 0;
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return false;
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write_port_to_handler[addr] = &io_write_handlers; // reset to default
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io_write_handler->usage_count--;
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@ -1009,7 +1006,7 @@ bool bx_devices_c::unregister_io_write_handler(void *this_ptr, bx_write_handler_
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delete [] io_write_handler->handler_name;
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delete io_write_handler;
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}
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return 1;
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return true;
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}
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bool bx_devices_c::unregister_io_read_handler_range(void *this_ptr, bx_read_handler_t f,
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@ -1017,15 +1014,14 @@ bool bx_devices_c::unregister_io_read_handler_range(void *this_ptr, bx_read_hand
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{
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begin &= 0xffff;
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end &= 0xffff;
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Bit32u addr;
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bool ret = 1;
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bool ret = true;
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/*
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* the easy way this time
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*/
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for (addr = begin; addr <= end; addr++)
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for (Bit32u addr = begin; addr <= end; addr++)
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if (!unregister_io_read_handler(this_ptr, f, addr, mask))
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ret = 0;
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ret = false;
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return ret;
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}
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@ -1035,15 +1031,14 @@ bool bx_devices_c::unregister_io_write_handler_range(void *this_ptr, bx_write_ha
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{
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begin &= 0xffff;
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end &= 0xffff;
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Bit32u addr;
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bool ret = 1;
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bool ret = true;
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/*
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* the easy way this time
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*/
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for (addr = begin; addr <= end; addr++)
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for (Bit32u addr = begin; addr <= end; addr++)
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if (!unregister_io_write_handler(this_ptr, f, addr, mask))
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ret = 0;
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ret = false;
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return ret;
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}
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@ -1109,9 +1104,9 @@ bool bx_devices_c::is_harddrv_enabled(void)
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for (int i=0; i<BX_MAX_ATA_CHANNEL; i++) {
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sprintf(pname, "ata.%d.resources.enabled", i);
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if (SIM->get_param_bool(pname)->get())
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return 1;
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return true;
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}
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return 0;
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return false;
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}
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bool bx_devices_c::is_agp_present(void)
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@ -1119,7 +1114,7 @@ bool bx_devices_c::is_agp_present(void)
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#if BX_SUPPORT_PCI
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return (pci.enabled && ((pci.advopts & BX_PCI_ADVOPT_NOAGP) == 0));
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#else
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return 0;
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return false;
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#endif
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}
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@ -1392,7 +1387,7 @@ bool bx_devices_c::register_pci_handlers(bx_pci_device_c *dev,
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if (strcmp(device, "none")) {
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if (!strcmp(name, device) && !pci.slot_used[i]) {
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*devfunc = ((i + pci.map_slot_to_dev) << 3) | (*devfunc & 0x07);
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pci.slot_used[i] = 1;
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pci.slot_used[i] = true;
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BX_INFO(("PCI slot #%d used by plugin '%s'", i+1, name));
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break;
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}
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@ -1407,20 +1402,20 @@ bool bx_devices_c::register_pci_handlers(bx_pci_device_c *dev,
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sprintf(devname, "pci.slot.%d", i+1);
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SIM->get_param_enum(devname)->set_by_name(name);
|
||||
*devfunc = ((i + pci.map_slot_to_dev) << 3) | (*devfunc & 0x07);
|
||||
pci.slot_used[i] = 1;
|
||||
pci.slot_used[i] = true;
|
||||
BX_INFO(("PCI slot #%d used by plugin '%s'", i+1, name));
|
||||
} else {
|
||||
BX_ERROR(("Plugin '%s' not connected to a PCI slot", name));
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
bus_devfunc = *devfunc;
|
||||
} else if ((bus == 1) && (max_pci_slots == 4)) {
|
||||
pci.slot_used[4] = 1;
|
||||
pci.slot_used[4] = true;
|
||||
bus_devfunc = 0x100;
|
||||
} else {
|
||||
BX_PANIC(("Invalid bus number #%d", bus));
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
/* check if device/function is available */
|
||||
@ -1428,7 +1423,7 @@ bool bx_devices_c::register_pci_handlers(bx_pci_device_c *dev,
|
||||
if (pci.num_pci_handlers >= BX_MAX_PCI_DEVICES) {
|
||||
BX_INFO(("too many PCI devices installed."));
|
||||
BX_PANIC((" try increasing BX_MAX_PCI_DEVICES"));
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
handle = pci.num_pci_handlers++;
|
||||
pci.pci_handler[handle].handler = dev;
|
||||
@ -1440,10 +1435,9 @@ bool bx_devices_c::register_pci_handlers(bx_pci_device_c *dev,
|
||||
BX_INFO(("%s present on AGP bus device #0", descr));
|
||||
}
|
||||
dev->set_name(descr);
|
||||
return 1; // device/function mapped successfully
|
||||
} else {
|
||||
return 0; // device/function not available, return false.
|
||||
return true; // device/function mapped successfully
|
||||
}
|
||||
return false; // device/function not available, return false.
|
||||
}
|
||||
|
||||
bool bx_devices_c::pci_set_base_mem(void *this_ptr, memory_handler_t f1, memory_handler_t f2,
|
||||
@ -1469,9 +1463,9 @@ bool bx_devices_c::pci_set_base_mem(void *this_ptr, memory_handler_t f1, memory_
|
||||
DEV_register_memory_handlers(this_ptr, f1, f2, newbase, newbase + size - 1);
|
||||
}
|
||||
*addr = newbase;
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
bool bx_devices_c::pci_set_base_io(void *this_ptr, bx_read_handler_t f1, bx_write_handler_t f2,
|
||||
@ -1504,9 +1498,9 @@ bool bx_devices_c::pci_set_base_io(void *this_ptr, bx_read_handler_t f1, bx_writ
|
||||
}
|
||||
}
|
||||
*addr = newbase;
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
// PCI device base class (common methods)
|
||||
|
||||
@ -65,55 +65,55 @@ bx_dma_c::~bx_dma_c()
|
||||
BX_DEBUG(("Exit"));
|
||||
}
|
||||
|
||||
unsigned bx_dma_c::registerDMA8Channel(unsigned channel,
|
||||
bool bx_dma_c::registerDMA8Channel(unsigned channel,
|
||||
Bit16u (* dmaRead)(Bit8u *data_byte, Bit16u maxlen),
|
||||
Bit16u (* dmaWrite)(Bit8u *data_byte, Bit16u maxlen),
|
||||
const char *name)
|
||||
{
|
||||
if (channel > 3) {
|
||||
BX_PANIC(("registerDMA8Channel: invalid channel number(%u).", channel));
|
||||
return 0; // Fail
|
||||
return false; // Fail
|
||||
}
|
||||
if (BX_DMA_THIS s[0].chan[channel].used) {
|
||||
BX_PANIC(("registerDMA8Channel: channel(%u) already in use.", channel));
|
||||
return 0; // Fail
|
||||
return false; // Fail
|
||||
}
|
||||
BX_INFO(("channel %u used by %s", channel, name));
|
||||
BX_DMA_THIS h[channel].dmaRead8 = dmaRead;
|
||||
BX_DMA_THIS h[channel].dmaWrite8 = dmaWrite;
|
||||
BX_DMA_THIS s[0].chan[channel].used = 1;
|
||||
return 1; // OK
|
||||
BX_DMA_THIS s[0].chan[channel].used = true;
|
||||
return true; // OK
|
||||
}
|
||||
|
||||
unsigned bx_dma_c::registerDMA16Channel(unsigned channel,
|
||||
bool bx_dma_c::registerDMA16Channel(unsigned channel,
|
||||
Bit16u (* dmaRead)(Bit16u *data_word, Bit16u maxlen),
|
||||
Bit16u (* dmaWrite)(Bit16u *data_word, Bit16u maxlen),
|
||||
const char *name)
|
||||
{
|
||||
if ((channel < 4) || (channel > 7)) {
|
||||
BX_PANIC(("registerDMA16Channel: invalid channel number(%u).", channel));
|
||||
return 0; // Fail
|
||||
return false; // Fail
|
||||
}
|
||||
if (BX_DMA_THIS s[1].chan[channel & 0x03].used) {
|
||||
BX_PANIC(("registerDMA16Channel: channel(%u) already in use.", channel));
|
||||
return 0; // Fail
|
||||
return false; // Fail
|
||||
}
|
||||
BX_INFO(("channel %u used by %s", channel, name));
|
||||
channel &= 0x03;
|
||||
BX_DMA_THIS h[channel].dmaRead16 = dmaRead;
|
||||
BX_DMA_THIS h[channel].dmaWrite16 = dmaWrite;
|
||||
BX_DMA_THIS s[1].chan[channel].used = 1;
|
||||
return 1; // OK
|
||||
BX_DMA_THIS s[1].chan[channel].used = true;
|
||||
return true; // OK
|
||||
}
|
||||
|
||||
unsigned bx_dma_c::unregisterDMAChannel(unsigned channel)
|
||||
bool bx_dma_c::unregisterDMAChannel(unsigned channel)
|
||||
{
|
||||
BX_DMA_THIS s[(channel > 3) ? 1 : 0].chan[channel & 0x03].used = 0;
|
||||
BX_DMA_THIS s[(channel > 3) ? 1 : 0].chan[channel & 0x03].used = false;
|
||||
BX_INFO(("channel %u no longer used", channel));
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
unsigned bx_dma_c::get_TC(void)
|
||||
bool bx_dma_c::get_TC(void)
|
||||
{
|
||||
return BX_DMA_THIS TC;
|
||||
}
|
||||
@ -162,11 +162,11 @@ void bx_dma_c::init(void)
|
||||
BX_DMA_THIS s[i].chan[c].base_count = 0;
|
||||
BX_DMA_THIS s[i].chan[c].current_count = 0;
|
||||
BX_DMA_THIS s[i].chan[c].page_reg = 0;
|
||||
BX_DMA_THIS s[i].chan[c].used = 0;
|
||||
BX_DMA_THIS s[i].chan[c].used = false;
|
||||
}
|
||||
}
|
||||
memset(&BX_DMA_THIS ext_page_reg[0], 0, 16);
|
||||
BX_DMA_THIS s[1].chan[0].used = 1; // cascade channel in use
|
||||
BX_DMA_THIS s[1].chan[0].used = true; // cascade channel in use
|
||||
BX_INFO(("channel 4 used by cascade"));
|
||||
#if BX_DEBUGGER
|
||||
// register device for the 'info device' command (calls debug_dump())
|
||||
@ -194,17 +194,16 @@ void bx_dma_c::reset_controller(unsigned num)
|
||||
|
||||
void bx_dma_c::register_state(void)
|
||||
{
|
||||
unsigned i, c;
|
||||
char name[6];
|
||||
bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "dma", "DMA State");
|
||||
for (i=0; i<2; i++) {
|
||||
for (unsigned i=0; i<2; i++) {
|
||||
sprintf(name, "%u", i);
|
||||
bx_list_c *ctrl = new bx_list_c(list, name);
|
||||
BXRS_PARAM_BOOL(ctrl, flip_flop, BX_DMA_THIS s[i].flip_flop);
|
||||
BXRS_HEX_PARAM_FIELD(ctrl, status_reg, BX_DMA_THIS s[i].status_reg);
|
||||
BXRS_HEX_PARAM_FIELD(ctrl, command_reg, BX_DMA_THIS s[i].command_reg);
|
||||
BXRS_PARAM_BOOL(ctrl, ctrl_disabled, BX_DMA_THIS s[i].ctrl_disabled);
|
||||
for (c=0; c<4; c++) {
|
||||
for (unsigned c=0; c<4; c++) {
|
||||
sprintf(name, "%u", c);
|
||||
bx_list_c *chan = new bx_list_c(ctrl, name);
|
||||
BXRS_PARAM_BOOL(chan, DRQ, BX_DMA_THIS s[i].DRQ[c]);
|
||||
@ -367,7 +366,7 @@ void bx_dma_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsig
|
||||
|
||||
/* 8237 DMA controller */
|
||||
void BX_CPP_AttrRegparmN(3)
|
||||
bx_dma_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
||||
bx_dma_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
||||
{
|
||||
#else
|
||||
UNUSED(this_ptr);
|
||||
|
||||
@ -35,25 +35,25 @@ public:
|
||||
bx_dma_c();
|
||||
virtual ~bx_dma_c();
|
||||
|
||||
virtual void init(void);
|
||||
virtual void reset(unsigned type);
|
||||
virtual void raise_HLDA(void);
|
||||
virtual void set_DRQ(unsigned channel, bool val);
|
||||
virtual unsigned get_TC(void);
|
||||
virtual void register_state(void);
|
||||
virtual void init(void);
|
||||
virtual void reset(unsigned type);
|
||||
virtual void raise_HLDA(void);
|
||||
virtual void set_DRQ(unsigned channel, bool val);
|
||||
virtual bool get_TC(void);
|
||||
virtual void register_state(void);
|
||||
#if BX_DEBUGGER
|
||||
virtual void debug_dump(int argc, char **argv);
|
||||
#endif
|
||||
|
||||
virtual unsigned registerDMA8Channel(unsigned channel,
|
||||
virtual bool registerDMA8Channel(unsigned channel,
|
||||
Bit16u (* dmaRead)(Bit8u *data_byte, Bit16u maxlen),
|
||||
Bit16u (* dmaWrite)(Bit8u *data_byte, Bit16u maxlen),
|
||||
const char *name);
|
||||
virtual unsigned registerDMA16Channel(unsigned channel,
|
||||
virtual bool registerDMA16Channel(unsigned channel,
|
||||
Bit16u (* dmaRead)(Bit16u *data_word, Bit16u maxlen),
|
||||
Bit16u (* dmaWrite)(Bit16u *data_word, Bit16u maxlen),
|
||||
const char *name);
|
||||
virtual unsigned unregisterDMAChannel(unsigned channel);
|
||||
virtual bool unregisterDMAChannel(unsigned channel);
|
||||
|
||||
private:
|
||||
|
||||
|
||||
@ -2307,12 +2307,12 @@ bool bx_floppy_ctrl_c::set_media_status(unsigned drive, bool status)
|
||||
BX_FD_THIS s.media_present[drive] = 0;
|
||||
SIM->get_param_enum("status", floppy)->set(BX_EJECTED);
|
||||
BX_FD_THIS s.DIR[drive] |= 0x80; // disk changed line
|
||||
return 0;
|
||||
return false;
|
||||
} else {
|
||||
// insert floppy
|
||||
const char *path = SIM->get_param_string("path", floppy)->getptr();
|
||||
if (!strcmp(path, "none"))
|
||||
return 0;
|
||||
return false;
|
||||
if (evaluate_media(BX_FD_THIS s.device_type[drive], type, path, & BX_FD_THIS s.media[drive])) {
|
||||
BX_FD_THIS s.media_present[drive] = 1;
|
||||
if (drive == 0) {
|
||||
@ -2334,12 +2334,12 @@ bool bx_floppy_ctrl_c::set_media_status(unsigned drive, bool status)
|
||||
#undef MED
|
||||
SIM->get_param_enum("status", floppy)->set(BX_INSERTED);
|
||||
}
|
||||
return 1;
|
||||
return true;
|
||||
} else {
|
||||
BX_FD_THIS s.media_present[drive] = 0;
|
||||
SIM->get_param_enum("status", floppy)->set(BX_EJECTED);
|
||||
SIM->get_param_enum("type", floppy)->set(BX_FLOPPY_NONE);
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -2611,7 +2611,7 @@ typedef struct {
|
||||
unsigned supported;
|
||||
} fdc_type_supported;
|
||||
|
||||
static fdc_type_supported fdc_supported[] = {
|
||||
static const fdc_type_supported fdc_supported[] = {
|
||||
{ FD_CMD_MODE, 0x00,
|
||||
FDC_TYPE_DP8473 | FDC_TYPE_PC87306 | FDC_TYPE_BOCHS },
|
||||
{ FD_CMD_READ_TRACK, FD_CMD_MFM,
|
||||
|
||||
@ -136,24 +136,24 @@ static bool hpet_read(bx_phy_address a20addr, unsigned len, void *data, void *pa
|
||||
if (len == 4) { // must be 32-bit aligned
|
||||
if ((a20addr & 0x3) != 0) {
|
||||
BX_PANIC(("Unaligned HPET read at address 0x" FMT_PHY_ADDRX, a20addr));
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
value1 = theHPET->read_aligned(a20addr);
|
||||
*((Bit32u *)data) = value1;
|
||||
return 1;
|
||||
return true;
|
||||
} else if (len == 8) { // must be 64-bit aligned
|
||||
if ((a20addr & 0x7) != 0) {
|
||||
BX_PANIC(("Unaligned HPET read at address 0x" FMT_PHY_ADDRX, a20addr));
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
value1 = theHPET->read_aligned(a20addr);
|
||||
value2 = theHPET->read_aligned(a20addr + 4);
|
||||
*((Bit64u *)data) = (value1 | (value2 << 32));
|
||||
return 1;
|
||||
return true;
|
||||
} else {
|
||||
BX_PANIC(("Unsupported HPET read at address 0x" FMT_PHY_ADDRX, a20addr));
|
||||
}
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool hpet_write(bx_phy_address a20addr, unsigned len, void *data, void *param)
|
||||
@ -161,14 +161,14 @@ static bool hpet_write(bx_phy_address a20addr, unsigned len, void *data, void *p
|
||||
if (len == 4) { // must be 32-bit aligned
|
||||
if ((a20addr & 0x3) != 0) {
|
||||
BX_PANIC(("Unaligned HPET write at address 0x" FMT_PHY_ADDRX, a20addr));
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
theHPET->write_aligned(a20addr, *((Bit32u*) data), true);
|
||||
return 1;
|
||||
return true;
|
||||
} else if (len == 8) { // must be 64-bit aligned
|
||||
if ((a20addr & 0x7) != 0) {
|
||||
BX_PANIC(("Unaligned HPET write at address 0x" FMT_PHY_ADDRX, a20addr));
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
Bit64u val64 = *((Bit64u*) data);
|
||||
theHPET->write_aligned(a20addr, (Bit32u)val64, false);
|
||||
@ -176,7 +176,7 @@ static bool hpet_write(bx_phy_address a20addr, unsigned len, void *data, void *p
|
||||
} else {
|
||||
BX_PANIC(("Unsupported HPET write at address 0x" FMT_PHY_ADDRX, a20addr));
|
||||
}
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
// the device object
|
||||
@ -261,16 +261,12 @@ Bit64u bx_hpet_c::hpet_get_ticks(void)
|
||||
Bit64u bx_hpet_c::hpet_calculate_diff(const HPETTimer *t, Bit64u current) const
|
||||
{
|
||||
if (t->config & HPET_TN_32BIT) {
|
||||
Bit32u diff, cmp;
|
||||
|
||||
cmp = (Bit32u)t->cmp;
|
||||
diff = cmp - (Bit32u)current;
|
||||
Bit32u cmp = (Bit32u)t->cmp;
|
||||
Bit32u diff = cmp - (Bit32u)current;
|
||||
return (Bit64u)diff;
|
||||
} else {
|
||||
Bit64u diff2, cmp2;
|
||||
|
||||
cmp2 = t->cmp;
|
||||
diff2 = cmp2 - current;
|
||||
Bit64u cmp2 = t->cmp;
|
||||
Bit64u diff2 = cmp2 - current;
|
||||
return diff2;
|
||||
}
|
||||
}
|
||||
|
||||
@ -351,11 +351,10 @@ void bx_ioapic_c::register_state(void)
|
||||
#if BX_DEBUGGER
|
||||
void bx_ioapic_c::debug_dump(int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
char buf[1024];
|
||||
|
||||
dbg_printf("82093AA I/O APIC\n\n");
|
||||
for (i = 0; i < BX_IOAPIC_NUM_PINS; i++) {
|
||||
for (int i = 0; i < BX_IOAPIC_NUM_PINS; i++) {
|
||||
bx_io_redirect_entry_t *entry = ioredtbl + i;
|
||||
entry->sprintf_self(buf);
|
||||
dbg_printf("entry[%d]: %s\n", i, buf);
|
||||
|
||||
@ -235,27 +235,27 @@ public:
|
||||
|
||||
class BOCHSAPI bx_dma_stub_c : public bx_devmodel_c {
|
||||
public:
|
||||
virtual unsigned registerDMA8Channel(
|
||||
virtual bool registerDMA8Channel(
|
||||
unsigned channel,
|
||||
Bit16u (* dmaRead)(Bit8u *data_byte, Bit16u maxlen),
|
||||
Bit16u (* dmaWrite)(Bit8u *data_byte, Bit16u maxlen),
|
||||
const char *name)
|
||||
{
|
||||
STUBFUNC(dma, registerDMA8Channel); return 0;
|
||||
STUBFUNC(dma, registerDMA8Channel); return false;
|
||||
}
|
||||
virtual unsigned registerDMA16Channel(
|
||||
virtual bool registerDMA16Channel(
|
||||
unsigned channel,
|
||||
Bit16u (* dmaRead)(Bit16u *data_word, Bit16u maxlen),
|
||||
Bit16u (* dmaWrite)(Bit16u *data_word, Bit16u maxlen),
|
||||
const char *name)
|
||||
{
|
||||
STUBFUNC(dma, registerDMA16Channel); return 0;
|
||||
STUBFUNC(dma, registerDMA16Channel); return false;
|
||||
}
|
||||
virtual unsigned unregisterDMAChannel(unsigned channel) {
|
||||
STUBFUNC(dma, unregisterDMAChannel); return 0;
|
||||
virtual bool unregisterDMAChannel(unsigned channel) {
|
||||
STUBFUNC(dma, unregisterDMAChannel); return false;
|
||||
}
|
||||
virtual unsigned get_TC(void) {
|
||||
STUBFUNC(dma, get_TC); return 0;
|
||||
virtual bool get_TC(void) {
|
||||
STUBFUNC(dma, get_TC); return false;
|
||||
}
|
||||
virtual void set_DRQ(unsigned channel, bool val) {
|
||||
STUBFUNC(dma, set_DRQ);
|
||||
|
||||
@ -650,7 +650,7 @@ void bx_keyb_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
||||
bool bx_keyb_c::gen_scancode_static(void *dev, Bit32u key)
|
||||
{
|
||||
((bx_keyb_c*)dev)->gen_scancode(key);
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
void bx_keyb_c::gen_scancode(Bit32u key)
|
||||
|
||||
@ -457,11 +457,10 @@ bool bx_pci_bridge_c::agp_ap_read_handler(bx_phy_address addr, unsigned len,
|
||||
*((Bit32u *) data) = value;
|
||||
break;
|
||||
}
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
Bit32u bx_pci_bridge_c::agp_aperture_read(bx_phy_address addr, unsigned len,
|
||||
bool agp)
|
||||
Bit32u bx_pci_bridge_c::agp_aperture_read(bx_phy_address addr, unsigned len, bool agp)
|
||||
{
|
||||
if (BX_PCI_THIS pci_conf[0x51] & 0x02) {
|
||||
Bit32u offset = (Bit32u)(addr - pci_bar[0].addr);
|
||||
@ -474,20 +473,18 @@ Bit32u bx_pci_bridge_c::agp_aperture_read(bx_phy_address addr, unsigned len,
|
||||
page_addr, (Bit16u)page_offset));
|
||||
// TODO
|
||||
}
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
bool bx_pci_bridge_c::agp_ap_write_handler(bx_phy_address addr, unsigned len,
|
||||
void *data, void *param)
|
||||
bool bx_pci_bridge_c::agp_ap_write_handler(bx_phy_address addr, unsigned len, void *data, void *param)
|
||||
{
|
||||
bx_pci_bridge_c *class_ptr = (bx_pci_bridge_c*)param;
|
||||
Bit32u value = *(Bit32u*)data;
|
||||
class_ptr->agp_aperture_write(addr, value, len, 0);
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
void bx_pci_bridge_c::agp_aperture_write(bx_phy_address addr, Bit32u value,
|
||||
unsigned len, bool agp)
|
||||
void bx_pci_bridge_c::agp_aperture_write(bx_phy_address addr, Bit32u value, unsigned len, bool agp)
|
||||
{
|
||||
if (BX_PCI_THIS pci_conf[0x51] & 0x02) {
|
||||
Bit32u offset = (Bit32u)(addr - pci_bar[0].addr);
|
||||
|
||||
@ -918,7 +918,7 @@ bool pit_82C54::read_OUT(Bit8u cnum)
|
||||
{
|
||||
if (cnum>MAX_COUNTER) {
|
||||
BX_ERROR(("Counter number incorrect in 82C54 read_OUT"));
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
return counter[cnum].OUTpin;
|
||||
@ -928,7 +928,7 @@ bool pit_82C54::read_GATE(Bit8u cnum)
|
||||
{
|
||||
if (cnum>MAX_COUNTER) {
|
||||
BX_ERROR(("Counter number incorrect in 82C54 read_GATE"));
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
return counter[cnum].GATE;
|
||||
@ -938,7 +938,7 @@ Bit32u pit_82C54::get_clock_event_time(Bit8u cnum)
|
||||
{
|
||||
if (cnum>MAX_COUNTER) {
|
||||
BX_ERROR(("Counter number incorrect in 82C54 read_GATE"));
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
return counter[cnum].next_change_time;
|
||||
|
||||
@ -30,7 +30,7 @@
|
||||
#include "gui/gui.h" // for BX_KEY_NBKEYS
|
||||
#include "scancodes.h"
|
||||
|
||||
unsigned char translation8042[256] = {
|
||||
const unsigned char translation8042[256] = {
|
||||
0xff,0x43,0x41,0x3f,0x3d,0x3b,0x3c,0x58,0x64,0x44,0x42,0x40,0x3e,0x0f,0x29,0x59,
|
||||
0x65,0x38,0x2a,0x70,0x1d,0x10,0x02,0x5a,0x66,0x71,0x2c,0x1f,0x1e,0x11,0x03,0x5b,
|
||||
0x67,0x2e,0x2d,0x20,0x12,0x05,0x04,0x5c,0x68,0x39,0x2f,0x21,0x14,0x13,0x06,0x5d,
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
#define BX_SCANCODES_H
|
||||
|
||||
// Translation table of the 8042
|
||||
extern unsigned char translation8042[256];
|
||||
extern const unsigned char translation8042[256];
|
||||
|
||||
typedef struct {
|
||||
const char *make;
|
||||
|
||||
@ -281,15 +281,15 @@ bx_serial_c::init(void)
|
||||
DEV_register_irq(BX_SER_THIS s[i].IRQ, name);
|
||||
}
|
||||
/* internal state */
|
||||
BX_SER_THIS s[i].ls_ipending = 0;
|
||||
BX_SER_THIS s[i].ms_ipending = 0;
|
||||
BX_SER_THIS s[i].rx_ipending = 0;
|
||||
BX_SER_THIS s[i].fifo_ipending = 0;
|
||||
BX_SER_THIS s[i].ls_interrupt = 0;
|
||||
BX_SER_THIS s[i].ms_interrupt = 0;
|
||||
BX_SER_THIS s[i].rx_interrupt = 0;
|
||||
BX_SER_THIS s[i].tx_interrupt = 0;
|
||||
BX_SER_THIS s[i].fifo_interrupt = 0;
|
||||
BX_SER_THIS s[i].ls_ipending = false;
|
||||
BX_SER_THIS s[i].ms_ipending = false;
|
||||
BX_SER_THIS s[i].rx_ipending = false;
|
||||
BX_SER_THIS s[i].fifo_ipending = false;
|
||||
BX_SER_THIS s[i].ls_interrupt = false;
|
||||
BX_SER_THIS s[i].ms_interrupt = false;
|
||||
BX_SER_THIS s[i].rx_interrupt = false;
|
||||
BX_SER_THIS s[i].tx_interrupt = false;
|
||||
BX_SER_THIS s[i].fifo_interrupt = false;
|
||||
|
||||
if (BX_SER_THIS s[i].tx_timer_index == BX_NULL_TIMER_HANDLE) {
|
||||
BX_SER_THIS s[i].tx_timer_index =
|
||||
@ -697,59 +697,59 @@ void bx_serial_c::register_state(void)
|
||||
void bx_serial_c::lower_interrupt(Bit8u port)
|
||||
{
|
||||
/* If there are no more ints pending, clear the irq */
|
||||
if ((BX_SER_THIS s[port].rx_interrupt == 0) &&
|
||||
(BX_SER_THIS s[port].tx_interrupt == 0) &&
|
||||
(BX_SER_THIS s[port].ls_interrupt == 0) &&
|
||||
(BX_SER_THIS s[port].ms_interrupt == 0) &&
|
||||
(BX_SER_THIS s[port].fifo_interrupt == 0)) {
|
||||
if ((BX_SER_THIS s[port].rx_interrupt == false) &&
|
||||
(BX_SER_THIS s[port].tx_interrupt == false) &&
|
||||
(BX_SER_THIS s[port].ls_interrupt == false) &&
|
||||
(BX_SER_THIS s[port].ms_interrupt == false) &&
|
||||
(BX_SER_THIS s[port].fifo_interrupt == false)) {
|
||||
DEV_pic_lower_irq(BX_SER_THIS s[port].IRQ);
|
||||
}
|
||||
}
|
||||
|
||||
void bx_serial_c::raise_interrupt(Bit8u port, int type)
|
||||
{
|
||||
bool gen_int = 0;
|
||||
bool gen_int = false;
|
||||
|
||||
switch (type) {
|
||||
case BX_SER_INT_IER: /* IER has changed */
|
||||
gen_int = 1;
|
||||
gen_int = true;
|
||||
break;
|
||||
case BX_SER_INT_RXDATA:
|
||||
if (BX_SER_THIS s[port].int_enable.rxdata_enable) {
|
||||
BX_SER_THIS s[port].rx_interrupt = 1;
|
||||
gen_int = 1;
|
||||
BX_SER_THIS s[port].rx_interrupt = true;
|
||||
gen_int = true;
|
||||
} else {
|
||||
BX_SER_THIS s[port].rx_ipending = 1;
|
||||
BX_SER_THIS s[port].rx_ipending = true;
|
||||
}
|
||||
break;
|
||||
case BX_SER_INT_TXHOLD:
|
||||
if (BX_SER_THIS s[port].int_enable.txhold_enable) {
|
||||
BX_SER_THIS s[port].tx_interrupt = 1;
|
||||
gen_int = 1;
|
||||
BX_SER_THIS s[port].tx_interrupt = true;
|
||||
gen_int = true;
|
||||
}
|
||||
break;
|
||||
case BX_SER_INT_RXLSTAT:
|
||||
if (BX_SER_THIS s[port].int_enable.rxlstat_enable) {
|
||||
BX_SER_THIS s[port].ls_interrupt = 1;
|
||||
gen_int = 1;
|
||||
BX_SER_THIS s[port].ls_interrupt = true;
|
||||
gen_int = true;
|
||||
} else {
|
||||
BX_SER_THIS s[port].ls_ipending = 1;
|
||||
BX_SER_THIS s[port].ls_ipending = true;
|
||||
}
|
||||
break;
|
||||
case BX_SER_INT_MODSTAT:
|
||||
if ((BX_SER_THIS s[port].ms_ipending == 1) &&
|
||||
if ((BX_SER_THIS s[port].ms_ipending) &&
|
||||
(BX_SER_THIS s[port].int_enable.modstat_enable == 1)) {
|
||||
BX_SER_THIS s[port].ms_interrupt = 1;
|
||||
BX_SER_THIS s[port].ms_ipending = 0;
|
||||
gen_int = 1;
|
||||
BX_SER_THIS s[port].ms_interrupt = true;
|
||||
BX_SER_THIS s[port].ms_ipending = false;
|
||||
gen_int = true;
|
||||
}
|
||||
break;
|
||||
case BX_SER_INT_FIFO:
|
||||
if (BX_SER_THIS s[port].int_enable.rxdata_enable) {
|
||||
BX_SER_THIS s[port].fifo_interrupt = 1;
|
||||
gen_int = 1;
|
||||
BX_SER_THIS s[port].fifo_interrupt = true;
|
||||
gen_int = true;
|
||||
} else {
|
||||
BX_SER_THIS s[port].fifo_ipending = 1;
|
||||
BX_SER_THIS s[port].fifo_ipending = true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -805,17 +805,17 @@ Bit32u bx_serial_c::read(Bit32u address, unsigned io_len)
|
||||
}
|
||||
if (BX_SER_THIS s[port].rx_fifo_end == 0) {
|
||||
BX_SER_THIS s[port].line_status.rxdata_ready = 0;
|
||||
BX_SER_THIS s[port].rx_interrupt = 0;
|
||||
BX_SER_THIS s[port].rx_ipending = 0;
|
||||
BX_SER_THIS s[port].fifo_interrupt = 0;
|
||||
BX_SER_THIS s[port].fifo_ipending = 0;
|
||||
BX_SER_THIS s[port].rx_interrupt = false;
|
||||
BX_SER_THIS s[port].rx_ipending = false;
|
||||
BX_SER_THIS s[port].fifo_interrupt = false;
|
||||
BX_SER_THIS s[port].fifo_ipending = false;
|
||||
lower_interrupt(port);
|
||||
}
|
||||
} else {
|
||||
val = BX_SER_THIS s[port].rxbuffer;
|
||||
BX_SER_THIS s[port].line_status.rxdata_ready = 0;
|
||||
BX_SER_THIS s[port].rx_interrupt = 0;
|
||||
BX_SER_THIS s[port].rx_ipending = 0;
|
||||
BX_SER_THIS s[port].rx_interrupt = false;
|
||||
BX_SER_THIS s[port].rx_ipending = false;
|
||||
lower_interrupt(port);
|
||||
}
|
||||
}
|
||||
@ -855,7 +855,7 @@ Bit32u bx_serial_c::read(Bit32u address, unsigned io_len)
|
||||
BX_SER_THIS s[port].int_ident.int_ID = 0x0;
|
||||
BX_SER_THIS s[port].int_ident.ipending = 1;
|
||||
}
|
||||
BX_SER_THIS s[port].tx_interrupt = 0;
|
||||
BX_SER_THIS s[port].tx_interrupt = false;
|
||||
lower_interrupt(port);
|
||||
|
||||
val = (Bit8u)BX_SER_THIS s[port].int_ident.ipending |
|
||||
@ -893,8 +893,8 @@ Bit32u bx_serial_c::read(Bit32u address, unsigned io_len)
|
||||
BX_SER_THIS s[port].line_status.overrun_error = 0;
|
||||
BX_SER_THIS s[port].line_status.framing_error = 0;
|
||||
BX_SER_THIS s[port].line_status.break_int = 0;
|
||||
BX_SER_THIS s[port].ls_interrupt = 0;
|
||||
BX_SER_THIS s[port].ls_ipending = 0;
|
||||
BX_SER_THIS s[port].ls_interrupt = false;
|
||||
BX_SER_THIS s[port].ls_ipending = false;
|
||||
lower_interrupt(port);
|
||||
break;
|
||||
|
||||
@ -936,8 +936,8 @@ Bit32u bx_serial_c::read(Bit32u address, unsigned io_len)
|
||||
BX_SER_THIS s[port].modem_status.delta_dsr = 0;
|
||||
BX_SER_THIS s[port].modem_status.ri_trailedge = 0;
|
||||
BX_SER_THIS s[port].modem_status.delta_dcd = 0;
|
||||
BX_SER_THIS s[port].ms_interrupt = 0;
|
||||
BX_SER_THIS s[port].ms_ipending = 0;
|
||||
BX_SER_THIS s[port].ms_interrupt = false;
|
||||
BX_SER_THIS s[port].ms_ipending = false;
|
||||
lower_interrupt(port);
|
||||
break;
|
||||
|
||||
@ -972,7 +972,7 @@ void bx_serial_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
||||
#else
|
||||
UNUSED(this_ptr);
|
||||
#endif // !BX_USE_SER_SMF
|
||||
bool gen_int = 0;
|
||||
bool gen_int = false;
|
||||
Bit8u offset, new_wordlen;
|
||||
#if BX_USE_RAW_SERIAL
|
||||
bool mcr_changed = 0;
|
||||
@ -1045,7 +1045,7 @@ void bx_serial_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
||||
0); /* not continuous */
|
||||
}
|
||||
} else {
|
||||
BX_SER_THIS s[port].tx_interrupt = 0;
|
||||
BX_SER_THIS s[port].tx_interrupt = false;
|
||||
lower_interrupt(port);
|
||||
}
|
||||
} else {
|
||||
@ -1069,15 +1069,15 @@ void bx_serial_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
||||
if (new_b3 != BX_SER_THIS s[port].int_enable.modstat_enable) {
|
||||
BX_SER_THIS s[port].int_enable.modstat_enable = new_b3;
|
||||
if (BX_SER_THIS s[port].int_enable.modstat_enable == 1) {
|
||||
if (BX_SER_THIS s[port].ms_ipending == 1) {
|
||||
BX_SER_THIS s[port].ms_interrupt = 1;
|
||||
BX_SER_THIS s[port].ms_ipending = 0;
|
||||
gen_int = 1;
|
||||
if (BX_SER_THIS s[port].ms_ipending) {
|
||||
BX_SER_THIS s[port].ms_interrupt = true;
|
||||
BX_SER_THIS s[port].ms_ipending = false;
|
||||
gen_int = true;
|
||||
}
|
||||
} else {
|
||||
if (BX_SER_THIS s[port].ms_interrupt == 1) {
|
||||
BX_SER_THIS s[port].ms_interrupt = 0;
|
||||
BX_SER_THIS s[port].ms_ipending = 1;
|
||||
if (BX_SER_THIS s[port].ms_interrupt) {
|
||||
BX_SER_THIS s[port].ms_interrupt = false;
|
||||
BX_SER_THIS s[port].ms_ipending = true;
|
||||
lower_interrupt(port);
|
||||
}
|
||||
}
|
||||
@ -1086,34 +1086,34 @@ void bx_serial_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
||||
BX_SER_THIS s[port].int_enable.txhold_enable = new_b1;
|
||||
if (BX_SER_THIS s[port].int_enable.txhold_enable == 1) {
|
||||
BX_SER_THIS s[port].tx_interrupt = BX_SER_THIS s[port].line_status.thr_empty;
|
||||
if (BX_SER_THIS s[port].tx_interrupt) gen_int = 1;
|
||||
if (BX_SER_THIS s[port].tx_interrupt) gen_int = true;
|
||||
} else {
|
||||
BX_SER_THIS s[port].tx_interrupt = 0;
|
||||
BX_SER_THIS s[port].tx_interrupt = false;
|
||||
lower_interrupt(port);
|
||||
}
|
||||
}
|
||||
if (new_b0 != BX_SER_THIS s[port].int_enable.rxdata_enable) {
|
||||
BX_SER_THIS s[port].int_enable.rxdata_enable = new_b0;
|
||||
if (BX_SER_THIS s[port].int_enable.rxdata_enable == 1) {
|
||||
if (BX_SER_THIS s[port].fifo_ipending == 1) {
|
||||
BX_SER_THIS s[port].fifo_interrupt = 1;
|
||||
BX_SER_THIS s[port].fifo_ipending = 0;
|
||||
gen_int = 1;
|
||||
if (BX_SER_THIS s[port].fifo_ipending) {
|
||||
BX_SER_THIS s[port].fifo_interrupt = true;
|
||||
BX_SER_THIS s[port].fifo_ipending = false;
|
||||
gen_int = true;
|
||||
}
|
||||
if (BX_SER_THIS s[port].rx_ipending == 1) {
|
||||
BX_SER_THIS s[port].rx_interrupt = 1;
|
||||
BX_SER_THIS s[port].rx_ipending = 0;
|
||||
gen_int = 1;
|
||||
if (BX_SER_THIS s[port].rx_ipending) {
|
||||
BX_SER_THIS s[port].rx_interrupt = true;
|
||||
BX_SER_THIS s[port].rx_ipending = false;
|
||||
gen_int = true;
|
||||
}
|
||||
} else {
|
||||
if (BX_SER_THIS s[port].rx_interrupt == 1) {
|
||||
BX_SER_THIS s[port].rx_interrupt = 0;
|
||||
BX_SER_THIS s[port].rx_ipending = 1;
|
||||
if (BX_SER_THIS s[port].rx_interrupt) {
|
||||
BX_SER_THIS s[port].rx_interrupt = false;
|
||||
BX_SER_THIS s[port].rx_ipending = true;
|
||||
lower_interrupt(port);
|
||||
}
|
||||
if (BX_SER_THIS s[port].fifo_interrupt == 1) {
|
||||
BX_SER_THIS s[port].fifo_interrupt = 0;
|
||||
BX_SER_THIS s[port].fifo_ipending = 1;
|
||||
if (BX_SER_THIS s[port].fifo_interrupt) {
|
||||
BX_SER_THIS s[port].fifo_interrupt = false;
|
||||
BX_SER_THIS s[port].fifo_ipending = true;
|
||||
lower_interrupt(port);
|
||||
}
|
||||
}
|
||||
@ -1121,15 +1121,15 @@ void bx_serial_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
||||
if (new_b2 != BX_SER_THIS s[port].int_enable.rxlstat_enable) {
|
||||
BX_SER_THIS s[port].int_enable.rxlstat_enable = new_b2;
|
||||
if (BX_SER_THIS s[port].int_enable.rxlstat_enable == 1) {
|
||||
if (BX_SER_THIS s[port].ls_ipending == 1) {
|
||||
BX_SER_THIS s[port].ls_interrupt = 1;
|
||||
BX_SER_THIS s[port].ls_ipending = 0;
|
||||
gen_int = 1;
|
||||
if (BX_SER_THIS s[port].ls_ipending) {
|
||||
BX_SER_THIS s[port].ls_interrupt = true;
|
||||
BX_SER_THIS s[port].ls_ipending = false;
|
||||
gen_int = true;
|
||||
}
|
||||
} else {
|
||||
if (BX_SER_THIS s[port].ls_interrupt == 1) {
|
||||
BX_SER_THIS s[port].ls_interrupt = 0;
|
||||
BX_SER_THIS s[port].ls_ipending = 1;
|
||||
if (BX_SER_THIS s[port].ls_interrupt) {
|
||||
BX_SER_THIS s[port].ls_interrupt = false;
|
||||
BX_SER_THIS s[port].ls_ipending = true;
|
||||
lower_interrupt(port);
|
||||
}
|
||||
}
|
||||
@ -1295,19 +1295,19 @@ void bx_serial_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
||||
BX_SER_THIS s[port].modem_status.dcd = BX_SER_THIS s[port].modem_cntl.out2;
|
||||
if (BX_SER_THIS s[port].modem_status.cts != prev_cts) {
|
||||
BX_SER_THIS s[port].modem_status.delta_cts = 1;
|
||||
BX_SER_THIS s[port].ms_ipending = 1;
|
||||
BX_SER_THIS s[port].ms_ipending = true;
|
||||
}
|
||||
if (BX_SER_THIS s[port].modem_status.dsr != prev_dsr) {
|
||||
BX_SER_THIS s[port].modem_status.delta_dsr = 1;
|
||||
BX_SER_THIS s[port].ms_ipending = 1;
|
||||
BX_SER_THIS s[port].ms_ipending = true;
|
||||
}
|
||||
if (BX_SER_THIS s[port].modem_status.ri != prev_ri)
|
||||
BX_SER_THIS s[port].ms_ipending = 1;
|
||||
BX_SER_THIS s[port].ms_ipending = true;
|
||||
if ((BX_SER_THIS s[port].modem_status.ri == 0) && (prev_ri == 1))
|
||||
BX_SER_THIS s[port].modem_status.ri_trailedge = 1;
|
||||
if (BX_SER_THIS s[port].modem_status.dcd != prev_dcd) {
|
||||
BX_SER_THIS s[port].modem_status.delta_dcd = 1;
|
||||
BX_SER_THIS s[port].ms_ipending = 1;
|
||||
BX_SER_THIS s[port].ms_ipending = true;
|
||||
}
|
||||
raise_interrupt(port, BX_SER_INT_MODSTAT);
|
||||
} else {
|
||||
@ -1373,7 +1373,7 @@ void bx_serial_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
||||
|
||||
void bx_serial_c::rx_fifo_enq(Bit8u port, Bit8u data)
|
||||
{
|
||||
bool gen_int = 0;
|
||||
bool gen_int = false;
|
||||
|
||||
if (BX_SER_THIS s[port].fifo_cntl.enable) {
|
||||
if (BX_SER_THIS s[port].rx_fifo_end == 16) {
|
||||
@ -1386,16 +1386,16 @@ void bx_serial_c::rx_fifo_enq(Bit8u port, Bit8u data)
|
||||
BX_SER_THIS s[port].rx_fifo[BX_SER_THIS s[port].rx_fifo_end++] = data;
|
||||
switch (BX_SER_THIS s[port].fifo_cntl.rxtrigger) {
|
||||
case 1:
|
||||
if (BX_SER_THIS s[port].rx_fifo_end == 4) gen_int = 1;
|
||||
if (BX_SER_THIS s[port].rx_fifo_end == 4) gen_int = true;
|
||||
break;
|
||||
case 2:
|
||||
if (BX_SER_THIS s[port].rx_fifo_end == 8) gen_int = 1;
|
||||
if (BX_SER_THIS s[port].rx_fifo_end == 8) gen_int = true;
|
||||
break;
|
||||
case 3:
|
||||
if (BX_SER_THIS s[port].rx_fifo_end == 14) gen_int = 1;
|
||||
if (BX_SER_THIS s[port].rx_fifo_end == 14) gen_int = true;
|
||||
break;
|
||||
default:
|
||||
gen_int = 1;
|
||||
gen_int = true;
|
||||
}
|
||||
if (gen_int) {
|
||||
bx_pc_system.deactivate_timer(BX_SER_THIS s[port].fifo_timer_index);
|
||||
@ -1428,7 +1428,7 @@ void bx_serial_c::tx_timer_handler(void *this_ptr)
|
||||
|
||||
void bx_serial_c::tx_timer(void)
|
||||
{
|
||||
bool gen_int = 0;
|
||||
bool gen_int = false;
|
||||
Bit8u port = (Bit8u)bx_pc_system.triggeredTimerParam();
|
||||
|
||||
switch (BX_SER_THIS s[port].io_mode) {
|
||||
@ -1493,7 +1493,7 @@ void bx_serial_c::tx_timer(void)
|
||||
} else if (!BX_SER_THIS s[port].line_status.thr_empty) {
|
||||
BX_SER_THIS s[port].tsrbuffer = BX_SER_THIS s[port].thrbuffer;
|
||||
BX_SER_THIS s[port].line_status.tsr_empty = 0;
|
||||
gen_int = 1;
|
||||
gen_int = true;
|
||||
}
|
||||
if (!BX_SER_THIS s[port].line_status.tsr_empty) {
|
||||
if (gen_int) {
|
||||
@ -1654,8 +1654,7 @@ void bx_serial_c::rx_timer(void)
|
||||
db_usec *= 4;
|
||||
}
|
||||
|
||||
bx_pc_system.activate_timer(BX_SER_THIS s[port].rx_timer_index,
|
||||
db_usec, 0); /* not continuous */
|
||||
bx_pc_system.activate_timer(BX_SER_THIS s[port].rx_timer_index, db_usec, 0); /* not continuous */
|
||||
}
|
||||
|
||||
void bx_serial_c::fifo_timer_handler(void *this_ptr)
|
||||
@ -1713,7 +1712,6 @@ void bx_serial_c::update_mouse_data()
|
||||
Bit8u b1, b2, b3, button_state, mouse_data[5];
|
||||
int bytes, tail;
|
||||
|
||||
|
||||
if (BX_SER_THIS mouse_delayed_dx > 127) {
|
||||
delta_x = 127;
|
||||
BX_SER_THIS mouse_delayed_dx -= 127;
|
||||
|
||||
@ -68,7 +68,7 @@ void bx_slowdown_timer_c::init(void)
|
||||
|
||||
BX_INFO(("using 'slowdown' timer synchronization method"));
|
||||
s.MAXmultiplier = MAXMULT;
|
||||
s.Q=Qval;
|
||||
s.Q = Qval;
|
||||
|
||||
if(s.MAXmultiplier<1)
|
||||
s.MAXmultiplier=1;
|
||||
|
||||
@ -173,7 +173,7 @@ void bx_virt_timer_c::periodic(Bit64u time_passed, bool mode)
|
||||
s[mode].timers_next_event_time = s[mode].current_timers_time + BX_MAX_VIRTUAL_TIME;
|
||||
for (i=0;i<numTimers;i++) {
|
||||
if (timer[i].inUse && timer[i].active && (timer[i].realtime == mode) &&
|
||||
((timer[i].timeToFire)<s[mode].timers_next_event_time)) {
|
||||
(timer[i].timeToFire < s[mode].timers_next_event_time)) {
|
||||
s[mode].timers_next_event_time = timer[i].timeToFire;
|
||||
}
|
||||
}
|
||||
@ -266,13 +266,13 @@ bool bx_virt_timer_c::unregisterTimer(unsigned timerID)
|
||||
|
||||
if (timer[timerID].active) {
|
||||
BX_PANIC(("unregisterTimer: timer '%s' is still active!", timer[timerID].id));
|
||||
return(0); // Fail.
|
||||
return false; // Fail
|
||||
}
|
||||
|
||||
//No need to prevent doing this to unused timers.
|
||||
timer[timerID].inUse = 0;
|
||||
if (timerID == (numTimers-1)) numTimers--;
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
void bx_virt_timer_c::start_timers(void)
|
||||
@ -307,7 +307,7 @@ void bx_virt_timer_c::deactivate_timer(unsigned timer_index)
|
||||
BX_ASSERT(timer_index < BX_MAX_VIRTUAL_TIMERS);
|
||||
|
||||
//No need to prevent doing this to unused/inactive timers.
|
||||
timer[timer_index].active = 0;
|
||||
timer[timer_index].active = false;
|
||||
}
|
||||
|
||||
void bx_virt_timer_c::advance_virtual_time(Bit64u time_passed, bool mode)
|
||||
@ -480,7 +480,7 @@ void bx_virt_timer_c::timer_handler(bool mode)
|
||||
|
||||
if (ticks_delta) {
|
||||
|
||||
# if DEBUG_REALTIME_WITH_PRINTF
|
||||
#if DEBUG_REALTIME_WITH_PRINTF
|
||||
//Every second print some info.
|
||||
if (((last_real_time + real_time_delta) / USEC_PER_SECOND) > (last_real_time / USEC_PER_SECOND)) {
|
||||
Bit64u temp1, temp2, temp3, temp4;
|
||||
@ -493,7 +493,7 @@ void bx_virt_timer_c::timer_handler(bool mode)
|
||||
printf("ticks: " FMT_LL "u, ", temp3);
|
||||
printf("diff: " FMT_LL "u\n", temp4);
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
|
||||
last_real_time += real_time_delta;
|
||||
total_real_usec += real_time_delta;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user