- update so that it applies clean again
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@ -28,18 +28,15 @@ Instructions:
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Index: cpu/cpu.h
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
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retrieving revision 1.78
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diff -u -r1.78 cpu.h
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--- cpu/cpu.h 24 Sep 2002 18:33:37 -0000 1.78
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+++ cpu/cpu.h 25 Sep 2002 02:59:01 -0000
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@@ -575,12 +575,18 @@
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typedef struct {
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Bit8u p5_mc_addr;
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Bit8u p5_mc_type;
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- Bit8u tsc;
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Bit8u cesr;
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Bit8u ctr0;
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Bit8u ctr1;
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retrieving revision 1.81
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diff -u -r1.81 cpu.h
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--- cpu/cpu.h 25 Sep 2002 14:09:08 -0000 1.81
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+++ cpu/cpu.h 26 Sep 2002 02:11:08 -0000
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@@ -582,9 +582,15 @@
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#endif // #if BX_CPU_LEVEL >= 4
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#if BX_CPU_LEVEL >= 5
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-typedef struct {
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Bit64u apicbase;
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+ // TSC: Time Stamp Counter
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@ -52,7 +49,7 @@ diff -u -r1.78 cpu.h
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#if BX_SUPPORT_X86_64
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// x86-64 EFER bits
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Boolean sce;
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@@ -1386,6 +1392,10 @@
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@@ -1390,6 +1396,10 @@
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#if BX_CPU_LEVEL >= 5
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bx_regs_msr_t msr;
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@ -69,7 +66,7 @@ RCS file: /cvsroot/bochs/bochs/cpu/init.cc,v
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retrieving revision 1.32
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diff -u -r1.32 init.cc
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--- cpu/init.cc 22 Sep 2002 18:22:24 -0000 1.32
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+++ cpu/init.cc 25 Sep 2002 02:59:02 -0000
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+++ cpu/init.cc 26 Sep 2002 02:11:09 -0000
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@@ -818,6 +818,9 @@
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/* initialise MSR registers to defaults */
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@ -83,10 +80,10 @@ diff -u -r1.32 init.cc
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Index: cpu/proc_ctrl.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/proc_ctrl.cc,v
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retrieving revision 1.50
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diff -u -r1.50 proc_ctrl.cc
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--- cpu/proc_ctrl.cc 24 Sep 2002 13:57:37 -0000 1.50
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+++ cpu/proc_ctrl.cc 25 Sep 2002 02:59:04 -0000
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retrieving revision 1.51
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diff -u -r1.51 proc_ctrl.cc
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--- cpu/proc_ctrl.cc 25 Sep 2002 14:09:08 -0000 1.51
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+++ cpu/proc_ctrl.cc 26 Sep 2002 02:11:11 -0000
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@@ -1644,6 +1644,20 @@
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#endif
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}
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