- i440fx structure is now a private member of bx_pci_c
- PCI configuration space of the host bridge renamed from array[] to pci_conf[] - new functions load_ROM() and mem_read() for ROM access - macros for PCI functions defined in bochs.h
This commit is contained in:
Volker Ruppert
parent
16f04b12f0
commit
46093f8a88
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: bochs.h,v 1.75 2002-08-09 06:16:42 vruppert Exp $
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// $Id: bochs.h,v 1.76 2002-08-17 09:23:42 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -153,6 +153,11 @@ extern "C" {
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BX_MEM(0)->read_physical(BX_CPU(0), phy_addr, len, ptr)
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#define BX_MEM_WRITE_PHYSICAL(addr, len, ptr) \
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BX_MEM(0)->write_physical(BX_CPU(0), phy_addr, len, ptr)
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// macros for PCI handling
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#define BX_REGISTER_PCI_HANDLERS(this_ptr, pci_read, pci_write, devfunc, name) \
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bx_pci.register_pci_handlers(this_ptr, pci_read, pci_write, devfunc, name)
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#define BX_PCI_LOAD_ROM(fd, offset, size) bx_pci.load_ROM(fd, offset, size)
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#define BX_PCI_MEM_READ(offset) bx_pci.mem_read(offset)
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#if BX_SMP_PROCESSORS==1
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#define BX_CPU(x) (&bx_cpu)
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pci.cc,v 1.16 2002-08-05 17:43:25 vruppert Exp $
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// $Id: pci.cc,v 1.17 2002-08-17 09:23:42 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -92,17 +92,17 @@ bx_pci_c::init(bx_devices_c *d)
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d->register_io_write_handler(this, write_handler, i, "i440FX");
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}
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BX_PCI_THIS register_pci_handlers(this, pci_read_handler, pci_write_handler,
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0x00, "440FX Host bridge");
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BX_REGISTER_PCI_HANDLERS(this, pci_read_handler, pci_write_handler,
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0x00, "440FX Host bridge");
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for (unsigned i=0; i<256; i++)
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BX_PCI_THIS s.i440fx.array[i] = 0x0;
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BX_PCI_THIS s.i440fx.pci_conf[i] = 0x0;
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// readonly registers
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BX_PCI_THIS s.i440fx.array[0x00] = 0x86;
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BX_PCI_THIS s.i440fx.array[0x01] = 0x80;
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BX_PCI_THIS s.i440fx.array[0x02] = 0x37;
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BX_PCI_THIS s.i440fx.array[0x03] = 0x12;
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BX_PCI_THIS s.i440fx.array[0x0b] = 0x06;
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BX_PCI_THIS s.i440fx.pci_conf[0x00] = 0x86;
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BX_PCI_THIS s.i440fx.pci_conf[0x01] = 0x80;
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BX_PCI_THIS s.i440fx.pci_conf[0x02] = 0x37;
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BX_PCI_THIS s.i440fx.pci_conf[0x03] = 0x12;
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BX_PCI_THIS s.i440fx.pci_conf[0x0b] = 0x06;
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}
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}
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@ -112,23 +112,23 @@ bx_pci_c::reset(void)
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BX_PCI_THIS s.i440fx.confAddr = 0;
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BX_PCI_THIS s.i440fx.confData = 0;
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BX_PCI_THIS s.i440fx.array[0x04] = 0x06;
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BX_PCI_THIS s.i440fx.array[0x05] = 0x00;
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BX_PCI_THIS s.i440fx.array[0x06] = 0x80;
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BX_PCI_THIS s.i440fx.array[0x07] = 0x02;
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BX_PCI_THIS s.i440fx.array[0x0d] = 0x00;
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BX_PCI_THIS s.i440fx.array[0x0f] = 0x00;
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BX_PCI_THIS s.i440fx.array[0x50] = 0x00;
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BX_PCI_THIS s.i440fx.array[0x51] = 0x01;
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BX_PCI_THIS s.i440fx.array[0x52] = 0x00;
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BX_PCI_THIS s.i440fx.array[0x53] = 0x80;
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BX_PCI_THIS s.i440fx.array[0x54] = 0x00;
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BX_PCI_THIS s.i440fx.array[0x55] = 0x00;
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BX_PCI_THIS s.i440fx.array[0x56] = 0x00;
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BX_PCI_THIS s.i440fx.array[0x57] = 0x01;
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BX_PCI_THIS s.i440fx.array[0x58] = 0x10;
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BX_PCI_THIS s.i440fx.pci_conf[0x04] = 0x06;
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BX_PCI_THIS s.i440fx.pci_conf[0x05] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x06] = 0x80;
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BX_PCI_THIS s.i440fx.pci_conf[0x07] = 0x02;
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BX_PCI_THIS s.i440fx.pci_conf[0x0d] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x0f] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x50] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x51] = 0x01;
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BX_PCI_THIS s.i440fx.pci_conf[0x52] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x53] = 0x80;
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BX_PCI_THIS s.i440fx.pci_conf[0x54] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x55] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x56] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x57] = 0x01;
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BX_PCI_THIS s.i440fx.pci_conf[0x58] = 0x10;
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for (unsigned i=0x59; i<0x60; i++)
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BX_PCI_THIS s.i440fx.array[i] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[i] = 0x00;
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}
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@ -285,7 +285,7 @@ bx_pci_c::pci_read(Bit8u address, unsigned io_len)
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Bit32u val440fx = 0;
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if (io_len <= 4) {
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memcpy(&val440fx, &BX_PCI_THIS s.i440fx.array[address], io_len);
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memcpy(&val440fx, &BX_PCI_THIS s.i440fx.pci_conf[address], io_len);
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BX_DEBUG(("440FX PMC read register 0x%02x value 0x%08x", address, val440fx));
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return val440fx;
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}
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@ -323,7 +323,7 @@ bx_pci_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
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case 0x0c:
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break;
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default:
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BX_PCI_THIS s.i440fx.array[address+i] = value8;
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BX_PCI_THIS s.i440fx.pci_conf[address+i] = value8;
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BX_DEBUG(("440FX PMC write register 0x%02x value 0x%02x", address,
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value8));
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}
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@ -367,38 +367,38 @@ bx_pci_c::rd_memType (Bit32u addr)
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{
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switch ((addr & 0xFC000) >> 12) {
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case 0xC0:
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return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5A] & 0x3));
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return (mapRead ( BX_PCI_THIS s.i440fx.pci_conf[0x5A] & 0x3));
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case 0xC4:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5A] >> 4) & 0x3));
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return (mapRead ( (BX_PCI_THIS s.i440fx.pci_conf[0x5A] >> 4) & 0x3));
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case 0xC8:
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return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5B] & 0x3));
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return (mapRead ( BX_PCI_THIS s.i440fx.pci_conf[0x5B] & 0x3));
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case 0xCC:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5B] >> 4) & 0x3));
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return (mapRead ( (BX_PCI_THIS s.i440fx.pci_conf[0x5B] >> 4) & 0x3));
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case 0xD0:
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return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5C] & 0x3));
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return (mapRead ( BX_PCI_THIS s.i440fx.pci_conf[0x5C] & 0x3));
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case 0xD4:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 4) & 0x3));
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return (mapRead ( (BX_PCI_THIS s.i440fx.pci_conf[0x5C] >> 4) & 0x3));
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case 0xD8:
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return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5D] & 0x3));
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return (mapRead ( BX_PCI_THIS s.i440fx.pci_conf[0x5D] & 0x3));
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case 0xDC:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5D] >> 4) & 0x3));
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return (mapRead ( (BX_PCI_THIS s.i440fx.pci_conf[0x5D] >> 4) & 0x3));
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case 0xE0:
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return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5E] & 0x3));
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return (mapRead ( BX_PCI_THIS s.i440fx.pci_conf[0x5E] & 0x3));
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case 0xE4:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5E] >> 4) & 0x3));
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return (mapRead ( (BX_PCI_THIS s.i440fx.pci_conf[0x5E] >> 4) & 0x3));
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case 0xE8:
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return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5F] & 0x3));
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return (mapRead ( BX_PCI_THIS s.i440fx.pci_conf[0x5F] & 0x3));
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case 0xEC:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5F] >> 4) & 0x3));
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return (mapRead ( (BX_PCI_THIS s.i440fx.pci_conf[0x5F] >> 4) & 0x3));
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case 0xF0:
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case 0xF4:
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case 0xF8:
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case 0xFC:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x59] >> 4) & 0x3));
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return (mapRead ( (BX_PCI_THIS s.i440fx.pci_conf[0x59] >> 4) & 0x3));
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default:
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BX_PANIC(("rd_memType () Error: Memory Type not known !"));
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@ -413,38 +413,38 @@ bx_pci_c::wr_memType (Bit32u addr)
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{
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switch ((addr & 0xFC000) >> 12) {
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case 0xC0:
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return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5A] & 0x3));
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return (mapWrite ( BX_PCI_THIS s.i440fx.pci_conf[0x5A] & 0x3));
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case 0xC4:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5A] >> 4) & 0x3));
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return (mapWrite ( (BX_PCI_THIS s.i440fx.pci_conf[0x5A] >> 4) & 0x3));
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case 0xC8:
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return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5B] & 0x3));
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return (mapWrite ( BX_PCI_THIS s.i440fx.pci_conf[0x5B] & 0x3));
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case 0xCC:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5B] >> 4) & 0x3));
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return (mapWrite ( (BX_PCI_THIS s.i440fx.pci_conf[0x5B] >> 4) & 0x3));
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case 0xD0:
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return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5C] & 0x3));
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return (mapWrite ( BX_PCI_THIS s.i440fx.pci_conf[0x5C] & 0x3));
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case 0xD4:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 4) & 0x3));
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return (mapWrite ( (BX_PCI_THIS s.i440fx.pci_conf[0x5C] >> 4) & 0x3));
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case 0xD8:
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return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5D] & 0x3));
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return (mapWrite ( BX_PCI_THIS s.i440fx.pci_conf[0x5D] & 0x3));
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case 0xDC:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5D] >> 4) & 0x3));
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return (mapWrite ( (BX_PCI_THIS s.i440fx.pci_conf[0x5D] >> 4) & 0x3));
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case 0xE0:
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return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5E] & 0x3));
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return (mapWrite ( BX_PCI_THIS s.i440fx.pci_conf[0x5E] & 0x3));
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case 0xE4:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5E] >> 4) & 0x3));
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return (mapWrite ( (BX_PCI_THIS s.i440fx.pci_conf[0x5E] >> 4) & 0x3));
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case 0xE8:
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return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5F] & 0x3));
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return (mapWrite ( BX_PCI_THIS s.i440fx.pci_conf[0x5F] & 0x3));
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case 0xEC:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5F] >> 4) & 0x3));
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return (mapWrite ( (BX_PCI_THIS s.i440fx.pci_conf[0x5F] >> 4) & 0x3));
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case 0xF0:
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case 0xF4:
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case 0xF8:
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case 0xFC:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x59] >> 4) & 0x3));
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return (mapWrite ( (BX_PCI_THIS s.i440fx.pci_conf[0x59] >> 4) & 0x3));
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default:
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BX_PANIC(("wr_memType () Error: Memory Type not known !"));
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@ -463,11 +463,11 @@ bx_pci_c::print_i440fx_state()
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#ifdef DUMP_FULL_I440FX
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for (i=0; i<256; i++) {
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BX_DEBUG(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.array[i] ));
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BX_DEBUG(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.pci_conf[i] ));
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}
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#else /* DUMP_FULL_I440FX */
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for (i=0x59; i<0x60; i++) {
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BX_DEBUG(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.array[i] ));
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BX_DEBUG(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.pci_conf[i] ));
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}
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#endif /* DUMP_FULL_I440FX */
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}
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@ -491,6 +491,17 @@ bx_pci_c::i440fx_fetch_ptr(Bit32u addr)
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return (&BX_PCI_THIS devices->mem->vector[addr]);
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}
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int
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bx_pci_c::load_ROM(int fd, Bit32u offset, Bit32u size)
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{
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return read(fd, (bx_ptr_t) &bx_pci.s.i440fx.shadow[offset], size);
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}
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Bit8u
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bx_pci_c::mem_read(Bit32u offset)
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{
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return (BX_PCI_THIS s.i440fx.shadow[offset]);
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}
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Boolean
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bx_pci_c::register_pci_handlers( void *this_ptr, bx_pci_read_handler_t f1,
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pci.h,v 1.6 2002-05-30 07:33:48 vruppert Exp $
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// $Id: pci.h,v 1.7 2002-08-17 09:23:42 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -44,7 +44,7 @@ typedef void (*bx_pci_write_handler_t)(void *, Bit8u, Bit32u, unsigned);
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typedef struct {
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Bit32u confAddr;
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Bit32u confData;
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Bit8u array[256];
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Bit8u pci_conf[256];
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Bit8u shadow[4*16*4096]; // 256k of memory
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} bx_def440fx_t;
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@ -64,10 +64,8 @@ public:
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BX_PCI_SMF Bit32u rd_memType (Bit32u addr);
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BX_PCI_SMF Bit32u wr_memType (Bit32u addr);
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BX_PCI_SMF Bit8u* i440fx_fetch_ptr(Bit32u addr);
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struct {
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bx_def440fx_t i440fx;
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} s;
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BX_PCI_SMF int load_ROM(int fd, Bit32u offset, Bit32u size);
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BX_PCI_SMF Bit8u mem_read(Bit32u offset);
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private:
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bx_devices_c *devices;
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@ -80,6 +78,10 @@ private:
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} pci_handler[BX_MAX_PCI_DEVICES];
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unsigned num_pci_handles;
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struct {
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bx_def440fx_t i440fx;
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} s;
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static Bit32u read_handler(void *this_ptr, Bit32u address, unsigned io_len);
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static void write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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static Bit32u pci_read_handler(void *this_ptr, Bit8u address, unsigned io_len);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: memory.cc,v 1.15 2002-06-06 23:03:09 yakovlev Exp $
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// $Id: memory.cc,v 1.16 2002-08-17 09:23:42 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -245,8 +245,7 @@ inc_one:
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goto inc_one;
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case 0x1: // Writes to ROM, Inhibit
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// bx_pci.s.i440fx.shadow[(a20addr - 0xc0000)] = *data_ptr;
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// BX_INFO(("Writing to ROM %08x, Data %02x ! ", (unsigned) a20addr, *data_ptr));
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BX_DEBUG(("Write to ROM ignored: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
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goto inc_one;
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default:
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BX_PANIC(("write_physical: default case"));
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@ -478,7 +477,7 @@ inc_one:
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goto inc_one;
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case 0x1: // Read from ROM
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*data_ptr = bx_pci.s.i440fx.shadow[(a20addr - 0xc0000)];
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*data_ptr = BX_PCI_MEM_READ(a20addr - 0xc0000);
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//BX_INFO(("Reading from ROM %08x, Data %02x ", (unsigned) a20addr, *data_ptr));
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goto inc_one;
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default:
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@ -558,7 +557,7 @@ inc_one:
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break;
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case 0x1: // Read from Shadow RAM
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*data_ptr = bx_pci.s.i440fx.shadow[(a20addr - 0xc0000)];
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*data_ptr = BX_PCI_MEM_READ(a20addr - 0xc0000);
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BX_INFO(("Reading from ShadowRAM %08x, Data %02x ", (unsigned) a20addr, *data_ptr));
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break;
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default:
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||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: misc_mem.cc,v 1.20 2002-07-03 17:13:29 mlerwill Exp $
|
||||
// $Id: misc_mem.cc,v 1.21 2002-08-17 09:23:42 vruppert Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -90,7 +90,7 @@ BX_MEM_C::~BX_MEM_C(void)
|
||||
void
|
||||
BX_MEM_C::init_memory(int memsize)
|
||||
{
|
||||
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.20 2002-07-03 17:13:29 mlerwill Exp $"));
|
||||
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.21 2002-08-17 09:23:42 vruppert Exp $"));
|
||||
// you can pass 0 if memory has been allocated already through
|
||||
// the constructor, or the desired size of memory if it hasn't
|
||||
|
||||
@ -158,12 +158,10 @@ BX_MEM_C::load_ROM(const char *path, Bit32u romaddress)
|
||||
while (size > 0) {
|
||||
#if BX_PCI_SUPPORT
|
||||
if (bx_options.Oi440FXSupport->get ())
|
||||
ret = read(fd, (bx_ptr_t) &bx_pci.s.i440fx.shadow[romaddress - 0xC0000 + offset],
|
||||
size);
|
||||
ret = BX_PCI_LOAD_ROM(fd, (romaddress - 0xC0000 + offset), size);
|
||||
else
|
||||
ret = read(fd, (bx_ptr_t) &BX_MEM_THIS vector[romaddress + offset], size);
|
||||
#else
|
||||
ret = read(fd, (bx_ptr_t) &BX_MEM_THIS vector[romaddress + offset], size);
|
||||
ret = read(fd, (bx_ptr_t) &BX_MEM_THIS vector[romaddress + offset], size);
|
||||
#endif
|
||||
if (ret <= 0) {
|
||||
BX_PANIC(( "ROM: read failed on BIOS image: '%s'",path));
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user