From 4470c6a1c8959181c321a0cb83e163f093a1c9c8 Mon Sep 17 00:00:00 2001 From: Stanislav Shwartsman Date: Fri, 13 Mar 2009 18:48:08 +0000 Subject: [PATCH] make ICACHE always enabled option and deprecate it in the configure script Trace cache still can be turned off --- bochs/CHANGES | 7 +++-- bochs/config.h.in | 5 ---- bochs/configure | 62 ++++++++++++---------------------------- bochs/configure.in | 39 +++++++------------------ bochs/cpu/access.cc | 4 +-- bochs/cpu/access32.cc | 28 +----------------- bochs/cpu/access64.cc | 28 +----------------- bochs/cpu/cpu.cc | 15 +--------- bochs/cpu/cpu.h | 14 ++------- bochs/cpu/icache.cc | 60 ++++++++++++++++++-------------------- bochs/cpu/icache.h | 6 +--- bochs/cpu/init.cc | 4 +-- bochs/cpu/proc_ctrl.cc | 12 +------- bochs/load32bitOShack.cc | 11 +++---- bochs/main.cc | 3 +- bochs/memory/memory.cc | 4 +-- bochs/pc_system.cc | 9 +----- 17 files changed, 80 insertions(+), 231 deletions(-) diff --git a/bochs/CHANGES b/bochs/CHANGES index bddcdeb09..ef23730ac 100644 --- a/bochs/CHANGES +++ b/bochs/CHANGES @@ -47,8 +47,11 @@ Detailed change log : the code. - Added ability to choose Bochs log file name and Bochs debugger log file name from Bochs command line (using new -log and -dbglog options) - - Removed --enable-guest2host-tlb configure option. The option will be - always enabled for any Bochs configuration. + - Removed --enable-guest2host-tlb configure option. The option is always + enabled for any Bochs configuration. + - Removed --enable-icache configure option. The option is always enabled + for any Bochs configuration. Trace cache support still remains optional + and could be configured off. - Added configure option to compile in GUI frontend for Bochs debugger, to enable configure with --enable-debugger-gui option. The GUI debugger frontend is enabled by default with Bochs debugger. diff --git a/bochs/config.h.in b/bochs/config.h.in index 067d2049c..7005ebc44 100644 --- a/bochs/config.h.in +++ b/bochs/config.h.in @@ -731,13 +731,8 @@ typedef #define BX_SupportRepeatSpeedups 0 #define BX_SupportHostAsms 0 -#define BX_SUPPORT_ICACHE 0 #define BX_SUPPORT_TRACE_CACHE 0 -#if (BX_SUPPORT_TRACE_CACHE && BX_SUPPORT_ICACHE==0) - #error Trace cache optimization cannot be compiled without iCache! -#endif - #if BX_SUPPORT_3DNOW #define BX_CPU_VENDOR_INTEL 0 #else diff --git a/bochs/configure b/bochs/configure index e64b9f8e0..913d814e1 100755 --- a/bochs/configure +++ b/bochs/configure @@ -1569,7 +1569,6 @@ Optional Features: --enable-mtrr support for MTRRs --enable-repeat-speedups support repeated IO and mem copy speedups --enable-trace-cache support instruction trace cache - --enable-icache support instruction cache --enable-fast-function-calls support for fast function calls (gcc on x86 only) --enable-host-specific-asms support for host specific inline assembly --enable-configurable-msrs support for configurable MSR registers @@ -1613,6 +1612,7 @@ Optional Features: --enable-docbook build the Docbook documentation --enable-xpm enable the check for XPM support --enable-guest2host-tlb enables guest to host addr TLB for speed (deprecated) + --enable-icache support instruction cache (deprecated) --enable-external-debugger enables external debugger interface (deprecated) --enable-magic-breakpoints enables magic breakpoints (deprecated) --enable-save-restore enables save/restore (deprecated) @@ -34739,29 +34739,6 @@ echo "${ECHO_T}no" >&6; } fi -{ echo "$as_me:$LINENO: checking for instruction cache support" >&5 -echo $ECHO_N "checking for instruction cache support... $ECHO_C" >&6; } -# Check whether --enable-icache was given. -if test "${enable_icache+set}" = set; then - enableval=$enable_icache; if test "$enableval" = yes; then - { echo "$as_me:$LINENO: result: yes" >&5 -echo "${ECHO_T}yes" >&6; } - speedup_iCache=1 - else - { echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6; } - speedup_iCache=0 - fi -else - - { echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6; } - speedup_iCache=0 - - -fi - - { echo "$as_me:$LINENO: checking for gcc fast function calls optimization" >&5 echo $ECHO_N "checking for gcc fast function calls optimization... $ECHO_C" >&6; } # Check whether --enable-fast-function-calls was given. @@ -35147,17 +35124,10 @@ fi if test "$speedups_all" = 1; then # Configure requested to force all options enabled. speedup_repeat=1 - speedup_iCache=1 speedup_TraceCache=1 speedup_fastcall=1 fi -if test "$speedup_iCache" = 0 -a "$speedup_TraceCache" = 1; then - { { echo "$as_me:$LINENO: error: iCache is required to compile with trace cache optimization" >&5 -echo "$as_me: error: iCache is required to compile with trace cache optimization" >&2;} - { (exit 1); exit 1; }; } -fi - if test "$speedup_repeat" = 1; then cat >>confdefs.h <<\_ACEOF #define BX_SupportRepeatSpeedups 1 @@ -35170,18 +35140,6 @@ _ACEOF fi -if test "$speedup_iCache" = 1; then - cat >>confdefs.h <<\_ACEOF -#define BX_SUPPORT_ICACHE 1 -_ACEOF - -else - cat >>confdefs.h <<\_ACEOF -#define BX_SUPPORT_ICACHE 0 -_ACEOF - -fi - if test "$speedup_host_specific_asms" = 1; then cat >>confdefs.h <<\_ACEOF #define BX_SupportHostAsms 1 @@ -39528,6 +39486,24 @@ echo "${ECHO_T}no" >&6; } fi +{ echo "$as_me:$LINENO: checking for instruction cache support (deprecated)" >&5 +echo $ECHO_N "checking for instruction cache support (deprecated)... $ECHO_C" >&6; } +# Check whether --enable-icache was given. +if test "${enable_icache+set}" = set; then + enableval=$enable_icache; { echo "$as_me:$LINENO: result: $enableval" >&5 +echo "${ECHO_T}$enableval" >&6; } + { { echo "$as_me:$LINENO: error: DEPRECATED - ALWAYS ON" >&5 +echo "$as_me: error: DEPRECATED - ALWAYS ON" >&2;} + { (exit 1); exit 1; }; } + +else + + { echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6; } + +fi + + { echo "$as_me:$LINENO: checking for external debugger interface (deprecated)" >&5 echo $ECHO_N "checking for external debugger interface (deprecated)... $ECHO_C" >&6; } # Check whether --enable-external-debugger was given. diff --git a/bochs/configure.in b/bochs/configure.in index 097e2d873..f9bde01f8 100644 --- a/bochs/configure.in +++ b/bochs/configure.in @@ -2,7 +2,7 @@ dnl // Process this file with autoconf to produce a configure script. AC_PREREQ(2.50) AC_INIT(bochs.h) -AC_REVISION([[$Id: configure.in,v 1.392 2009-03-10 19:33:03 vruppert Exp $]]) +AC_REVISION([[$Id: configure.in,v 1.393 2009-03-13 18:48:08 sshwarts Exp $]]) AC_CONFIG_HEADER(config.h) AC_CONFIG_HEADER(ltdlconf.h) @@ -1088,22 +1088,6 @@ AC_ARG_ENABLE(trace-cache, ] ) -AC_MSG_CHECKING(for instruction cache support) -AC_ARG_ENABLE(icache, - [ --enable-icache support instruction cache], - [if test "$enableval" = yes; then - AC_MSG_RESULT(yes) - speedup_iCache=1 - else - AC_MSG_RESULT(no) - speedup_iCache=0 - fi], - [ - AC_MSG_RESULT(no) - speedup_iCache=0 - ] - ) - AC_MSG_CHECKING(for gcc fast function calls optimization) AC_ARG_ENABLE(fast-function-calls, [ --enable-fast-function-calls support for fast function calls (gcc on x86 only)], @@ -1341,27 +1325,16 @@ AC_ARG_ENABLE(all-optimizations, if test "$speedups_all" = 1; then # Configure requested to force all options enabled. speedup_repeat=1 - speedup_iCache=1 speedup_TraceCache=1 speedup_fastcall=1 fi -if test "$speedup_iCache" = 0 -a "$speedup_TraceCache" = 1; then - AC_MSG_ERROR([iCache is required to compile with trace cache optimization]) -fi - if test "$speedup_repeat" = 1; then AC_DEFINE(BX_SupportRepeatSpeedups, 1) else AC_DEFINE(BX_SupportRepeatSpeedups, 0) fi -if test "$speedup_iCache" = 1; then - AC_DEFINE(BX_SUPPORT_ICACHE, 1) -else - AC_DEFINE(BX_SUPPORT_ICACHE, 0) -fi - if test "$speedup_host_specific_asms" = 1; then AC_DEFINE(BX_SupportHostAsms, 1) else @@ -3074,6 +3047,16 @@ AC_ARG_ENABLE(guest2host-tlb, AC_MSG_RESULT(no) ]) +AC_MSG_CHECKING(for instruction cache support (deprecated)) +AC_ARG_ENABLE(icache, + [ --enable-icache support instruction cache (deprecated)], + [AC_MSG_RESULT($enableval) + AC_MSG_ERROR([DEPRECATED - ALWAYS ON]) + ], + [ + AC_MSG_RESULT(no) + ]) + AC_MSG_CHECKING(for external debugger interface (deprecated)) AC_ARG_ENABLE(external-debugger, [ --enable-external-debugger enables external debugger interface (deprecated)], diff --git a/bochs/cpu/access.cc b/bochs/cpu/access.cc index f3924f753..ac01cbb8f 100644 --- a/bochs/cpu/access.cc +++ b/bochs/cpu/access.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: access.cc,v 1.123 2009-03-05 17:48:12 sshwarts Exp $ +// $Id: access.cc,v 1.124 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -367,9 +367,7 @@ BX_CPU_C::v2h_write_byte(bx_address laddr, bx_bool user) bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif return hostAddr; } } diff --git a/bochs/cpu/access32.cc b/bochs/cpu/access32.cc index d8b0e7e87..9756ca556 100755 --- a/bochs/cpu/access32.cc +++ b/bochs/cpu/access32.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: access32.cc,v 1.24 2009-02-26 21:56:53 sshwarts Exp $ +// $Id: access32.cc,v 1.25 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (c) 2008 Stanislav Shwartsman @@ -52,9 +52,7 @@ accessOK: BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, CPL, BX_WRITE, (Bit8u*) &data); Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif *hostAddr = data; return; } @@ -103,9 +101,7 @@ accessOK: BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, CPL, BX_WRITE, (Bit8u*) &data); Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostWordToLittleEndian(hostAddr, data); return; } @@ -164,9 +160,7 @@ accessOK: BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, CPL, BX_WRITE, (Bit8u*) &data); Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostDWordToLittleEndian(hostAddr, data); return; } @@ -225,9 +219,7 @@ accessOK: BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, CPL, BX_WRITE, (Bit8u*) &data); Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostQWordToLittleEndian(hostAddr, data); return; } @@ -284,9 +276,7 @@ accessOK: BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, CPL, BX_WRITE, (Bit8u*) data); Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostQWordToLittleEndian(hostAddr, data->xmm64u(0)); WriteHostQWordToLittleEndian(hostAddr+1, data->xmm64u(1)); return; @@ -333,9 +323,7 @@ accessOK: BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, CPL, BX_WRITE, (Bit8u*) data); Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostQWordToLittleEndian(hostAddr, data->xmm64u(0)); WriteHostQWordToLittleEndian(hostAddr+1, data->xmm64u(1)); return; @@ -710,9 +698,7 @@ accessOK: bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif data = *hostAddr; BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr; BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_RW); @@ -763,9 +749,7 @@ accessOK: bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif ReadHostWordFromLittleEndian(hostAddr, data); BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr; BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_RW); @@ -826,9 +810,7 @@ accessOK: bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif ReadHostDWordFromLittleEndian(hostAddr, data); BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr; BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_RW); @@ -889,9 +871,7 @@ accessOK: bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif ReadHostQWordFromLittleEndian(hostAddr, data); BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr; BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_RW); @@ -1099,9 +1079,7 @@ accessOK: BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, curr_pl, BX_WRITE, (Bit8u*) &data); Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostWordToLittleEndian(hostAddr, data); return; } @@ -1160,9 +1138,7 @@ accessOK: BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, curr_pl, BX_WRITE, (Bit8u*) &data); Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostDWordToLittleEndian(hostAddr, data); return; } @@ -1221,9 +1197,7 @@ accessOK: BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, curr_pl, BX_WRITE, (Bit8u*) &data); Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostQWordToLittleEndian(hostAddr, data); return; } diff --git a/bochs/cpu/access64.cc b/bochs/cpu/access64.cc index 188792ac5..29447bdf8 100755 --- a/bochs/cpu/access64.cc +++ b/bochs/cpu/access64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: access64.cc,v 1.23 2009-02-26 21:56:57 sshwarts Exp $ +// $Id: access64.cc,v 1.24 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (c) 2008 Stanislav Shwartsman @@ -49,9 +49,7 @@ BX_CPU_C::write_virtual_byte_64(unsigned s, Bit64u offset, Bit8u data) BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, CPL, BX_WRITE, (Bit8u*) &data); Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif *hostAddr = data; return; } @@ -90,9 +88,7 @@ BX_CPU_C::write_virtual_word_64(unsigned s, Bit64u offset, Bit16u data) BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, CPL, BX_WRITE, (Bit8u*) &data); Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostWordToLittleEndian(hostAddr, data); return; } @@ -140,9 +136,7 @@ BX_CPU_C::write_virtual_dword_64(unsigned s, Bit64u offset, Bit32u data) BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, CPL, BX_WRITE, (Bit8u*) &data); Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostDWordToLittleEndian(hostAddr, data); return; } @@ -190,9 +184,7 @@ BX_CPU_C::write_virtual_qword_64(unsigned s, Bit64u offset, Bit64u data) BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, CPL, BX_WRITE, (Bit8u*) &data); Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostQWordToLittleEndian(hostAddr, data); return; } @@ -236,9 +228,7 @@ BX_CPU_C::write_virtual_dqword_64(unsigned s, Bit64u offset, const BxPackedXmmRe BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, CPL, BX_WRITE, (Bit8u*) data); Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostQWordToLittleEndian(hostAddr, data->xmm64u(0)); WriteHostQWordToLittleEndian(hostAddr+1, data->xmm64u(1)); return; @@ -274,9 +264,7 @@ BX_CPU_C::write_virtual_dqword_aligned_64(unsigned s, Bit64u offset, const BxPac BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, CPL, BX_WRITE, (Bit8u*) data); Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostQWordToLittleEndian(hostAddr, data->xmm64u(0)); WriteHostQWordToLittleEndian(hostAddr+1, data->xmm64u(1)); return; @@ -570,9 +558,7 @@ BX_CPU_C::read_RMW_virtual_byte_64(unsigned s, Bit64u offset) bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif data = *hostAddr; BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr; BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_RW); @@ -613,9 +599,7 @@ BX_CPU_C::read_RMW_virtual_word_64(unsigned s, Bit64u offset) bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif ReadHostWordFromLittleEndian(hostAddr, data); BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr; BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_RW); @@ -665,9 +649,7 @@ BX_CPU_C::read_RMW_virtual_dword_64(unsigned s, Bit64u offset) bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif ReadHostDWordFromLittleEndian(hostAddr, data); BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr; BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_RW); @@ -717,9 +699,7 @@ BX_CPU_C::read_RMW_virtual_qword_64(unsigned s, Bit64u offset) bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif ReadHostQWordFromLittleEndian(hostAddr, data); BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr; BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_RW); @@ -767,9 +747,7 @@ void BX_CPU_C::write_new_stack_word_64(Bit64u laddr, unsigned curr_pl, Bit16u da BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, curr_pl, BX_WRITE, (Bit8u*) &data); Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostWordToLittleEndian(hostAddr, data); return; } @@ -812,9 +790,7 @@ void BX_CPU_C::write_new_stack_dword_64(Bit64u laddr, unsigned curr_pl, Bit32u d BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, curr_pl, BX_WRITE, (Bit8u*) &data); Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostDWordToLittleEndian(hostAddr, data); return; } @@ -857,9 +833,7 @@ void BX_CPU_C::write_new_stack_qword_64(Bit64u laddr, unsigned curr_pl, Bit64u d BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, curr_pl, BX_WRITE, (Bit8u*) &data); Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset); -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); -#endif WriteHostQWordToLittleEndian(hostAddr, data); return; } diff --git a/bochs/cpu/cpu.cc b/bochs/cpu/cpu.cc index aac129919..a831626a6 100644 --- a/bochs/cpu/cpu.cc +++ b/bochs/cpu/cpu.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: cpu.cc,v 1.275 2009-03-13 18:02:33 sshwarts Exp $ +// $Id: cpu.cc,v 1.276 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -38,9 +38,6 @@ #define RCX ECX #endif -// ICACHE instrumentation code -#if BX_SUPPORT_ICACHE - #define InstrumentICACHE 0 #if InstrumentICACHE @@ -59,14 +56,11 @@ static unsigned iCacheMisses=0; } \ } #define InstrICache_Increment(v) (v)++ - #else #define InstrICache_Stats() #define InstrICache_Increment(v) #endif -#endif // BX_SUPPORT_ICACHE - // The CHECK_MAX_INSTRUCTIONS macro allows cpu_loop to execute a few // instructions and then return so that the other processors have a chance to // run. This is used by bochs internal debugger or when simulating @@ -141,7 +135,6 @@ no_async_event: eipBiased = RIP + BX_CPU_THIS_PTR eipPageBias; } -#if BX_SUPPORT_ICACHE bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrPage + eipBiased; bxICacheEntry_c *entry = BX_CPU_THIS_PTR iCache.get_entry(pAddr); bxInstruction_c *i = entry->i; @@ -161,10 +154,6 @@ no_async_event: serveICacheMiss(entry, eipBiased, pAddr); i = entry->i; } -#else - bxInstruction_c iStorage, *i = &iStorage; - fetchInstruction(i, eipBiased); -#endif #if BX_SUPPORT_TRACE_CACHE unsigned length = entry->ilen; @@ -767,13 +756,11 @@ void BX_CPU_C::prefetch(void) } } -#if BX_SUPPORT_ICACHE BX_CPU_THIS_PTR currPageWriteStampPtr = pageWriteStampTable.getPageWriteStampPtr(BX_CPU_THIS_PTR pAddrPage); Bit32u pageWriteStamp = *(BX_CPU_THIS_PTR currPageWriteStampPtr); pageWriteStamp &= ~ICacheWriteStampFetchModeMask; // Clear out old fetch mode bits pageWriteStamp |= BX_CPU_THIS_PTR fetchModeMask; // And add new ones pageWriteStampTable.setPageWriteStamp(BX_CPU_THIS_PTR pAddrPage, pageWriteStamp); -#endif } void BX_CPU_C::boundaryFetch(const Bit8u *fetchPtr, unsigned remainingInPage, bxInstruction_c *i) diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h index 30cb823e9..aa24d43cc 100644 --- a/bochs/cpu/cpu.h +++ b/bochs/cpu/cpu.h @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: cpu.h,v 1.583 2009-03-13 18:26:10 sshwarts Exp $ +// $Id: cpu.h,v 1.584 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -621,10 +621,7 @@ struct cpuid_function_t { #include "descriptor.h" #include "instr.h" #include "lazy_flags.h" - -#if BX_SUPPORT_ICACHE #include "icache.h" -#endif // BX_TLB_SIZE: Number of entries in TLB // BX_TLB_INDEX_OF(lpf): This macro is passed the linear page frame @@ -987,11 +984,9 @@ public: // for now... // An instruction cache. Each entry should be exactly 32 bytes, and // this structure should be aligned on a 32-byte boundary to be friendly // with the host cache lines. -#if BX_SUPPORT_ICACHE bxICache_c iCache BX_CPP_AlignN(32); Bit32u fetchModeMask; const Bit32u *currPageWriteStampPtr; -#endif struct { bx_address rm_addr; // The address offset after resolution @@ -2776,13 +2771,12 @@ public: // for now... #if BX_SUPPORT_X86_64 BX_SMF unsigned fetchDecode64(const Bit8u *fetchPtr, bxInstruction_c *i, unsigned remainingInPage) BX_CPP_AttrRegparmN(3); #endif - BX_SMF bx_bool fetchInstruction(bxInstruction_c *iStorage, Bit32u eipBiased); BX_SMF void boundaryFetch(const Bit8u *fetchPtr, unsigned remainingInPage, bxInstruction_c *); -#if BX_SUPPORT_ICACHE BX_SMF void serveICacheMiss(bxICacheEntry_c *entry, Bit32u eipBiased, bx_phy_address pAddr); #if BX_SUPPORT_TRACE_CACHE BX_SMF bx_bool mergeTraces(bxICacheEntry_c *entry, bxInstruction_c *i, bx_phy_address pAddr); -#endif +#else + BX_SMF bx_bool fetchInstruction(bxInstruction_c *iStorage, Bit32u eipBiased); #endif BX_SMF void prefetch(void); BX_SMF void updateFetchModeMask(void); @@ -3427,13 +3421,11 @@ BX_CPP_INLINE void BX_CPU_C::prepareXSAVE(void) BX_CPP_INLINE void BX_CPU_C::updateFetchModeMask(void) { -#if BX_SUPPORT_ICACHE BX_CPU_THIS_PTR fetchModeMask = #if BX_SUPPORT_X86_64 ((BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)<<31) | #endif (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b << 30); -#endif BX_CPU_THIS_PTR user_pl = // CPL == 3 (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl == 3); diff --git a/bochs/cpu/icache.cc b/bochs/cpu/icache.cc index c39fbb998..b8fed8c23 100755 --- a/bochs/cpu/icache.cc +++ b/bochs/cpu/icache.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: icache.cc,v 1.21 2009-01-16 18:18:58 sshwarts Exp $ +// $Id: icache.cc,v 1.22 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (c) 2007 Stanislav Shwartsman @@ -26,35 +26,6 @@ #include "cpu.h" #define LOG_THIS BX_CPU_THIS_PTR -bx_bool BX_CPU_C::fetchInstruction(bxInstruction_c *iStorage, Bit32u eipBiased) -{ - unsigned remainingInPage = BX_CPU_THIS_PTR eipPageWindowSize - eipBiased; - const Bit8u *fetchPtr = BX_CPU_THIS_PTR eipFetchPtr + eipBiased; - unsigned ret; - -#if BX_SUPPORT_X86_64 - if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) - ret = fetchDecode64(fetchPtr, iStorage, remainingInPage); - else -#endif - ret = fetchDecode32(fetchPtr, iStorage, remainingInPage); - - if (ret==0) { - // handle instrumentation callback inside boundaryFetch - boundaryFetch(fetchPtr, remainingInPage, iStorage); - return 0; - } - -#if BX_INSTRUMENTATION - BX_INSTR_OPCODE(BX_CPU_ID, fetchPtr, iStorage->ilen(), - BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, Is64BitMode()); -#endif - - return 1; -} - -#if BX_SUPPORT_ICACHE - bxPageWriteStampTable pageWriteStampTable; void flushICaches(void) @@ -163,6 +134,33 @@ bx_bool BX_CPU_C::mergeTraces(bxICacheEntry_c *entry, bxInstruction_c *i, bx_phy #else // BX_SUPPORT_TRACE_CACHE == 0 +bx_bool BX_CPU_C::fetchInstruction(bxInstruction_c *iStorage, Bit32u eipBiased) +{ + unsigned remainingInPage = BX_CPU_THIS_PTR eipPageWindowSize - eipBiased; + const Bit8u *fetchPtr = BX_CPU_THIS_PTR eipFetchPtr + eipBiased; + unsigned ret; + +#if BX_SUPPORT_X86_64 + if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) + ret = fetchDecode64(fetchPtr, iStorage, remainingInPage); + else +#endif + ret = fetchDecode32(fetchPtr, iStorage, remainingInPage); + + if (ret==0) { + // handle instrumentation callback inside boundaryFetch + boundaryFetch(fetchPtr, remainingInPage, iStorage); + return 0; + } + +#if BX_INSTRUMENTATION + BX_INSTR_OPCODE(BX_CPU_ID, fetchPtr, iStorage->ilen(), + BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, Is64BitMode()); +#endif + + return 1; +} + void BX_CPU_C::serveICacheMiss(bxICacheEntry_c *cache_entry, Bit32u eipBiased, bx_phy_address pAddr) { // The entry will be marked valid if fetchdecode will succeed @@ -175,5 +173,3 @@ void BX_CPU_C::serveICacheMiss(bxICacheEntry_c *cache_entry, Bit32u eipBiased, b } #endif - -#endif // BX_SUPPORT_ICACHE diff --git a/bochs/cpu/icache.h b/bochs/cpu/icache.h index 5a40db539..e247c7711 100755 --- a/bochs/cpu/icache.h +++ b/bochs/cpu/icache.h @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: icache.h,v 1.43 2009-03-10 16:28:01 sshwarts Exp $ +// $Id: icache.h,v 1.44 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (c) 2007 Stanislav Shwartsman @@ -24,8 +24,6 @@ #ifndef BX_ICACHE_H #define BX_ICACHE_H -#if BX_SUPPORT_ICACHE - // bit31: 1=Long Mode, 0=not Long Mode. // bit30: 1=CS is 32/64-bit, 0=CS is 16-bit. // Combination bit31=1 & bit30=1 is invalid (data page) @@ -199,6 +197,4 @@ BX_CPP_INLINE void bxICache_c::purgeICacheEntries(void) extern void purgeICaches(void); extern void flushICaches(void); -#endif // BX_SUPPORT_ICACHE - #endif diff --git a/bochs/cpu/init.cc b/bochs/cpu/init.cc index 29c6f0ea3..33c5ef671 100644 --- a/bochs/cpu/init.cc +++ b/bochs/cpu/init.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: init.cc,v 1.203 2009-02-20 17:26:01 sshwarts Exp $ +// $Id: init.cc,v 1.204 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -778,9 +778,7 @@ void BX_CPU_C::reset(unsigned source) #endif updateFetchModeMask(); -#if BX_SUPPORT_ICACHE flushICaches(); -#endif /* DS (Data Segment) and descriptor cache */ parse_selector(0x0000, diff --git a/bochs/cpu/proc_ctrl.cc b/bochs/cpu/proc_ctrl.cc index 3991ded4e..59d6a5d2d 100644 --- a/bochs/cpu/proc_ctrl.cc +++ b/bochs/cpu/proc_ctrl.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: proc_ctrl.cc,v 1.290 2009-03-10 22:28:08 sshwarts Exp $ +// $Id: proc_ctrl.cc,v 1.291 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -173,10 +173,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::INVD(bxInstruction_c *i) BX_DEBUG(("INVD: Flush internal caches !")); BX_INSTR_CACHE_CNTRL(BX_CPU_ID, BX_INSTR_INVD); -#if BX_SUPPORT_ICACHE flushICaches(); -#endif - #else BX_INFO(("INVD: required 486 support, use --enable-cpu-level=4 option")); exception(BX_UD_EXCEPTION, 0, 0); @@ -197,10 +194,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::WBINVD(bxInstruction_c *i) BX_DEBUG(("WBINVD: Flush internal caches !")); BX_INSTR_CACHE_CNTRL(BX_CPU_ID, BX_INSTR_WBINVD); -#if BX_SUPPORT_ICACHE flushICaches(); -#endif - #else BX_INFO(("WBINVD: required 486 support, use --enable-cpu-level=4 option")); exception(BX_UD_EXCEPTION, 0, 0); @@ -1240,18 +1234,14 @@ void BX_CPU_C::handleAlignmentCheck(void) if (BX_CPU_THIS_PTR alignment_check_mask == 0) { BX_CPU_THIS_PTR alignment_check_mask = 0xF; BX_INFO(("Enable alignment check (#AC exception)")); -#if BX_SUPPORT_ICACHE BX_CPU_THIS_PTR iCache.flushICacheEntries(); -#endif } } else { if (BX_CPU_THIS_PTR alignment_check_mask != 0) { BX_CPU_THIS_PTR alignment_check_mask = 0; BX_INFO(("Disable alignment check (#AC exception)")); -#if BX_SUPPORT_ICACHE BX_CPU_THIS_PTR iCache.flushICacheEntries(); -#endif } } } diff --git a/bochs/load32bitOShack.cc b/bochs/load32bitOShack.cc index e04e1797f..7b24e040d 100644 --- a/bochs/load32bitOShack.cc +++ b/bochs/load32bitOShack.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: load32bitOShack.cc,v 1.32 2009-01-16 18:18:57 sshwarts Exp $ +// $Id: load32bitOShack.cc,v 1.33 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -246,10 +246,6 @@ void bx_load_null_kernel_hack(void) BX_CPU(0)->sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // page gran BX_CPU(0)->sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1; // 32bit -#if BX_SUPPORT_ICACHE - BX_CPU(0)->updateFetchModeMask(); -#endif - // DS deltas BX_CPU(0)->sregs[BX_SEG_REG_DS].cache.u.segment.base = 0x00000000; BX_CPU(0)->sregs[BX_SEG_REG_DS].cache.u.segment.limit = 0xFFFFF; @@ -259,10 +255,11 @@ void bx_load_null_kernel_hack(void) // CR0 deltas BX_CPU(0)->cr0.set_PE(1); // protected mode + + BX_CPU(0)->handleCpuModeChange(); } - Bit32u -bx_load_kernel_image(char *path, Bit32u paddr) +Bit32u bx_load_kernel_image(char *path, Bit32u paddr) { struct stat stat_buf; int fd, ret; diff --git a/bochs/main.cc b/bochs/main.cc index a71def935..c51d424ae 100644 --- a/bochs/main.cc +++ b/bochs/main.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: main.cc,v 1.393 2009-02-23 11:06:53 vruppert Exp $ +// $Id: main.cc,v 1.394 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2002 MandrakeSoft S.A. @@ -1028,7 +1028,6 @@ void bx_init_hardware() BX_INFO((" VMX support: %s",BX_SUPPORT_VMX?"yes":"no")); BX_INFO(("Optimization configuration")); BX_INFO((" RepeatSpeedups support: %s",BX_SupportRepeatSpeedups?"yes":"no")); - BX_INFO((" Icache support: %s",BX_SUPPORT_ICACHE?"yes":"no")); BX_INFO((" Trace cache support: %s",BX_SUPPORT_TRACE_CACHE?"yes":"no")); BX_INFO((" Fast function calls: %s",BX_FAST_FUNC_CALL?"yes":"no")); BX_INFO(("Devices configuration")); diff --git a/bochs/memory/memory.cc b/bochs/memory/memory.cc index 9193abce4..946809440 100644 --- a/bochs/memory/memory.cc +++ b/bochs/memory/memory.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: memory.cc,v 1.75 2009-02-17 19:20:47 sshwarts Exp $ +// $Id: memory.cc,v 1.76 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -89,9 +89,7 @@ mem_write: // all memory access feets in single 4K page if (a20addr < BX_MEM_THIS len) { -#if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(a20addr); -#endif // all of data is within limits of physical memory if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff)) { diff --git a/bochs/pc_system.cc b/bochs/pc_system.cc index 3041c0047..b3cb220c8 100644 --- a/bochs/pc_system.cc +++ b/bochs/pc_system.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: pc_system.cc,v 1.73 2009-01-16 18:18:57 sshwarts Exp $ +// $Id: pc_system.cc,v 1.74 2009-03-13 18:48:08 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2002 MandrakeSoft S.A. @@ -48,12 +48,7 @@ double m_ips; // Millions of Instructions Per Second #define SpewPeriodicTimerInfo 0 #define MinAllowableTimerPeriod 1 -#if BX_SUPPORT_ICACHE const Bit64u bx_pc_system_c::NullTimerInterval = ICacheWriteStampStart; -#else -// This must be the maximum 32-bit unsigned int value, NOT (Bit64u) -1. -const Bit64u bx_pc_system_c::NullTimerInterval = 0xffffffff; -#endif // constructor bx_pc_system_c::bx_pc_system_c() @@ -418,9 +413,7 @@ void bx_pc_system_c::nullTimer(void* this_ptr) } #endif -#if BX_SUPPORT_ICACHE purgeICaches(); -#endif } void bx_pc_system_c::benchmarkTimer(void* this_ptr)