Changes by me for 2.1
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Changes in 2.1 (July ??, 2003):
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- Stanislav's changes...
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+ Added emulation of AMD 3DNow! instructions set.
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Bochs now could decode all AMD 3DNow! instructions.
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Most of instructions still not implemented, but the basis already presents.
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Configure --enable-3dnow to enable 3DNow! support.
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TODO:
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Close all still not implemented instructions:
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PFPNACC_PqQq, PI2FW_PqQq, PI2FD_PqQq, PF2IW_PqQq, PF2ID_PqQq,
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PFNACC_PqQq, PFCMPGE_PqQq, PFMIN_PqQq, PFRCP_PqQq, PFRSQRT_PqQq,
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PFSUB_PqQq, PFADD_PqQq, PFCMPGT_PqQq, PFMAX_PqQq, PFRCPIT1_PqQq,
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PFRSQIT1_PqQq, PFSUBR_PqQq, PFACC_PqQq, PFCMPEQ_PqQq, PFMUL_PqQq,
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PFRCPIT2_PqQq
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CPUID still could not report 3DNow! instruction set.
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+ Added emulation of SSE/SSE2 floating point instructions
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Alsmost all SSE/SSE2 floating point instructions are fully implemented
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using free softfloat library (including DAZ support and floating point
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exceptions). Correctness of the emulation checked with heavily random
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testing.
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TODO:
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Close 4 last still not implemented instructions:
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RSQRTSS_VssWss, RSQRTPS_VpsWps, RCPPS_VpsWps, RCPSS_VssWss
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+ Fixed: Unallowed lock prefix cases must cause #UD exception
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+ Fixed FXSAVE/FXRSTOR instructions
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+ Fixed fetchdecode bug caused #UD in SYSENTER/SYSEXIT instructions
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in 32bit mode.
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+ Hundreds of bugfixes in FPU emulation after checking of the emulation
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with testfloat. Fixed cases:
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floatx80_to_int32
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floatx80_to_float32
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floatx80_to_float64
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floatx80_round_to_int
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floatx80_add
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floatx80_sub
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floatx80_mul
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floatx80_div
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Thanks to Scott Duplichan for fixing the bugs.
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--------------------------------------------------------------------------
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- Christophe's changes...
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- Volker's changes...
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- Peter's changes...
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- patches by X, Y, and Z were added...
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added rombios patch by Dirk Thierbach
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added rombios patch by Kory Markevich
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I think these already could be committed:
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added disassembler patch by Dirk Thierbach
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added FPU 64-bit addresses patch
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- these S.F. bugs were fixed...
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-------------------------------------------------------------------------
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