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This commit is contained in:
Stanislav Shwartsman 2010-02-25 22:44:46 +00:00
parent 78a420faa1
commit 32e5f1ffc8
3 changed files with 6 additions and 22 deletions
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6
bochs/cpu/cpuid.cc
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@ -1,5 +1,5 @@
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// $Id: cpuid.cc,v 1.90 2010-02-25 22:34:56 sshwarts Exp $ // $Id: cpuid.cc,v 1.91 2010-02-25 22:44:46 sshwarts Exp $
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// //
// Copyright (c) 2007-2009 Stanislav Shwartsman // Copyright (c) 2007-2009 Stanislav Shwartsman
@ -792,7 +792,7 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
} }
if (sse_enabled >= BX_CPUID_SUPPORT_SSE2) { if (sse_enabled >= BX_CPUID_SUPPORT_SSE2) {
if (BX_SUPPORT_XAPIC) { if (! BX_SUPPORT_XAPIC) {
BX_PANIC(("PANIC: SSE2 is enabled and XAPIC is not configured in !")); BX_PANIC(("PANIC: SSE2 is enabled and XAPIC is not configured in !"));
return; return;
} }
@ -806,7 +806,7 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
} }
#if BX_SUPPORT_X86_64 #if BX_SUPPORT_X86_64
if (sse_enabled <= BX_CPUID_SUPPORT_SSE2) { if (sse_enabled < BX_CPUID_SUPPORT_SSE2) {
BX_PANIC(("PANIC: x86-64 emulation requires SSE2 support !")); BX_PANIC(("PANIC: x86-64 emulation requires SSE2 support !"));
return; return;
} }

18
bochs/cpu/fetchdecode.cc
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.253 2010-02-25 22:04:30 sshwarts Exp $ // $Id: fetchdecode.cc,v 1.254 2010-02-25 22:44:46 sshwarts Exp $
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2001-2009 The Bochs Project // Copyright (C) 2001-2009 The Bochs Project
@ -471,11 +471,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F 0A /wr */ { 0, BX_IA_ERROR }, /* 0F 0A /wr */ { 0, BX_IA_ERROR },
/* 0F 0B /wr */ { BxTraceEnd, BX_IA_UD2A }, /* 0F 0B /wr */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /wr */ { 0, BX_IA_ERROR }, /* 0F 0C /wr */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /wr */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel /* 0F 0D /wr */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
#else
/* 0F 0D /wr */ { 0, BX_IA_ERROR },
#endif
/* 0F 0E /wr */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS /* 0F 0E /wr */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
#if BX_SUPPORT_3DNOW #if BX_SUPPORT_3DNOW
/* 0F 0F /wr */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo }, /* 0F 0F /wr */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo },
@ -1026,11 +1022,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F 0A /dr */ { 0, BX_IA_ERROR }, /* 0F 0A /dr */ { 0, BX_IA_ERROR },
/* 0F 0B /dr */ { BxTraceEnd, BX_IA_UD2A }, /* 0F 0B /dr */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /dr */ { 0, BX_IA_ERROR }, /* 0F 0C /dr */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /dr */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel /* 0F 0D /dr */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
#else
/* 0F 0D /dr */ { 0, BX_IA_ERROR },
#endif
/* 0F 0E /dr */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS /* 0F 0E /dr */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
#if BX_SUPPORT_3DNOW #if BX_SUPPORT_3DNOW
/* 0F 0F /dr */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo }, /* 0F 0F /dr */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo },
@ -1588,11 +1580,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F 0A /wm */ { 0, BX_IA_ERROR }, /* 0F 0A /wm */ { 0, BX_IA_ERROR },
/* 0F 0B /wm */ { BxTraceEnd, BX_IA_UD2A }, /* 0F 0B /wm */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /wm */ { 0, BX_IA_ERROR }, /* 0F 0C /wm */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /wm */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel /* 0F 0D /wm */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
#else
/* 0F 0D /wm */ { 0, BX_IA_ERROR },
#endif
/* 0F 0E /wm */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS /* 0F 0E /wm */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
#if BX_SUPPORT_3DNOW #if BX_SUPPORT_3DNOW
/* 0F 0F /wm */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo }, /* 0F 0F /wm */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo },
@ -2143,11 +2131,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F 0A /dm */ { 0, BX_IA_ERROR }, /* 0F 0A /dm */ { 0, BX_IA_ERROR },
/* 0F 0B /dm */ { BxTraceEnd, BX_IA_UD2A }, /* 0F 0B /dm */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /dm */ { 0, BX_IA_ERROR }, /* 0F 0C /dm */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /dm */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel /* 0F 0D /dm */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
#else
/* 0F 0D /dm */ { 0, BX_IA_ERROR },
#endif
/* 0F 0E /dm */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS /* 0F 0E /dm */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
#if BX_SUPPORT_3DNOW #if BX_SUPPORT_3DNOW
/* 0F 0F /dm */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo }, /* 0F 0F /dm */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo },

4
bochs/cpu/ia_opcodes.h
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// $Id: ia_opcodes.h,v 1.39 2010-02-25 22:04:30 sshwarts Exp $ // $Id: ia_opcodes.h,v 1.40 2010-02-25 22:44:46 sshwarts Exp $
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// //
// Copyright (c) 2008-2009 Stanislav Shwartsman // Copyright (c) 2008-2009 Stanislav Shwartsman
@ -858,7 +858,7 @@ bx_define_opcode(BX_IA_PI2FW_PqQq, &BX_CPU_C::PI2FW_PqQq, NULL, BX_CPU_3DNOW)
bx_define_opcode(BX_IA_PMULHRW_PqQq, &BX_CPU_C::PMULHRW_PqQq, NULL, BX_CPU_3DNOW) bx_define_opcode(BX_IA_PMULHRW_PqQq, &BX_CPU_C::PMULHRW_PqQq, NULL, BX_CPU_3DNOW)
bx_define_opcode(BX_IA_PSWAPD_PqQq, &BX_CPU_C::PSWAPD_PqQq, NULL, BX_CPU_3DNOW) bx_define_opcode(BX_IA_PSWAPD_PqQq, &BX_CPU_C::PSWAPD_PqQq, NULL, BX_CPU_3DNOW)
#endif #endif
bx_define_opcode(BX_IA_PREFETCHW, &BX_CPU_C::NOP, NULL, 0) bx_define_opcode(BX_IA_PREFETCHW, &BX_CPU_C::NOP, NULL, BX_CPU_3DNOW | BX_CPU_X86_64)
// P6 new instructions // P6 new instructions
bx_define_opcode(BX_IA_FXSAVE, &BX_CPU_C::FXSAVE, NULL, BX_CPU_P6) bx_define_opcode(BX_IA_FXSAVE, &BX_CPU_C::FXSAVE, NULL, BX_CPU_P6)