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- WLI separated his patch into 8 cpu support and workarounds. I checked

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in the 8 cpu support changes.  These are the workarounds.
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Bryce Denney 2002-04-08 02:03:08 +00:00
parent 45b49fe35f
commit 327e7742d2
1 changed files with 8 additions and 203 deletions
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bochs/patches/patch.smp-8cpu-etc
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@ -1,212 +1,17 @@
From wli@holomorphy.com Fri Apr 5 13:32:54 2002 From wli@holomorphy.com Sun Apr 7 21:59:35 2002
Date: Fri, 5 Apr 2002 02:36:43 -0800 Date: Sun, 7 Apr 2002 18:07:38 -0700
From: William Lee Irwin III <wli@holomorphy.com> From: William Lee Irwin III <wli@holomorphy.com>
To: bochs-developers@lists.sourceforge.net To: bochs-developers@lists.sourceforge.net
Subject: [Bochs-developers] 05_8_cpus Subject: [Bochs-developers] 06_8_cpu_workarounds
These are all fairly trivial patches; essentially aside from minor Here's a patch with the workarounds for 8 cpu's I used on top of
#defined limitations and some table setup for interacting with the reverting keyboard changes... looks like keyboard changes are getting
OS this works pretty much out of the box. keyboard.cc changes fixed up pretty soon here so that will not be necessary for long.
reverted as usual for Linux compatibility.
A few minor things came up while testing the thing, which are addressed Cheers,
along with the defines and table setups in the following patch. Bill
configure.in:
Add a case for 8 cpu's.
rombios.c:
Add an MP table for 8 cpu's.
apic.cc:
Handle a strange boundary case tripped by setting something
to an APIC ID it already possesses.
cpu.cc:
Assign either 0 or 1 to is_32, which is a Bool. The value
appeared to resemble a stack address, which is probably a
sign of a deeper problem and interacted poorly with
fetchdecode.cc's array index arithmetic (in fact raising
an exception within the simulator itself).
cpu.h:
(A) make as_32 and os_32 booleans, to (hopefully) prevent
similar problems as with is_32.
(B) #define APIC_MAX_ID to 32. Any higher than this and
poor interactions with 32-bit APIC ID bitmasks begin to
occur; larger bitmasks may well be in order esp. if these
are considered physical or clustered APIC ID's.
ioapic.cc:
Avoid truncation of ioapic's physical APIC ID so as to
prevent clashes of I/O APIC ID's with local APIC ID's
This is compatible with flat logical destination modes
of APICs because I/O apics are never worthwhile destinations
for IPI's, so its non-addressibility in flat logical mode
is inconsequential. It's unclear with which version of the
I/O APIC this is compatible given the usual limitations on
the number(s) of bits involved, but essentially this appears
to work around some problems I've seen arising when the I/O
APIC's ID clashes with a CPU's local APIC ID by assigning the
I/O APIC an ID distinct from all cpus' while leaving all APIC
ID's addressible in flat logical mode available for local APICs.
Index: configure.in
===================================================================
RCS file: /cvsroot/bochs/bochs/configure.in,v
retrieving revision 1.78
diff -u -r1.78 configure.in
--- configure.in 28 Mar 2002 09:43:07 -0000 1.78
+++ configure.in 5 Apr 2002 10:17:15 -0000
@@ -236,6 +236,13 @@
AC_DEFINE(BX_IOAPIC_DEFAULT_ID, 4)
AC_DEFINE(BX_USE_CPU_SMF, 0)
;;
+ 8)
+ AC_MSG_RESULT(8)
+ AC_DEFINE(BX_SMP_PROCESSORS, 8)
+ AC_DEFINE(BX_BOOTSTRAP_PROCESSOR, 0)
+ AC_DEFINE(BX_IOAPIC_DEFAULT_ID, 0x11)
+ AC_DEFINE(BX_USE_CPU_SMF, 0)
+ ;;
*)
echo " "
echo "WARNING: processors != [1,2,4] can work, but you need to modify rombios.c manually"
Index: bios/rombios.c
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v
retrieving revision 1.44
diff -u -r1.44 rombios.c
--- bios/rombios.c 4 Apr 2002 16:57:45 -0000 1.44
+++ bios/rombios.c 5 Apr 2002 10:17:18 -0000
@@ -9966,6 +9966,132 @@
db 3,0,0,0,0,13,4,13
db 3,0,0,0,0,14,4,14
db 3,0,0,0,0,15,4,15
+#elif (BX_SMP_PROCESSORS==8)
+// define the Intel MP Configuration Structure for 4 processors at
+// APIC ID 0,1,2,3. I/O APIC at ID=4.
+.align 16
+mp_config_table:
+ db 0x50, 0x43, 0x4d, 0x50 ;; "PCMP" signature
+ dw (mp_config_end-mp_config_table) ;; table length
+ db 4 ;; spec rev
+ db 0x2e ;; checksum
+ .ascii "BOCHSCPU" ;; OEM id = "BOCHSCPU"
+ db 0x30, 0x2e, 0x31, 0x20 ;; vendor id = "0.1 "
+ db 0x20, 0x20, 0x20, 0x20
+ db 0x20, 0x20, 0x20, 0x20
+ dw 0,0 ;; oem table ptr
+ dw 0 ;; oem table size
+ dw 22 ;; entry count
+ dw 0x0000, 0xfee0 ;; memory mapped address of local APIC
+ dw 0 ;; extended table length
+ db 0 ;; extended table checksum
+ db 0 ;; reserved
+mp_config_proc0:
+ db 0 ;; entry type=processor
+ db 0 ;; local APIC id
+ db 0x11 ;; local APIC version number
+ db 3 ;; cpu flags: bootstrap cpu
+ db 0,6,0,0 ;; cpu signature
+ dw 0x201,0 ;; feature flags
+ dw 0,0 ;; reserved
+ dw 0,0 ;; reserved
+mp_config_proc1:
+ db 0 ;; entry type=processor
+ db 1 ;; local APIC id
+ db 0x11 ;; local APIC version number
+ db 1 ;; cpu flags: enabled
+ db 0,6,0,0 ;; cpu signature
+ dw 0x201,0 ;; feature flags
+ dw 0,0 ;; reserved
+ dw 0,0 ;; reserved
+mp_config_proc2:
+ db 0 ;; entry type=processor
+ db 2 ;; local APIC id
+ db 0x11 ;; local APIC version number
+ db 1 ;; cpu flags: enabled
+ db 0,6,0,0 ;; cpu signature
+ dw 0x201,0 ;; feature flags
+ dw 0,0 ;; reserved
+ dw 0,0 ;; reserved
+mp_config_proc3:
+ db 0 ;; entry type=processor
+ db 3 ;; local APIC id
+ db 0x11 ;; local APIC version number
+ db 1 ;; cpu flags: enabled
+ db 0,6,0,0 ;; cpu signature
+ dw 0x201,0 ;; feature flags
+ dw 0,0 ;; reserved
+ dw 0,0 ;; reserved
+mp_config_proc4:
+ db 0 ;; entry type=processor
+ db 4 ;; local APIC id
+ db 0x11 ;; local APIC version number
+ db 1 ;; cpu flags: enabled
+ db 0,6,0,0 ;; cpu signature
+ dw 0x201,0 ;; feature flags
+ dw 0,0 ;; reserved
+ dw 0,0 ;; reserved
+mp_config_proc5:
+ db 0 ;; entry type=processor
+ db 5 ;; local APIC id
+ db 0x11 ;; local APIC version number
+ db 1 ;; cpu flags: enabled
+ db 0,6,0,0 ;; cpu signature
+ dw 0x201,0 ;; feature flags
+ dw 0,0 ;; reserved
+ dw 0,0 ;; reserved
+mp_config_proc6:
+ db 0 ;; entry type=processor
+ db 6 ;; local APIC id
+ db 0x11 ;; local APIC version number
+ db 1 ;; cpu flags: enabled
+ db 0,6,0,0 ;; cpu signature
+ dw 0x201,0 ;; feature flags
+ dw 0,0 ;; reserved
+ dw 0,0 ;; reserved
+mp_config_proc7:
+ db 0 ;; entry type=processor
+ db 7 ;; local APIC id
+ db 0x11 ;; local APIC version number
+ db 1 ;; cpu flags: enabled
+ db 0,6,0,0 ;; cpu signature
+ dw 0x201,0 ;; feature flags
+ dw 0,0 ;; reserved
+ dw 0,0 ;; reserved
+mp_config_isa_bus:
+ db 1 ;; entry type=bus
+ db 0 ;; bus ID
+ db 0x49, 0x53, 0x41, 0x20, 0x20, 0x20 ;; bus type="ISA "
+mp_config_ioapic:
+ db 2 ;; entry type=I/O APIC
+ db 0x11 ;; apic id=2. linux will set.
+ db 0x11 ;; I/O APIC version number
+ db 1 ;; flags=1=enabled
+ dw 0x0000, 0xfec0 ;; memory mapped address of I/O APIC
+mp_config_irqs:
+ db 3 ;; entry type=I/O interrupt
+ db 0 ;; interrupt type=vectored interrupt
+ db 0,0 ;; flags po=0, el=0 (linux uses as default)
+ db 0 ;; source bus ID is ISA
+ db 0 ;; source bus IRQ
+ db 0x11 ;; destination I/O APIC ID, Linux can't address it but won't need to
+ db 0 ;; destination I/O APIC interrrupt in
+ ;; repeat pattern for interrupts 0-15
+ db 3,0,0,0,0,1,0x11,1
+ db 3,0,0,0,0,2,0x11,2
+ db 3,0,0,0,0,3,0x11,3
+ db 3,0,0,0,0,4,0x11,4
+ db 3,0,0,0,0,5,0x11,5
+ db 3,0,0,0,0,6,0x11,6
+ db 3,0,0,0,0,7,0x11,7
+ db 3,0,0,0,0,8,0x11,8
+ db 3,0,0,0,0,9,0x11,9
+ db 3,0,0,0,0,10,0x11,10
+ db 3,0,0,0,0,11,0x11,11
+ db 3,0,0,0,0,12,0x11,12
+ db 3,0,0,0,0,13,0x11,13
+ db 3,0,0,0,0,14,0x11,14
+ db 3,0,0,0,0,15,0x11,15
#else
# error Sorry, rombios only has configurations for 1, 2, or 4 processors.
#endif // if (BX_SMP_PROCESSORS==...)
Index: cpu/apic.cc Index: cpu/apic.cc
=================================================================== ===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/apic.cc,v RCS file: /cvsroot/bochs/bochs/cpu/apic.cc,v