- WLI separated his patch into 8 cpu support and workarounds. I checked
in the 8 cpu support changes. These are the workarounds.
This commit is contained in:
Bryce Denney
parent
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@ -1,212 +1,17 @@
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From wli@holomorphy.com Fri Apr 5 13:32:54 2002
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Date: Fri, 5 Apr 2002 02:36:43 -0800
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From wli@holomorphy.com Sun Apr 7 21:59:35 2002
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Date: Sun, 7 Apr 2002 18:07:38 -0700
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From: William Lee Irwin III <wli@holomorphy.com>
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To: bochs-developers@lists.sourceforge.net
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Subject: [Bochs-developers] 05_8_cpus
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Subject: [Bochs-developers] 06_8_cpu_workarounds
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These are all fairly trivial patches; essentially aside from minor
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#defined limitations and some table setup for interacting with the
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OS this works pretty much out of the box. keyboard.cc changes
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reverted as usual for Linux compatibility.
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Here's a patch with the workarounds for 8 cpu's I used on top of
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reverting keyboard changes... looks like keyboard changes are getting
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fixed up pretty soon here so that will not be necessary for long.
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A few minor things came up while testing the thing, which are addressed
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along with the defines and table setups in the following patch.
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Cheers,
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Bill
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configure.in:
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Add a case for 8 cpu's.
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rombios.c:
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Add an MP table for 8 cpu's.
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apic.cc:
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Handle a strange boundary case tripped by setting something
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to an APIC ID it already possesses.
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cpu.cc:
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Assign either 0 or 1 to is_32, which is a Bool. The value
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appeared to resemble a stack address, which is probably a
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sign of a deeper problem and interacted poorly with
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fetchdecode.cc's array index arithmetic (in fact raising
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an exception within the simulator itself).
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cpu.h:
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(A) make as_32 and os_32 booleans, to (hopefully) prevent
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similar problems as with is_32.
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(B) #define APIC_MAX_ID to 32. Any higher than this and
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poor interactions with 32-bit APIC ID bitmasks begin to
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occur; larger bitmasks may well be in order esp. if these
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are considered physical or clustered APIC ID's.
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ioapic.cc:
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Avoid truncation of ioapic's physical APIC ID so as to
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prevent clashes of I/O APIC ID's with local APIC ID's
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This is compatible with flat logical destination modes
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of APICs because I/O apics are never worthwhile destinations
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for IPI's, so its non-addressibility in flat logical mode
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is inconsequential. It's unclear with which version of the
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I/O APIC this is compatible given the usual limitations on
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the number(s) of bits involved, but essentially this appears
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to work around some problems I've seen arising when the I/O
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APIC's ID clashes with a CPU's local APIC ID by assigning the
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I/O APIC an ID distinct from all cpus' while leaving all APIC
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ID's addressible in flat logical mode available for local APICs.
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Index: configure.in
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===================================================================
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RCS file: /cvsroot/bochs/bochs/configure.in,v
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retrieving revision 1.78
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diff -u -r1.78 configure.in
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--- configure.in 28 Mar 2002 09:43:07 -0000 1.78
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+++ configure.in 5 Apr 2002 10:17:15 -0000
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@@ -236,6 +236,13 @@
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AC_DEFINE(BX_IOAPIC_DEFAULT_ID, 4)
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AC_DEFINE(BX_USE_CPU_SMF, 0)
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;;
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+ 8)
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+ AC_MSG_RESULT(8)
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+ AC_DEFINE(BX_SMP_PROCESSORS, 8)
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+ AC_DEFINE(BX_BOOTSTRAP_PROCESSOR, 0)
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+ AC_DEFINE(BX_IOAPIC_DEFAULT_ID, 0x11)
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+ AC_DEFINE(BX_USE_CPU_SMF, 0)
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+ ;;
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*)
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echo " "
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echo "WARNING: processors != [1,2,4] can work, but you need to modify rombios.c manually"
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Index: bios/rombios.c
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v
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retrieving revision 1.44
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diff -u -r1.44 rombios.c
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--- bios/rombios.c 4 Apr 2002 16:57:45 -0000 1.44
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+++ bios/rombios.c 5 Apr 2002 10:17:18 -0000
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@@ -9966,6 +9966,132 @@
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db 3,0,0,0,0,13,4,13
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db 3,0,0,0,0,14,4,14
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db 3,0,0,0,0,15,4,15
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+#elif (BX_SMP_PROCESSORS==8)
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+// define the Intel MP Configuration Structure for 4 processors at
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+// APIC ID 0,1,2,3. I/O APIC at ID=4.
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+.align 16
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+mp_config_table:
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+ db 0x50, 0x43, 0x4d, 0x50 ;; "PCMP" signature
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+ dw (mp_config_end-mp_config_table) ;; table length
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+ db 4 ;; spec rev
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+ db 0x2e ;; checksum
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+ .ascii "BOCHSCPU" ;; OEM id = "BOCHSCPU"
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+ db 0x30, 0x2e, 0x31, 0x20 ;; vendor id = "0.1 "
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+ db 0x20, 0x20, 0x20, 0x20
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+ db 0x20, 0x20, 0x20, 0x20
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+ dw 0,0 ;; oem table ptr
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+ dw 0 ;; oem table size
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+ dw 22 ;; entry count
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+ dw 0x0000, 0xfee0 ;; memory mapped address of local APIC
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+ dw 0 ;; extended table length
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+ db 0 ;; extended table checksum
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+ db 0 ;; reserved
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+mp_config_proc0:
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+ db 0 ;; entry type=processor
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+ db 0 ;; local APIC id
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+ db 0x11 ;; local APIC version number
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+ db 3 ;; cpu flags: bootstrap cpu
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+ db 0,6,0,0 ;; cpu signature
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+ dw 0x201,0 ;; feature flags
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+ dw 0,0 ;; reserved
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+ dw 0,0 ;; reserved
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+mp_config_proc1:
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+ db 0 ;; entry type=processor
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+ db 1 ;; local APIC id
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+ db 0x11 ;; local APIC version number
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+ db 1 ;; cpu flags: enabled
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+ db 0,6,0,0 ;; cpu signature
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+ dw 0x201,0 ;; feature flags
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+ dw 0,0 ;; reserved
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+ dw 0,0 ;; reserved
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+mp_config_proc2:
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+ db 0 ;; entry type=processor
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+ db 2 ;; local APIC id
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+ db 0x11 ;; local APIC version number
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+ db 1 ;; cpu flags: enabled
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+ db 0,6,0,0 ;; cpu signature
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+ dw 0x201,0 ;; feature flags
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+ dw 0,0 ;; reserved
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+ dw 0,0 ;; reserved
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+mp_config_proc3:
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+ db 0 ;; entry type=processor
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+ db 3 ;; local APIC id
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+ db 0x11 ;; local APIC version number
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+ db 1 ;; cpu flags: enabled
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+ db 0,6,0,0 ;; cpu signature
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+ dw 0x201,0 ;; feature flags
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+ dw 0,0 ;; reserved
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+ dw 0,0 ;; reserved
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+mp_config_proc4:
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+ db 0 ;; entry type=processor
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+ db 4 ;; local APIC id
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+ db 0x11 ;; local APIC version number
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+ db 1 ;; cpu flags: enabled
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+ db 0,6,0,0 ;; cpu signature
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+ dw 0x201,0 ;; feature flags
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+ dw 0,0 ;; reserved
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+ dw 0,0 ;; reserved
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+mp_config_proc5:
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+ db 0 ;; entry type=processor
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+ db 5 ;; local APIC id
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+ db 0x11 ;; local APIC version number
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+ db 1 ;; cpu flags: enabled
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+ db 0,6,0,0 ;; cpu signature
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+ dw 0x201,0 ;; feature flags
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+ dw 0,0 ;; reserved
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+ dw 0,0 ;; reserved
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+mp_config_proc6:
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+ db 0 ;; entry type=processor
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+ db 6 ;; local APIC id
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+ db 0x11 ;; local APIC version number
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+ db 1 ;; cpu flags: enabled
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+ db 0,6,0,0 ;; cpu signature
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+ dw 0x201,0 ;; feature flags
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+ dw 0,0 ;; reserved
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+ dw 0,0 ;; reserved
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+mp_config_proc7:
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+ db 0 ;; entry type=processor
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+ db 7 ;; local APIC id
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+ db 0x11 ;; local APIC version number
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+ db 1 ;; cpu flags: enabled
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+ db 0,6,0,0 ;; cpu signature
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+ dw 0x201,0 ;; feature flags
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+ dw 0,0 ;; reserved
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+ dw 0,0 ;; reserved
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+mp_config_isa_bus:
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+ db 1 ;; entry type=bus
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+ db 0 ;; bus ID
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+ db 0x49, 0x53, 0x41, 0x20, 0x20, 0x20 ;; bus type="ISA "
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+mp_config_ioapic:
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+ db 2 ;; entry type=I/O APIC
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+ db 0x11 ;; apic id=2. linux will set.
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+ db 0x11 ;; I/O APIC version number
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+ db 1 ;; flags=1=enabled
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+ dw 0x0000, 0xfec0 ;; memory mapped address of I/O APIC
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+mp_config_irqs:
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+ db 3 ;; entry type=I/O interrupt
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+ db 0 ;; interrupt type=vectored interrupt
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+ db 0,0 ;; flags po=0, el=0 (linux uses as default)
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+ db 0 ;; source bus ID is ISA
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+ db 0 ;; source bus IRQ
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+ db 0x11 ;; destination I/O APIC ID, Linux can't address it but won't need to
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+ db 0 ;; destination I/O APIC interrrupt in
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+ ;; repeat pattern for interrupts 0-15
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+ db 3,0,0,0,0,1,0x11,1
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+ db 3,0,0,0,0,2,0x11,2
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+ db 3,0,0,0,0,3,0x11,3
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+ db 3,0,0,0,0,4,0x11,4
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+ db 3,0,0,0,0,5,0x11,5
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+ db 3,0,0,0,0,6,0x11,6
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+ db 3,0,0,0,0,7,0x11,7
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+ db 3,0,0,0,0,8,0x11,8
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+ db 3,0,0,0,0,9,0x11,9
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+ db 3,0,0,0,0,10,0x11,10
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+ db 3,0,0,0,0,11,0x11,11
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+ db 3,0,0,0,0,12,0x11,12
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+ db 3,0,0,0,0,13,0x11,13
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+ db 3,0,0,0,0,14,0x11,14
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+ db 3,0,0,0,0,15,0x11,15
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#else
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# error Sorry, rombios only has configurations for 1, 2, or 4 processors.
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#endif // if (BX_SMP_PROCESSORS==...)
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Index: cpu/apic.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/apic.cc,v
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