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Update instrumentation

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- x86-64 update
 - fixed several compilation erros
 - prepared for 'determine cpu count from .bocshrc' patch
 - now it works ;)
This commit is contained in:
Stanislav Shwartsman 2006-01-16 19:47:18 +00:00
parent 7bf51e48db
commit 2ff8b93f10
5 changed files with 101 additions and 104 deletions
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87
bochs/instrument/example0/instrument.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.cc,v 1.13 2005-11-14 18:25:41 sshwarts Exp $
// $Id: instrument.cc,v 1.14 2006-01-16 19:47:18 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,8 +25,9 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#include "bochs.h"
#include <assert.h>
#include "bochs.h"
// maximum size of an instruction
#define MAX_OPCODE_SIZE 16
@ -50,18 +51,27 @@ static struct instruction_t {
unsigned num_data_accesses;
struct {
bx_address laddr; // linear address
bx_address paddr; // physical address
Bit32u paddr; // physical address
unsigned op; // BX_READ, BX_WRITE or BX_RW
unsigned size; // 1 .. 8
} data_access[MAX_DATA_ACCESSES];
bx_bool is_branch;
bx_bool is_taken;
bx_address target_linear;
} instruction[BX_SMP_PROCESSORS];
} *instruction;
static logfunctions *instrument_log = new logfunctions ();
#define LOG_THIS instrument_log->
void bx_instr_init(unsigned cpu)
{
assert(cpu < BX_SMP_PROCESSORS);
if (instruction == NULL)
instruction = new struct instruction_t[BX_SMP_PROCESSORS];
fprintf(stderr, "Initialize cpu %d\n", cpu);
}
void bx_instr_reset(unsigned cpu)
{
@ -73,10 +83,7 @@ void bx_instr_reset(unsigned cpu)
void bx_instr_new_instruction(unsigned cpu)
{
if (!active)
{
return;
}
if (!active) return;
instruction_t *i = &instruction[cpu];
@ -102,14 +109,23 @@ void bx_instr_new_instruction(unsigned cpu)
else
fprintf(stderr, "(NOT TAKEN)");
}
fprintf(stderr, "\n");
fprintf(stderr, "\nMEMORY ACCESSES: %u\n", i->num_data_accesses);
for(n=0;n<i->num_data_accesses;n++)
{
fprintf(stderr, "MEM ACCESS: %08x (linear) %08x (physical) %s SIZE: %d\n",
#if BX_SUPPORT_X86_64
fprintf(stderr, "MEM ACCESS: %08x%08x (linear) %08x (physical) %s SIZE: %d\n",
(Bit32u)(i->data_access[n].laddr >> 32),
(Bit32u)(i->data_access[n].laddr & 0xffffffff),
i->data_access[n].paddr,
i->data_access[n].op == BX_READ ? "RD":"WR",
i->data_access[n].size);
#else
fprintf(stderr, "MEM ACCESS: %08x (linear) %08x (physical) %s SIZE: %d\n",
i->data_access[n].laddr,
i->data_access[n].paddr,
i->data_access[n].op == BX_READ ? "RD":"WR",
i->data_access[n].size);
#endif
}
fprintf(stderr, "\n");
}
@ -123,19 +139,10 @@ void bx_instr_new_instruction(unsigned cpu)
static void branch_taken(unsigned cpu, bx_address new_eip)
{
Bit32u laddr;
if (!active)
{
return;
}
if (!instruction[cpu].valid)
{
return;
}
if (!active || !instruction[cpu].valid) return;
// find linear address
laddr = BX_CPU(cpu)->get_segment_base(BX_SEG_REG_CS) + new_eip;
Bit32u laddr = BX_CPU(cpu)->get_segment_base(BX_SEG_REG_CS) + new_eip;
instruction[cpu].is_branch = 1;
instruction[cpu].is_taken = 1;
@ -149,35 +156,27 @@ void bx_instr_cnear_branch_taken(unsigned cpu, bx_address new_eip)
void bx_instr_cnear_branch_not_taken(unsigned cpu)
{
if (!active)
{
return;
}
if (!instruction[cpu].valid)
{
return;
}
if (!active || !instruction[cpu].valid) return;
instruction[cpu].is_branch = 1;
instruction[cpu].is_taken = 0;
}
void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address new_eip) {
void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address new_eip)
{
branch_taken(cpu, new_eip);
}
void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address new_eip) {
void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address new_eip)
{
branch_taken(cpu, new_eip);
}
void bx_instr_opcode(unsigned cpu, Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64)
{
if (!active)
{
return;
}
if (!active) return;
for(int i=0;i<len;i++)
for(unsigned i=0;i<len;i++)
{
instruction[cpu].opcode[i] = opcode[i];
}
@ -189,10 +188,7 @@ void bx_instr_opcode(unsigned cpu, Bit8u *opcode, unsigned len, bx_bool is32, bx
void bx_instr_fetch_decode_completed(unsigned cpu, const bxInstruction_c *i)
{
if(active)
{
instruction[cpu].valid = 1;
}
if(active) instruction[cpu].valid = 1;
}
void bx_instr_prefix(unsigned cpu, Bit8u prefix)
@ -227,17 +223,10 @@ void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address e
void bx_instr_mem_data(unsigned cpu, bx_address lin, unsigned size, unsigned rw)
{
unsigned index;
bx_address phy;
Bit32u phy;
bx_bool page_valid;
if(!active)
{
return;
}
if (!instruction[cpu].valid)
{
return;
}
if(!active || !instruction[cpu].valid) return;
if (instruction[cpu].num_data_accesses >= MAX_DATA_ACCESSES)
{

7
bochs/instrument/example0/instrument.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.h,v 1.15 2005-11-14 18:25:41 sshwarts Exp $
// $Id: instrument.h,v 1.16 2006-01-16 19:47:18 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -53,6 +53,7 @@ class bxInstruction_c;
// called from the CPU core
void bx_instr_init(unsigned cpu);
void bx_instr_reset(unsigned cpu);
void bx_instr_new_instruction(unsigned cpu);
@ -73,7 +74,7 @@ void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address e
void bx_instr_mem_data(unsigned cpu, bx_address lin, unsigned size, unsigned rw);
/* simulation init, shutdown, reset */
# define BX_INSTR_INIT(cpu_id)
# define BX_INSTR_INIT(cpu_id) bx_instr_init(cpu_id)
# define BX_INSTR_SHUTDOWN(cpu_id)
# define BX_INSTR_RESET(cpu_id) bx_instr_reset(cpu_id)
# define BX_INSTR_HLT(cpu_id)
@ -98,7 +99,7 @@ void bx_instr_mem_data(unsigned cpu, bx_address lin, unsigned size, unsigned rw)
bx_instr_fetch_decode_completed(cpu_id, i)
/* prefix byte decoded */
# define BX_INSTR_PREFIX(cpu_id, prefix) bx_instr_prefix_as(cpu_id, prefix)
# define BX_INSTR_PREFIX(cpu_id, prefix) bx_instr_prefix(cpu_id, prefix)
/* exceptional case and interrupt */
# define BX_INSTR_EXCEPTION(cpu_id, vector) bx_instr_exception(cpu_id, vector)

96
bochs/instrument/example1/instrument.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.cc,v 1.9 2005-11-14 18:25:41 sshwarts Exp $
// $Id: instrument.cc,v 1.10 2006-01-16 19:47:18 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -24,13 +24,26 @@
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#include <assert.h>
#include "bochs.h"
bxInstrumentation icpu[BX_SMP_PROCESSORS];
bxInstrumentation *icpu = NULL;
static disassembler bx_disassembler;
void bx_instr_init(unsigned cpu)
{
assert(cpu < BX_SMP_PROCESSORS);
if (icpu == NULL)
icpu = new bxInstrumentation[BX_SMP_PROCESSORS];
icpu[cpu].set_cpu_id(cpu);
fprintf(stderr, "Initialize cpu %d\n", cpu);
}
void bxInstrumentation::bx_instr_reset()
{
valid = is_branch = 0;
@ -40,16 +53,13 @@ void bxInstrumentation::bx_instr_reset()
void bxInstrumentation::bx_instr_new_instruction()
{
if (!active)
{
return;
}
if (!active) return;
if (valid)
{
char disasm_tbuf[512]; // buffer for instruction disassembly
unsigned length = opcode_size, n;
bx_disassemble.disasm(is32, is64, 0, 0, opcode, disasm_tbuf);
bx_disassembler.disasm(is32, is64, 0, 0, opcode, disasm_tbuf);
if(length != 0)
{
fprintf(stderr, "----------------------------------------------------------\n");
@ -65,14 +75,23 @@ void bxInstrumentation::bx_instr_new_instruction()
else
fprintf(stderr, "(NOT TAKEN)");
}
fprintf(stderr, "\n");
fprintf(stderr, "\nMEMORY ACCESSES: %u\n", num_data_accesses);
for(n=0;n < num_data_accesses;n++)
{
fprintf(stderr, "MEM ACCESS: %08x (linear) %08x (physical) %s SIZE: %d\n",
data_access[n].laddr,
#if BX_SUPPORT_X86_64
fprintf(stderr, "MEM ACCESS %u: %08x%08x (linear) %08x (physical) %s SIZE: %d\n", n,
(Bit32u)(data_access[n].laddr >> 32),
(Bit32u)(data_access[n].laddr & 0xffffffff),
data_access[n].paddr,
data_access[n].op == BX_READ ? "RD":"WR",
data_access[n].size);
#else
fprintf(stderr, "MEM ACCESS %u: %08x (linear) %08x (physical) %s SIZE: %d\n", n,
i->data_access[n].laddr,
i->data_access[n].paddr,
i->data_access[n].op == BX_READ ? "RD":"WR",
i->data_access[n].size);
#endif
}
fprintf(stderr, "\n");
}
@ -84,14 +103,10 @@ void bxInstrumentation::bx_instr_new_instruction()
void bxInstrumentation::branch_taken(bx_address new_eip)
{
Bit32u laddr;
if (!active || !valid) {
return;
}
if (!active || !valid) return;
// find linear address
laddr = BX_CPU(cpu_id)->get_segment_base(BX_SEG_REG_CS) + new_eip;
Bit32u laddr = BX_CPU(cpu_id)->get_segment_base(BX_SEG_REG_CS) + new_eip;
is_branch = 1;
is_taken = 1;
@ -105,32 +120,29 @@ void bxInstrumentation::bx_instr_cnear_branch_taken(bx_address new_eip)
void bxInstrumentation::bx_instr_cnear_branch_not_taken()
{
if (!active || !valid) {
return;
}
if (!active || !valid) return;
is_branch = 1;
is_taken = 0;
}
void bxInstrumentation::bx_instr_ucnear_branch(unsigned what, bx_address new_eip) {
branch_taken(new_eip);
}
void bxInstrumentation::bx_instr_far_branch(unsigned what, Bit16u new_cs, bx_address new_eip) {
branch_taken(new_eip);
}
void bxInstrumentation::bx_instr_opcode(Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64)
void bxInstrumentation::bx_instr_ucnear_branch(unsigned what, bx_address new_eip)
{
if (!active)
{
return;
}
branch_taken(new_eip);
}
for(int i=0;i<len;i++)
void bxInstrumentation::bx_instr_far_branch(unsigned what, Bit16u new_cs, bx_address new_eip)
{
branch_taken(new_eip);
}
void bxInstrumentation::bx_instr_opcode(Bit8u *opcode_bytes, unsigned len, bx_bool is32, bx_bool is64)
{
if (!active) return;
for(unsigned i=0;i<len;i++)
{
opcode[i] = opcode[i];
opcode[i] = opcode_bytes[i];
}
is32 = is32;
@ -140,10 +152,7 @@ void bxInstrumentation::bx_instr_opcode(Bit8u *opcode, unsigned len, bx_bool is3
void bxInstrumentation::bx_instr_fetch_decode_completed(const bxInstruction_c *i)
{
if(active)
{
valid = 1;
}
if(active) valid = 1;
}
void bxInstrumentation::bx_instr_prefix(Bit8u prefix)
@ -177,17 +186,10 @@ void bxInstrumentation::bx_instr_hwinterrupt(unsigned vector, Bit16u cs, bx_addr
void bxInstrumentation::bx_instr_mem_data(bx_address lin, unsigned size, unsigned rw)
{
bx_address phy;
Bit32u phy;
bx_bool page_valid;
if(!active)
{
return;
}
if (!valid)
{
return;
}
if(!active || !valid) return;
if (num_data_accesses >= MAX_DATA_ACCESSES)
{

12
bochs/instrument/example1/instrument.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.h,v 1.13 2005-11-14 18:25:41 sshwarts Exp $
// $Id: instrument.h,v 1.14 2006-01-16 19:47:18 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -74,7 +74,7 @@ public:
unsigned num_data_accesses;
struct {
bx_address laddr; // linear address
bx_address paddr; // physical address
Bit32u paddr; // physical address
unsigned op; // BX_READ, BX_WRITE or BX_RW
unsigned size; // 1 .. 8
} data_access[MAX_DATA_ACCESSES];
@ -91,7 +91,7 @@ public:
void activate() { active = 1; }
void deactivate() { active = 0; }
bx_bool toggle_active() { active = !active; }
void toggle_active() { active = !active; }
bx_bool is_active() const { return active; }
void bx_instr_reset();
@ -117,10 +117,12 @@ private:
void branch_taken(bx_address new_eip);
};
extern bxInstrumentation icpu[BX_SMP_PROCESSORS];
void bx_instr_init(unsigned cpu);
extern bxInstrumentation *icpu;
/* simulation init, shutdown, reset */
# define BX_INSTR_INIT(cpu_id) icpu[cpu_id].set_cpu_id(cpu_id)
# define BX_INSTR_INIT(cpu_id) bx_instr_init(cpu_id);
# define BX_INSTR_SHUTDOWN(cpu_id)
# define BX_INSTR_RESET(cpu_id) icpu[cpu_id].bx_instr_reset()
# define BX_INSTR_HLT(cpu_id)

3
bochs/instrument/instrumentation.txt
View File

@ -228,3 +228,6 @@ Feature requests:
'not taken' new_EIP parameter.
2. X86-64 support
3. BX_INSTR_SMI, BX_INSTR_NMI, BX_INSTR_SIPI and other external events
callbacks