added IOAPIC control from the PIIX3 (enable /disable and address relocation)
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7efd6866ce
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@ -119,7 +119,7 @@ void bx_io_redirect_entry_t::register_state(bx_param_c *parent)
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#define BX_IOAPIC_BASE_ADDR (0xfec00000)
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#define BX_IOAPIC_DEFAULT_ID (BX_SMP_PROCESSORS)
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bx_ioapic_c::bx_ioapic_c(): base_addr(BX_IOAPIC_BASE_ADDR)
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bx_ioapic_c::bx_ioapic_c(): enabled(0), base_addr(BX_IOAPIC_BASE_ADDR)
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{
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set_id(BX_IOAPIC_DEFAULT_ID);
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put("ioapic", "IOAP");
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@ -134,8 +134,7 @@ bx_ioapic_c::~bx_ioapic_c()
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void bx_ioapic_c::init(void)
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{
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BX_INFO(("initializing I/O APIC"));
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DEV_register_memory_handlers(theIOAPIC,
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ioapic_read, ioapic_write, base_addr, base_addr + 0xfff);
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set_enabled(1, 0x0000);
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reset(BX_RESET_HARDWARE);
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#if BX_DEBUGGER
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// register device for the 'info device' command (calls debug_dump())
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@ -235,6 +234,26 @@ void bx_ioapic_c::write_aligned(bx_phy_address address, Bit32u value)
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}
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}
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void bx_ioapic_c::set_enabled(bx_bool _enabled, Bit16u base_offset)
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{
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if (_enabled != enabled) {
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if (_enabled) {
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base_addr = BX_IOAPIC_BASE_ADDR | base_offset;
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DEV_register_memory_handlers(theIOAPIC,
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ioapic_read, ioapic_write, base_addr, base_addr + 0xfff);
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} else {
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DEV_unregister_memory_handlers(theIOAPIC, base_addr, base_addr + 0xfff);
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}
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enabled = _enabled;
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} else if (enabled && (base_offset != (base_addr & 0xffff))) {
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DEV_unregister_memory_handlers(theIOAPIC, base_addr, base_addr + 0xfff);
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base_addr = BX_IOAPIC_BASE_ADDR | base_offset;
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DEV_register_memory_handlers(theIOAPIC,
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ioapic_read, ioapic_write, base_addr, base_addr + 0xfff);
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}
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BX_INFO(("IOAPIC %sabled (base address = 0x%08x)", enabled?"en":"dis", (Bit32u)base_addr));
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}
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void bx_ioapic_c::set_irq_level(Bit8u int_in, bx_bool level)
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{
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if (int_in == 0) { // timer connected to pin #2
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@ -82,6 +82,7 @@ public:
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virtual void debug_dump(int argc, char **argv);
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#endif
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virtual void set_enabled(bx_bool enabled, Bit16u base_offset);
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virtual void receive_eoi(Bit8u vector);
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virtual void set_irq_level(Bit8u int_in, bx_bool level);
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@ -89,12 +90,12 @@ public:
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void write_aligned(bx_phy_address address, Bit32u data);
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private:
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bx_phy_address get_base(void) const { return base_addr; }
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void set_id(Bit32u new_id) { id = new_id; }
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Bit32u get_id() const { return id; }
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void service_ioapic(void);
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bx_bool enabled;
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bx_phy_address base_addr;
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Bit32u id;
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@ -308,6 +308,7 @@ public:
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#if BX_SUPPORT_APIC
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class BOCHSAPI bx_ioapic_stub_c : public bx_devmodel_c {
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public:
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virtual void set_enabled(bx_bool enabled, Bit16u base_offset) {}
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virtual void receive_eoi(Bit8u vector) {}
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virtual void set_irq_level(Bit8u int_in, bx_bool level) {}
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};
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@ -388,8 +388,12 @@ void bx_piix3_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
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break;
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case 0x4f:
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if (BX_P2I_THIS s.chipset == BX_PCI_CHIPSET_I440FX) {
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// TODO: enable / disable IOAPIC chip select
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BX_P2I_THIS pci_conf[address+i] = (value8 & 0x01);
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#if BX_SUPPORT_APIC
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if (DEV_ioapic_present()) {
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DEV_ioapic_set_enabled(value8 & 0x01, (BX_P2I_THIS pci_conf[0x80] & 0x3f) << 10);
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}
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#endif
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}
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break;
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case 0x60:
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@ -413,6 +417,16 @@ void bx_piix3_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
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BX_P2I_THIS pci_conf[address+i] = (value8 & 0xd7);
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}
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break;
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case 0x80:
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if (BX_P2I_THIS s.chipset == BX_PCI_CHIPSET_I440FX) {
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BX_P2I_THIS pci_conf[address+i] = (value8 & 0x7f);
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#if BX_SUPPORT_APIC
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if (DEV_ioapic_present()) {
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DEV_ioapic_set_enabled(BX_P2I_THIS pci_conf[0x4f] & 0x01, (value8 & 0x3f) << 10);
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}
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#endif
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}
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break;
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default:
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BX_P2I_THIS pci_conf[address+i] = value8;
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BX_DEBUG(("PIIX3 PCI-to-ISA write register 0x%02x value 0x%02x", address+i,
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@ -148,6 +148,7 @@ extern "C" {
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///////// I/O APIC macros
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#define DEV_ioapic_present() (bx_devices.pluginIOAPIC != &bx_devices.stubIOAPIC)
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#define DEV_ioapic_set_enabled(a,b) (bx_devices.pluginIOAPIC->set_enabled(a,b))
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#define DEV_ioapic_receive_eoi(a) (bx_devices.pluginIOAPIC->receive_eoi(a))
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#define DEV_ioapic_set_irq_level(a,b) (bx_devices.pluginIOAPIC->set_irq_level(a,b))
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