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Fixed several disasm bugs

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This commit is contained in:
Stanislav Shwartsman 2006-02-17 13:33:05 +00:00
parent 4cece81589
commit 2dc81b172a
5 changed files with 117 additions and 80 deletions
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35
bochs/disasm/dis_groups.cc
View File

@ -290,6 +290,14 @@ void disassembler::Pq(const x86_insn *insn)
dis_sprintf("%%mm%d", insn->nnn);
}
void disassembler::Nq(const x86_insn *insn)
{
if (intel_mode)
dis_sprintf ("mm%d", insn->rm);
else
dis_sprintf("%%mm%d", insn->rm);
}
void disassembler::Qd(const x86_insn *insn)
{
if (insn->mod == 3)
@ -317,6 +325,14 @@ void disassembler::Qq(const x86_insn *insn)
}
// xmm register
void disassembler::Udq(const x86_insn *insn)
{
if (intel_mode)
dis_sprintf ("xmm%d", insn->rm);
else
dis_sprintf("%%xmm%d", insn->rm);
}
void disassembler::Vq(const x86_insn *insn)
{
if (intel_mode)
@ -357,10 +373,23 @@ void disassembler::Wdq(const x86_insn *insn)
(this->*resolve_modrm)(insn, O_SIZE);
}
void disassembler::Wss(const x86_insn *insn) { Wdq(insn); }
void disassembler::Wsd(const x86_insn *insn) { Wdq(insn); }
void disassembler::Wps(const x86_insn *insn) { Wdq(insn); }
void disassembler::Wsd(const x86_insn *insn) { Wq(insn); }
void disassembler::Wss(const x86_insn *insn)
{
if (insn->mod == 3)
{
if (intel_mode)
dis_sprintf ("xmm%d", insn->rm);
else
dis_sprintf("%%xmm%d", insn->rm);
}
else
(this->*resolve_modrm)(insn, D_SIZE);
}
void disassembler::Wpd(const x86_insn *insn) { Wdq(insn); }
void disassembler::Wps(const x86_insn *insn) { Wdq(insn); }
// direct memory access
void disassembler::OP_O(const x86_insn *insn, unsigned size)

2
bochs/disasm/dis_tables.h
View File

@ -82,6 +82,7 @@
#define Pq &disassembler::Pq
#define Qd &disassembler::Qd
#define Qq &disassembler::Qq
#define Nq &disassembler::Nq
#define Vq &disassembler::Vq
#define Vdq &disassembler::Vdq
@ -89,6 +90,7 @@
#define Vsd &disassembler::Vsd
#define Vps &disassembler::Vps
#define Vpd &disassembler::Vpd
#define Udq &disassembler::Udq
#define Wq &disassembler::Wq
#define Wdq &disassembler::Wdq

70
bochs/disasm/dis_tables.inc
View File

@ -37,8 +37,8 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f14[4] = {
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f15[4] = {
/* -- */ { 0, &Ia_unpckhps_Vps_Wq },
/* 66 */ { 0, &Ia_unpckhpd_Vpd_Wq },
/* -- */ { 0, &Ia_unpckhps_Vps_Wdq },
/* 66 */ { 0, &Ia_unpckhpd_Vpd_Wdq },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
@ -457,8 +457,8 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fc4[4] = {
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fc5[4] = {
/* -- */ { 0, &Ia_pextrw_Gd_Pq_Ib },
/* 66 */ { 0, &Ia_pextrw_Gd_Vdq_Ib },
/* -- */ { 0, &Ia_pextrw_Gd_Nq_Ib },
/* 66 */ { 0, &Ia_pextrw_Gd_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
@ -520,8 +520,8 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fd6[4] = {
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fd7[4] = {
/* -- */ { 0, &Ia_pmovmskb_Gd_Pq },
/* 66 */ { 0, &Ia_pmovmskb_Gd_Vdq },
/* -- */ { 0, &Ia_pmovmskb_Gd_Nq },
/* 66 */ { 0, &Ia_pmovmskb_Gd_Udq },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
@ -744,8 +744,8 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0ff6[4] = {
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0ff7[4] = {
/* -- */ { 0, &Ia_maskmovq_Pq_Qq },
/* 66 */ { 0, &Ia_maskmovdqu_Vdq_Wdq },
/* -- */ { 0, &Ia_maskmovq_Pq_Nq },
/* 66 */ { 0, &Ia_maskmovdqu_Vdq_Udq },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
@ -800,71 +800,71 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0ffe[4] = {
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G1202[4] = {
/* -- */ { 0, &Ia_psrlw_Pq_Ib },
/* 66 */ { 0, &Ia_psrlw_Vdq_Ib },
/* -- */ { 0, &Ia_psrlw_Nq_Ib },
/* 66 */ { 0, &Ia_psrlw_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G1204[4] = {
/* -- */ { 0, &Ia_psraw_Pq_Ib },
/* 66 */ { 0, &Ia_psraw_Vdq_Ib },
/* -- */ { 0, &Ia_psraw_Nq_Ib },
/* 66 */ { 0, &Ia_psraw_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G1206[4] = {
/* -- */ { 0, &Ia_psllw_Pq_Ib },
/* 66 */ { 0, &Ia_psllw_Vdq_Ib },
/* -- */ { 0, &Ia_psllw_Nq_Ib },
/* 66 */ { 0, &Ia_psllw_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G1302[4] = {
/* -- */ { 0, &Ia_psrld_Pq_Ib },
/* 66 */ { 0, &Ia_psrld_Vdq_Ib },
/* -- */ { 0, &Ia_psrld_Nq_Ib },
/* 66 */ { 0, &Ia_psrld_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G1304[4] = {
/* -- */ { 0, &Ia_psrad_Pq_Ib },
/* 66 */ { 0, &Ia_psrad_Vdq_Ib },
/* -- */ { 0, &Ia_psrad_Nq_Ib },
/* 66 */ { 0, &Ia_psrad_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G1306[4] = {
/* -- */ { 0, &Ia_pslld_Pq_Ib },
/* 66 */ { 0, &Ia_pslld_Vdq_Ib },
/* -- */ { 0, &Ia_pslld_Nq_Ib },
/* 66 */ { 0, &Ia_pslld_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G1402[4] = {
/* -- */ { 0, &Ia_psrlq_Pq_Ib },
/* 66 */ { 0, &Ia_psrlq_Vdq_Ib },
/* -- */ { 0, &Ia_psrlq_Nq_Ib },
/* 66 */ { 0, &Ia_psrlq_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G1403[4] = {
/* -- */ { 0, &Ia_Invalid },
/* 66 */ { 0, &Ia_psrldq_Wdq_Ib },
/* 66 */ { 0, &Ia_psrldq_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G1406[4] = {
/* -- */ { 0, &Ia_psllq_Pq_Ib },
/* 66 */ { 0, &Ia_psllq_Vdq_Ib },
/* -- */ { 0, &Ia_psllq_Nq_Ib },
/* 66 */ { 0, &Ia_psllq_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G1407[4] = {
/* -- */ { 0, &Ia_Invalid },
/* 66 */ { 0, &Ia_pslldq_Vdq_Ib },
/* 66 */ { 0, &Ia_pslldq_Udq_Ib },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid }
};
@ -1630,7 +1630,7 @@ static BxDisasmOpcodeTable_t BxDisasmFPGroupD8[8] = {
/* 4 */ { 0, &Ia_fsubs_Md },
/* 5 */ { 0, &Ia_fsubrs_Md },
/* 6 */ { 0, &Ia_fdivs_Md },
/* 7 */ { 0, &Ia_fdivprs_Md }
/* 7 */ { 0, &Ia_fdivrs_Md }
};
// D9 (modrm is outside 00h - BFh) (mod != 11)
@ -1776,14 +1776,14 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodeInfoFP[512] = {
/* D8 F5 */ { 0, &Ia_fdiv_ST0_STi },
/* D8 F6 */ { 0, &Ia_fdiv_ST0_STi },
/* D8 F7 */ { 0, &Ia_fdiv_ST0_STi },
/* D8 F8 */ { 0, &Ia_fsubr_ST0_STi },
/* D8 F9 */ { 0, &Ia_fsubr_ST0_STi },
/* D8 FA */ { 0, &Ia_fsubr_ST0_STi },
/* D8 FB */ { 0, &Ia_fsubr_ST0_STi },
/* D8 FC */ { 0, &Ia_fsubr_ST0_STi },
/* D8 FD */ { 0, &Ia_fsubr_ST0_STi },
/* D8 FE */ { 0, &Ia_fsubr_ST0_STi },
/* D8 FF */ { 0, &Ia_fsubr_ST0_STi },
/* D8 F8 */ { 0, &Ia_fdivr_ST0_STi },
/* D8 F9 */ { 0, &Ia_fdivr_ST0_STi },
/* D8 FA */ { 0, &Ia_fdivr_ST0_STi },
/* D8 FB */ { 0, &Ia_fdivr_ST0_STi },
/* D8 FC */ { 0, &Ia_fdivr_ST0_STi },
/* D8 FD */ { 0, &Ia_fdivr_ST0_STi },
/* D8 FE */ { 0, &Ia_fdivr_ST0_STi },
/* D8 FF */ { 0, &Ia_fdivr_ST0_STi },
// D9 (modrm is outside 00h - BFh) (mod == 11)
/* D9 C0 */ { 0, &Ia_fld_STi },

5
bochs/disasm/disasm.h
View File

@ -308,6 +308,8 @@ public:
* J - The instruction contains a relative offset to be added to the
* instruction pointer register.
* M - The ModR/M byte may refer only to memory.
* N - The R/M field of the ModR/M byte selects a packed-quadword MMX
technology register.
* O - The instruction has no ModR/M byte; the offset of the operand is
* coded as a word or double word (depending on address size attribute)
* in the instruction. No base register, index register, or scaling
@ -321,6 +323,7 @@ public:
* index register, a scaling factor, and a displacement.
* R - The mod field of the ModR/M byte may refer only to a general register.
* S - The reg field of the ModR/M byte selects a segment register.
* U - The R/M field of the ModR/M byte selects a 128-bit XMM register.
* T - The reg field of the ModR/M byte selects a test register.
* V - The reg field of the ModR/M byte selects a 128-bit XMM register.
* W - A ModR/M byte follows the opcode and specifies the operand. The
@ -447,8 +450,10 @@ public:
void Qd(const x86_insn *insn);
void Qq(const x86_insn *insn);
void Vq(const x86_insn *insn);
void Nq(const x86_insn *insn);
// xmm register
void Udq(const x86_insn *insn);
void Vdq(const x86_insn *insn);
void Vss(const x86_insn *insn);
void Vsd(const x86_insn *insn);

55
bochs/disasm/opcodes.inc
View File

@ -287,7 +287,8 @@ Ia_fdiv_ST0_STi = { "fdiv", "fdiv", ST0, STi, XX },
Ia_fdiv_STi_ST0 = { "fdiv", "fdiv", STi, ST0, XX },
Ia_fdivl_Mq = { "fdiv", "fdivl", Mq, XX, XX },
Ia_fdivp_STi_ST0 = { "fdivp", "fdivp", STi, ST0, XX },
Ia_fdivprs_Md = { "fdivpr", "fdivprs", Md, XX, XX },
Ia_fdivrs_Md = { "fdivr", "fdivrs", Md, XX, XX },
Ia_fdivr_ST0_STi = { "fdivr", "fdivr", ST0, STi, XX },
Ia_fdivr_STi_ST0 = { "fdivr", "fdivr", STi, ST0, XX },
Ia_fdivrl_Mq = { "fdivr", "fdivrl", Mq, XX, XX },
Ia_fdivrp_STi_ST0 = { "fdivrp", "fdivrp", STi, ST0, XX },
@ -543,8 +544,8 @@ Ia_lssl_Gd_Mp = { "lss", "lssl", Gd, Mp, XX },
Ia_lssq_Gq_Mp = { "lss", "lssq", Gq, Mp, XX },
Ia_lssw_Gw_Mp = { "lss", "lssw", Gw, Mp, XX },
Ia_ltr = { "ltr", "ltr", Ew, XX, XX },
Ia_maskmovdqu_Vdq_Wdq = { "maskmovdqu", "maskmovdqu", Vdq, Wdq, XX },
Ia_maskmovq_Pq_Qq = { "maskmovq", "maskmovq", Pq, Qq, XX },
Ia_maskmovdqu_Vdq_Udq = { "maskmovdqu", "maskmovdqu", Vdq, Udq, XX },
Ia_maskmovq_Pq_Nq = { "maskmovq", "maskmovq", Pq, Nq, XX },
Ia_maxpd_Vpd_Wpd = { "maxpd", "maxpd", Vpd, Wpd, XX },
Ia_maxps_Vps_Wps = { "maxps", "maxps", Vps, Wps, XX },
Ia_maxsd_Vsd_Wsd = { "maxsd", "maxsd", Vsd, Wsd, XX },
@ -746,8 +747,8 @@ Ia_pcmpgtd_Pq_Qq = { "pcmpgtd", "pcmpgtd", Pq, Qq, XX },
Ia_pcmpgtd_Vdq_Wdq = { "pcmpgtd", "pcmpgtd", Vdq, Wdq, XX },
Ia_pcmpgtw_Pq_Qq = { "pcmpgtw", "pcmpgtw", Pq, Qq, XX },
Ia_pcmpgtw_Vdq_Wq = { "pcmpgtw", "pcmpgtw", Vdq, Wq, XX },
Ia_pextrw_Gd_Pq_Ib = { "pextrw", "pextrw", Gd, Pq, Ib },
Ia_pextrw_Gd_Vdq_Ib = { "pextrw", "pextrw", Gd, Vdq, Ib },
Ia_pextrw_Gd_Nq_Ib = { "pextrw", "pextrw", Gd, Nq, Ib },
Ia_pextrw_Gd_Udq_Ib = { "pextrw", "pextrw", Gd, Udq, Ib },
Ia_pf2id_Pq_Qq = { "pf2id", "pf2id", Pq, Qq, XX },
Ia_pf2iw_Pq_Qq = { "pf2iw", "pf2iw", Pq, Qq, XX },
Ia_pfacc_Pq_Qq = { "pfacc", "pfacc", Pq, Qq, XX },
@ -781,8 +782,8 @@ Ia_pminsw_Pq_Qq = { "pminsw", "pminsw", Pq, Qq, XX },
Ia_pminsw_Vdq_Wdq = { "pminsw", "pminsw", Vdq, Wdq, XX },
Ia_pminub_Pq_Qq = { "pminub", "pminub", Pq, Qq, XX },
Ia_pminub_Vdq_Wdq = { "pminub", "pminub", Vdq, Wdq, XX },
Ia_pmovmskb_Gd_Pq = { "pmovmskb", "pmovmskb", Gd, Pq, XX },
Ia_pmovmskb_Gd_Vdq = { "pmovmskb", "pmovmskb", Gd, Vdq, XX },
Ia_pmovmskb_Gd_Nq = { "pmovmskb", "pmovmskb", Gd, Nq, XX },
Ia_pmovmskb_Gd_Udq = { "pmovmskb", "pmovmskb", Gd, Udq, XX },
Ia_pmulhrw_Pq_Qq = { "pmulhrw", "pmulhrw", Pq, Qq, XX },
Ia_pmulhuw_Pq_Qq = { "pmulhuw", "pmulhuw", Pq, Qq, XX },
Ia_pmulhuw_Vdq_Wdq = { "pmulhuw", "pmulhuw", Vdq, Wdq, XX },
@ -840,39 +841,39 @@ Ia_pshufd_Vdq_Wdq_Ib = { "pshufd", "pshufd", Vdq, Wdq, Ib },
Ia_pshufhw_Vq_Wq_Ib = { "pshufhw", "pshufhw", Vq, Wq, Ib },
Ia_pshuflw_Vq_Wq_Ib = { "pshuflw", "pshuflw", Vq, Wq, Ib },
Ia_pshufw_Pq_Qq_Ib = { "pshufw", "pshufw", Pq, Qq, Ib },
Ia_pslld_Pq_Ib = { "pslld", "pslld", Pq, Ib, XX },
Ia_pslld_Nq_Ib = { "pslld", "pslld", Nq, Ib, XX },
Ia_pslld_Pq_Qq = { "pslld", "pslld", Pq, Qq, XX },
Ia_pslld_Vdq_Ib = { "pslld", "pslld", Vdq, Ib, XX },
Ia_pslld_Udq_Ib = { "pslld", "pslld", Udq, Ib, XX },
Ia_pslld_Vdq_Wdq = { "pslld", "pslld", Vdq, Wdq, XX },
Ia_pslldq_Vdq_Ib = { "pslldq", "pslldq", Vdq, Ib, XX },
Ia_psllq_Pq_Ib = { "psllq", "psllq", Pq, Ib, XX },
Ia_pslldq_Udq_Ib = { "pslldq", "pslldq", Udq, Ib, XX },
Ia_psllq_Nq_Ib = { "psllq", "psllq", Nq, Ib, XX },
Ia_psllq_Pq_Qq = { "psllq", "psllq", Pq, Qq, XX },
Ia_psllq_Vdq_Ib = { "psllq", "psllq", Vdq, Ib, XX },
Ia_psllq_Udq_Ib = { "psllq", "psllq", Udq, Ib, XX },
Ia_psllq_Vdq_Wdq = { "psllq", "psllq", Vdq, Wdq, XX },
Ia_psllw_Pq_Ib = { "psllw", "psllw", Pq, Ib, XX },
Ia_psllw_Nq_Ib = { "psllw", "psllw", Nq, Ib, XX },
Ia_psllw_Pq_Qq = { "psllw", "psllw", Pq, Qq, XX },
Ia_psllw_Vdq_Ib = { "psllw", "psllw", Vdq, Ib, XX },
Ia_psllw_Udq_Ib = { "psllw", "psllw", Udq, Ib, XX },
Ia_psllw_Vdq_Wdq = { "psllw", "psllw", Vdq, Wdq, XX },
Ia_psrad_Pq_Ib = { "psrad", "psrad", Pq, Ib, XX },
Ia_psrad_Nq_Ib = { "psrad", "psrad", Nq, Ib, XX },
Ia_psrad_Pq_Qq = { "psrad", "psrad", Pq, Qq, XX },
Ia_psrad_Vdq_Ib = { "psrad", "psrad", Vdq, Ib, XX },
Ia_psrad_Udq_Ib = { "psrad", "psrad", Udq, Ib, XX },
Ia_psrad_Vdq_Wdq = { "psrad", "psrad", Vdq, Wdq, XX },
Ia_psraw_Pq_Ib = { "psraw", "psraw", Pq, Ib, XX },
Ia_psraw_Nq_Ib = { "psraw", "psraw", Nq, Ib, XX },
Ia_psraw_Pq_Qq = { "psraw", "psraw", Pq, Qq, XX },
Ia_psraw_Vdq_Ib = { "psraw", "psraw", Vdq, Ib, XX },
Ia_psraw_Udq_Ib = { "psraw", "psraw", Udq, Ib, XX },
Ia_psraw_Vdq_Wdq = { "psraw", "psraw", Vdq, Wdq, XX },
Ia_psrld_Pq_Ib = { "psrld", "psrld", Pq, Ib, XX },
Ia_psrld_Nq_Ib = { "psrld", "psrld", Nq, Ib, XX },
Ia_psrld_Pq_Qq = { "psrld", "psrld", Pq, Qq, XX },
Ia_psrld_Vdq_Ib = { "psrld", "psrld", Vdq, Ib, XX },
Ia_psrld_Udq_Ib = { "psrld", "psrld", Udq, Ib, XX },
Ia_psrld_Vdq_Wdq = { "psrld", "psrld", Vdq, Wdq, XX },
Ia_psrldq_Wdq_Ib = { "psrldq", "psrldq", Wdq, Ib, XX },
Ia_psrlq_Pq_Ib = { "psrlq", "psrlq", Pq, Ib, XX },
Ia_psrldq_Udq_Ib = { "psrldq", "psrldq", Udq, Ib, XX },
Ia_psrlq_Nq_Ib = { "psrlq", "psrlq", Nq, Ib, XX },
Ia_psrlq_Pq_Qq = { "psrlq", "psrlq", Pq, Qq, XX },
Ia_psrlq_Vdq_Ib = { "psrlq", "psrlq", Vdq, Ib, XX },
Ia_psrlq_Udq_Ib = { "psrlq", "psrlq", Udq, Ib, XX },
Ia_psrlq_Vdq_Wdq = { "psrlq", "psrlq", Vdq, Wdq, XX },
Ia_psrlw_Pq_Ib = { "psrlw", "psrlw", Pq, Ib, XX },
Ia_psrlw_Nq_Ib = { "psrlw", "psrlw", Nq, Ib, XX },
Ia_psrlw_Pq_Qq = { "psrlw", "psrlw", Pq, Qq, XX },
Ia_psrlw_Vdq_Ib = { "psrlw", "psrlw", Vdq, Ib, XX },
Ia_psrlw_Udq_Ib = { "psrlw", "psrlw", Udq, Ib, XX },
Ia_psrlw_Vdq_Wdq = { "psrlw", "psrlw", Vdq, Wdq, XX },
Ia_psubb_Pq_Qq = { "psubb", "psubb", Pq, Qq, XX },
Ia_psubb_Vdq_Wdq = { "psubb", "psubb", Vdq, Wdq, XX },
@ -1150,8 +1151,8 @@ Ia_ucomisd_Vsd_Wss = { "ucomisd", "ucomisd", Vsd, Wsd, XX },
Ia_ucomiss_Vss_Wss = { "ucomiss", "ucomiss", Vss, Wss, XX },
Ia_ud2a = { "ud2a", "ud2a", XX, XX, XX },
Ia_ud2b = { "ud2b", "ud2b", XX, XX, XX },
Ia_unpckhpd_Vpd_Wq = { "unpckhpd", "unpckhpd", Vpd, Wq, XX },
Ia_unpckhps_Vps_Wq = { "unpckhps", "unpckhps", Vps, Wq, XX },
Ia_unpckhpd_Vpd_Wdq = { "unpckhpd", "unpckhpd", Vpd, Wdq, XX },
Ia_unpckhps_Vps_Wdq = { "unpckhps", "unpckhps", Vps, Wdq, XX },
Ia_unpcklpd_Vpd_Wq = { "unpcklpd", "unpcklpd", Vpd, Wq, XX },
Ia_unpcklps_Vps_Wq = { "unpcklps", "unpcklps", Vps, Wq, XX },
Ia_verr = { "verr", "verr", Ew, XX, XX },