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- port 0x03c7 returns the DAC state (read = 11b, write = 00b)

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- pel data register returns 0x3f if the DAC is not in read mode
This commit is contained in:
Volker Ruppert 2003-01-11 11:18:04 +00:00
parent d18476b4ae
commit 2c93eb7600
2 changed files with 32 additions and 20 deletions
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49
bochs/iodev/vga.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: vga.cc,v 1.57 2003-01-01 21:21:29 vruppert Exp $
// $Id: vga.cc,v 1.58 2003-01-11 11:18:03 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -174,6 +174,7 @@ bx_vga_c::init(void)
BX_VGA_THIS s.pel.write_data_cycle = 0;
BX_VGA_THIS s.pel.read_data_register = 0;
BX_VGA_THIS s.pel.read_data_cycle = 0;
BX_VGA_THIS s.pel.dac_state = 0x01;
BX_VGA_THIS s.pel.mask = 0xff;
BX_VGA_THIS s.graphics_ctrl.index = 0;
@ -564,24 +565,33 @@ bx_vga_c::read(Bit32u address, unsigned io_len)
RETURN(BX_VGA_THIS s.pel.mask);
break;
case 0x03c7: /* DAC state, read = 11b, write = 00b */
RETURN(BX_VGA_THIS s.pel.dac_state);
break;
case 0x03c9: /* PEL Data Register, colors 00..FF */
switch (BX_VGA_THIS s.pel.read_data_cycle) {
case 0:
retval = BX_VGA_THIS s.pel.data[BX_VGA_THIS s.pel.read_data_register].red;
break;
case 1:
retval = BX_VGA_THIS s.pel.data[BX_VGA_THIS s.pel.read_data_register].green;
break;
case 2:
retval = BX_VGA_THIS s.pel.data[BX_VGA_THIS s.pel.read_data_register].blue;
break;
default:
retval = 0; // keep compiler happy
}
BX_VGA_THIS s.pel.read_data_cycle++;
if (BX_VGA_THIS s.pel.read_data_cycle >= 3) {
BX_VGA_THIS s.pel.read_data_cycle = 0;
BX_VGA_THIS s.pel.read_data_register++;
if (BX_VGA_THIS s.pel.dac_state == 0x03) {
switch (BX_VGA_THIS s.pel.read_data_cycle) {
case 0:
retval = BX_VGA_THIS s.pel.data[BX_VGA_THIS s.pel.read_data_register].red;
break;
case 1:
retval = BX_VGA_THIS s.pel.data[BX_VGA_THIS s.pel.read_data_register].green;
break;
case 2:
retval = BX_VGA_THIS s.pel.data[BX_VGA_THIS s.pel.read_data_register].blue;
break;
default:
retval = 0; // keep compiler happy
}
BX_VGA_THIS s.pel.read_data_cycle++;
if (BX_VGA_THIS s.pel.read_data_cycle >= 3) {
BX_VGA_THIS s.pel.read_data_cycle = 0;
BX_VGA_THIS s.pel.read_data_register++;
}
}
else {
retval = 0x3f;
}
RETURN(retval);
break;
@ -674,7 +684,6 @@ if (BX_VGA_THIS s.graphics_ctrl.odd_even ||
break;
case 0x03b4: /* CRTC Index Register (monochrome emulation modes) */
case 0x03c7: /* not sure but OpenBSD reads it a lot */
case 0x03cb: /* not sure but OpenBSD reads it a lot */
case 0x03c8: /* */
default:
@ -1021,11 +1030,13 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, bx_bool no_log)
case 0x03c7: // PEL address, read mode
BX_VGA_THIS s.pel.read_data_register = value;
BX_VGA_THIS s.pel.read_data_cycle = 0;
BX_VGA_THIS s.pel.dac_state = 0x03;
break;
case 0x03c8: /* PEL address write mode */
BX_VGA_THIS s.pel.write_data_register = value;
BX_VGA_THIS s.pel.write_data_cycle = 0;
BX_VGA_THIS s.pel.dac_state = 0x00;
break;
case 0x03c9: /* PEL Data Register, colors 00..FF */

3
bochs/iodev/vga.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: vga.h,v 1.21 2002-12-28 11:49:17 vruppert Exp $
// $Id: vga.h,v 1.22 2003-01-11 11:18:04 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -176,6 +176,7 @@ private:
Bit8u write_data_cycle; /* 0, 1, 2 */
Bit8u read_data_register;
Bit8u read_data_cycle; /* 0, 1, 2 */
Bit8u dac_state;
struct {
Bit8u red;
Bit8u green;