Got rid of Ctrl-M's in exception.cc, introduced with the
implementation of SYSCALL.
This commit is contained in:
Kevin Lawton
parent
6dff398915
commit
2baf4372d1
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: exception.cc,v 1.25 2002-10-03 04:52:39 bdenney Exp $
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// $Id: exception.cc,v 1.26 2002-10-06 18:05:21 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1070,63 +1070,63 @@ BX_CPU_C::SYSCALL(bxInstruction_c *i)
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SYSCALL_START:
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IF (MSR_EFER.SCE = 0) // Check if syscall/sysret are enabled.
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EXCEPTION [#UD]
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IF (LONG_MODE)
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SYSCALL_LONG_MODE
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ELSE // (LEGACY_MODE)
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SYSCALL_LEGACY_MODE
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SYSCALL_LONG_MODE:
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RCX.q = next_RIP
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R11.q = RFLAGS // with rf cleared
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IF (64BIT_MODE)
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temp_RIP.q = MSR_LSTAR
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ELSE // (COMPATIBILITY_MODE)
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temp_RIP.q = MSR_CSTAR
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CS.sel = MSR_STAR.SYSCALL_CS AND 0xFFFC
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CS.attr = 64-bit code,dpl0 // Always switch to 64-bit mode in long mode.
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CS.base = 0x00000000
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CS.limit = 0xFFFFFFFF
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SS.sel = MSR_STAR.SYSCALL_CS + 8
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SS.attr = 64-bit stack,dpl0
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SS.base = 0x00000000
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SS.limit = 0xFFFFFFFF
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RFLAGS = RFLAGS AND ~MSR_SFMASK
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RFLAGS.RF = 0
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CPL = 0
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RIP = temp_RIP
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EXIT
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SYSCALL_LEGACY_MODE:
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RCX.d = next_RIP
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temp_RIP.d = MSR_STAR.EIP
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CS.sel = MSR_STAR.SYSCALL_CS AND 0xFFFC
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CS.attr = 32-bit code,dpl0 // Always switch to 32-bit mode in legacy mode.
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CS.base = 0x00000000
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CS.limit = 0xFFFFFFFF
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SS.sel = MSR_STAR.SYSCALL_CS + 8
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SS.attr = 32-bit stack,dpl0
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SS.base = 0x00000000
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SS.limit = 0xFFFFFFFF
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RFLAGS.VM,IF,RF=0
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CPL = 0
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RIP = temp_RIP
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EXCEPTION [#UD]
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IF (LONG_MODE)
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SYSCALL_LONG_MODE
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ELSE // (LEGACY_MODE)
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SYSCALL_LEGACY_MODE
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SYSCALL_LONG_MODE:
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RCX.q = next_RIP
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R11.q = RFLAGS // with rf cleared
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IF (64BIT_MODE)
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temp_RIP.q = MSR_LSTAR
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ELSE // (COMPATIBILITY_MODE)
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temp_RIP.q = MSR_CSTAR
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CS.sel = MSR_STAR.SYSCALL_CS AND 0xFFFC
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CS.attr = 64-bit code,dpl0 // Always switch to 64-bit mode in long mode.
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CS.base = 0x00000000
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CS.limit = 0xFFFFFFFF
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SS.sel = MSR_STAR.SYSCALL_CS + 8
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SS.attr = 64-bit stack,dpl0
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SS.base = 0x00000000
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SS.limit = 0xFFFFFFFF
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RFLAGS = RFLAGS AND ~MSR_SFMASK
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RFLAGS.RF = 0
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CPL = 0
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RIP = temp_RIP
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EXIT
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SYSCALL_LEGACY_MODE:
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RCX.d = next_RIP
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temp_RIP.d = MSR_STAR.EIP
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CS.sel = MSR_STAR.SYSCALL_CS AND 0xFFFC
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CS.attr = 32-bit code,dpl0 // Always switch to 32-bit mode in legacy mode.
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CS.base = 0x00000000
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CS.limit = 0xFFFFFFFF
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SS.sel = MSR_STAR.SYSCALL_CS + 8
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SS.attr = 32-bit stack,dpl0
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SS.base = 0x00000000
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SS.limit = 0xFFFFFFFF
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RFLAGS.VM,IF,RF=0
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CPL = 0
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RIP = temp_RIP
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EXIT
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*/
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@ -1200,53 +1200,53 @@ BX_CPU_C::SYSRET(bxInstruction_c *i)
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/* from AMD manual
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SYSRET_START:
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IF (MSR_EFER.SCE = 0) // Check if syscall/sysret are enabled.
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EXCEPTION [#UD]
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IF ((!PROTECTED_MODE) || (CPL != 0))
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EXCEPTION [#GP(0)] // SYSRET requires protected mode, cpl0
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IF (64BIT_MODE)
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SYSRET_64BIT_MODE
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ELSE // (!64BIT_MODE)
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SYSRET_NON_64BIT_MODE
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SYSRET_64BIT_MODE:
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IF (OPERAND_SIZE = 64) // Return to 64-bit mode.
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{
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CS.sel = (MSR_STAR.SYSRET_CS + 16) OR 3
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CS.base = 0x00000000
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CS.limit = 0xFFFFFFFF
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CS.attr = 64-bit code,dpl3
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temp_RIP.q = RCX
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}
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ELSE // Return to 32-bit compatibility mode.
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{
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CS.sel = MSR_STAR.SYSRET_CS OR 3
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CS.base = 0x00000000
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CS.limit = 0xFFFFFFFF
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CS.attr = 32-bit code,dpl3
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temp_RIP.d = RCX
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}
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SS.sel = MSR_STAR.SYSRET_CS + 8 // SS selector is changed,
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// SS base, limit, attributes unchanged.
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RFLAGS.q = R11 // RF=0,VM=0
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CPL = 3
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RIP = temp_RIP
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EXIT
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SYSRET_NON_64BIT_MODE:
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CS.sel = MSR_STAR.SYSRET_CS OR 3 // Return to 32-bit legacy protected mode.
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CS.base = 0x00000000
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CS.limit = 0xFFFFFFFF
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CS.attr = 32-bit code,dpl3
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temp_RIP.d = RCX
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SS.sel = MSR_STAR.SYSRET_CS + 8 // SS selector is changed.
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// SS base, limit, attributes unchanged.
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RFLAGS.IF = 1
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CPL = 3
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RIP = temp_RIP
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IF (MSR_EFER.SCE = 0) // Check if syscall/sysret are enabled.
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EXCEPTION [#UD]
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IF ((!PROTECTED_MODE) || (CPL != 0))
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EXCEPTION [#GP(0)] // SYSRET requires protected mode, cpl0
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IF (64BIT_MODE)
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SYSRET_64BIT_MODE
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ELSE // (!64BIT_MODE)
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SYSRET_NON_64BIT_MODE
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SYSRET_64BIT_MODE:
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IF (OPERAND_SIZE = 64) // Return to 64-bit mode.
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{
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CS.sel = (MSR_STAR.SYSRET_CS + 16) OR 3
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CS.base = 0x00000000
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CS.limit = 0xFFFFFFFF
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CS.attr = 64-bit code,dpl3
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temp_RIP.q = RCX
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}
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ELSE // Return to 32-bit compatibility mode.
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{
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CS.sel = MSR_STAR.SYSRET_CS OR 3
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CS.base = 0x00000000
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CS.limit = 0xFFFFFFFF
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CS.attr = 32-bit code,dpl3
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temp_RIP.d = RCX
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}
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SS.sel = MSR_STAR.SYSRET_CS + 8 // SS selector is changed,
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// SS base, limit, attributes unchanged.
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RFLAGS.q = R11 // RF=0,VM=0
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CPL = 3
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RIP = temp_RIP
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EXIT
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SYSRET_NON_64BIT_MODE:
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CS.sel = MSR_STAR.SYSRET_CS OR 3 // Return to 32-bit legacy protected mode.
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CS.base = 0x00000000
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CS.limit = 0xFFFFFFFF
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CS.attr = 32-bit code,dpl3
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temp_RIP.d = RCX
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SS.sel = MSR_STAR.SYSRET_CS + 8 // SS selector is changed.
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// SS base, limit, attributes unchanged.
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RFLAGS.IF = 1
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CPL = 3
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RIP = temp_RIP
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EXIT
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*/
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@ -1276,47 +1276,47 @@ SYSRET_NON_64BIT_MODE:
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temp_RIP = RCX;
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}
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else { // Return to 32-bit compatibility mode.
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parse_selector((MSR_STAR >> 48) | 3, &cs_selector);
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fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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}
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else { // Return to 32-bit compatibility mode.
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parse_selector((MSR_STAR >> 48) | 3, &cs_selector);
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fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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parse_descriptor(dword1, dword2, &cs_descriptor);
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load_cs(&cs_selector, &cs_descriptor, 3);
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temp_RIP = ECX;
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}
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parse_selector((MSR_STAR >> 48) + 8, &ss_selector);
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fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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temp_RIP = ECX;
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}
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parse_selector((MSR_STAR >> 48) + 8, &ss_selector);
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fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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parse_descriptor(dword1, dword2, &ss_descriptor);
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load_ss(&ss_selector, &ss_descriptor, 0);
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// SS base, limit, attributes unchanged.
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write_eflags(R11,1,1,1,1);
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RIP = temp_RIP;
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}
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else { // (!64BIT_MODE)
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parse_selector((MSR_STAR >> 48) + 16, &cs_selector);
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fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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// SS base, limit, attributes unchanged.
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write_eflags(R11,1,1,1,1);
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RIP = temp_RIP;
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}
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else { // (!64BIT_MODE)
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parse_selector((MSR_STAR >> 48) + 16, &cs_selector);
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fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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parse_descriptor(dword1, dword2, &cs_descriptor);
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load_cs(&cs_selector, &cs_descriptor, 3);
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temp_RIP = ECX;
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parse_selector((MSR_STAR >> 48) + 8, &ss_selector);
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fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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temp_RIP = ECX;
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parse_selector((MSR_STAR >> 48) + 8, &ss_selector);
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fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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parse_descriptor(dword1, dword2, &ss_descriptor);
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load_ss(&ss_selector, &ss_descriptor, 0);
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BX_CPU_THIS_PTR assert_IF ();
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RIP = temp_RIP;
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BX_CPU_THIS_PTR assert_IF ();
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RIP = temp_RIP;
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}
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}
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#endif // BX_SUPPORT_X86_64
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