Fixed a problem in LDMXCSR instruction
Beta version of FXSAVE/FXRSTOR instructions implementation (still imcomplete, doesn't fully restore FPU state)
This commit is contained in:
Stanislav Shwartsman
parent
6f798350f1
commit
2b2e773dde
168
bochs/cpu/sse.cc
168
bochs/cpu/sse.cc
@ -48,9 +48,13 @@ void BX_CPU_C::LDMXCSR(bxInstruction_c *i)
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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read_virtual_dword(i->seg(), RMAddr(i), &BX_MXCSR_REGISTER);
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if(BX_MXCSR_REGISTER & ~MXCSR_MASK)
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Bit32u new_mxcsr;
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read_virtual_dword(i->seg(), RMAddr(i), &new_mxcsr);
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if(new_mxcsr & ~MXCSR_MASK)
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exception(BX_GP_EXCEPTION, 0, 0);
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BX_MXCSR_REGISTER = new_mxcsr;
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#else
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BX_INFO(("LDMXCSR: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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@ -71,20 +75,176 @@ void BX_CPU_C::STMXCSR(bxInstruction_c *i)
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#endif
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}
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/* 0F AE Grp15 000 */
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void BX_CPU_C::FXSAVE(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_INFO(("FXSAVE: SSE instruction still not implemented"));
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BxPackedXmmRegister xmm;
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Bit16u twd = BX_CPU_THIS_PTR the_i387.soft.twd, tbd = 0;
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unsigned index;
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xmm.xmm16u(0) = BX_CPU_THIS_PTR the_i387.soft.cwd;
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xmm.xmm16u(1) = BX_CPU_THIS_PTR the_i387.soft.swd;
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if(twd & 0x0003 == 0x0003) tbd |= 0x010000;
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if(twd & 0x000c == 0x000c) tbd |= 0x020000;
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if(twd & 0x0030 == 0x0030) tbd |= 0x040000;
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if(twd & 0x00c0 == 0x00c0) tbd |= 0x080000;
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if(twd & 0x0300 == 0x0300) tbd |= 0x100000;
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if(twd & 0x0c00 == 0x0c00) tbd |= 0x200000;
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if(twd & 0x3000 == 0x3000) tbd |= 0x400000;
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if(twd & 0xc000 == 0xc000) tbd |= 0x800000;
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xmm.xmm16u(2) = tbd;
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/* x87 FPU Opcode (16 bits) */
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/* The lower 11 bits contain the FPU opcode, upper 5 bits are reserved */
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xmm.xmm16u(3) = 0; /* still not implemented */
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/*
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* x87 FPU IP Offset (32 bits)
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* The contents of this field differ depending on the current
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* addressing mode (16/32 bit) when the FXSAVE instruction was executed:
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* + 32-bit mode-32-bit IP offset
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* + 16-bit mode-low 16 bits are IP offset; high 16 bits are reserved.
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*
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* x87 CS FPU IP Selector (16 bits)
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*/
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xmm.xmm64u(1) = 0; /* still not implemented */
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writeVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &xmm);
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/*
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* x87 FPU Instruction Operand (Data) Pointer Offset (32 bits)
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* The contents of this field differ depending on the current
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* addressing mode (16/32 bit) when the FXSAVE instruction was executed:
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* + 32-bit mode-32-bit offset
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* + 16-bit mode-low 16 bits are offset; high 16 bits are reserved.
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*
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* x87 DS FPU Instruction Operand (Data) Pointer Selector (16 bits)
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*/
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xmm.xmm64u(0) = 0; /* still not implemented */
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xmm.xmm32u(2) = BX_MXCSR_REGISTER;
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xmm.xmm32u(3) = MXCSR_MASK;
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writeVirtualDQwordAligned(i->seg(), RMAddr(i) + 16, (Bit8u *) &xmm);
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/* store i387 register file */
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for(index=0; index < 8; index++)
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{
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Bit8u *r387 = (Bit8u *) &(BX_CPU_THIS_PTR the_i387.soft.st_space[index]);
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writeVirtualDQwordAligned(i->seg(), RMAddr(i)+index*16+32, r387);
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}
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/* store XMM register file */
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for(index=0; index < BX_XMM_REGISTERS; index++)
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{
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Bit8u *r128 = (Bit8u *) &(BX_CPU_THIS_PTR xmm[index]);
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writeVirtualDQwordAligned(i->seg(), RMAddr(i)+index*16+160, r128);
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}
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/* do not touch reserved fields */
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#else
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BX_INFO(("FXSAVE: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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/* 0F AE Grp15 001 */
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void BX_CPU_C::FXRSTOR(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_INFO(("FXRSTOR : SSE instruction still not implemented"));
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BxPackedXmmRegister xmm;
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Bit32u tbd, twd = 0;
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unsigned index;
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readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &xmm);
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BX_CPU_THIS_PTR the_i387.soft.cwd = xmm.xmm16u(0);
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BX_CPU_THIS_PTR the_i387.soft.swd = xmm.xmm16u(1);
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/* TOS restore still not implemented */
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/* FOO/FPU IP restore still not implemented */
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/*
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* Note that the original format for FTW can be recreated from the stored
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* FTW valid bits and the stored 80-bit FP data (assuming the stored data
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* was not the contents of MMX registers) using the following table:
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| Exponent | Exponent | Fraction | J,M bits | FTW valid | x87 FTW |
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| all 1s | all 0s | all 0s | | | |
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-------------------------------------------------------------------
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| 0 | 0 | 0 | 0x | 1 | S 10 |
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| 0 | 0 | 0 | 1x | 1 | V 00 |
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-------------------------------------------------------------------
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| 0 | 0 | 1 | 00 | 1 | S 10 |
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| 0 | 0 | 1 | 10 | 1 | V 00 |
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-------------------------------------------------------------------
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| 0 | 1 | 0 | 0x | 1 | S 10 |
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| 0 | 1 | 0 | 1x | 1 | V 10 |
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-------------------------------------------------------------------
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| 0 | 1 | 1 | 00 | 1 | S 01 |
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| 0 | 1 | 1 | 10 | 1 | V 10 |
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-------------------------------------------------------------------
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| 1 | 0 | 0 | 1x | 1 | S 10 |
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| 1 | 0 | 0 | 1x | 1 | V 10 |
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-------------------------------------------------------------------
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| 1 | 0 | 1 | 00 | 1 | S 10 |
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| 1 | 0 | 1 | 10 | 1 | V 10 |
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-------------------------------------------------------------------
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| all combinations above | 1 | E 11 |
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*
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* The J-bit is defined to be the 1-bit binary integer to the left
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* of the decimal place in the significand.
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*
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* The M-bit is defined to be the most significant bit of the fractional
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* portion of the significand (i.e., the bit immediately to the right of
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* the decimal place). When the M-bit is the most significant bit of the
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* fractional portion of the significand, it must be 0 if the fraction
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* is all 0's.
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*/ /* still not implemented */
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tbd = xmm.xmm16u(2);
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if(tbd & 0x010000) twd |= 0x0003;
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if(tbd & 0x020000) twd |= 0x000c;
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if(tbd & 0x040000) twd |= 0x0030;
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if(tbd & 0x080000) twd |= 0x00c0;
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if(tbd & 0x100000) twd |= 0x0300;
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if(tbd & 0x200000) twd |= 0x0c00;
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if(tbd & 0x400000) twd |= 0x3000;
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if(tbd & 0x800000) twd |= 0xc000;
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BX_CPU_THIS_PTR the_i387.soft.twd = twd;
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readVirtualDQwordAligned(i->seg(), RMAddr(i) + 16, (Bit8u *) &xmm);
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/* FPU DP restore still not implemented */
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Bit32u new_mxcsr = xmm.xmm32u(2);
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Bit32u mxcsr_msk = xmm.xmm32u(3);
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if(! mxcsr_msk) mxcsr_msk = MXCSR_MASK;
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if(new_mxcsr & ~mxcsr_msk)
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exception(BX_GP_EXCEPTION, 0, 0);
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BX_MXCSR_REGISTER = new_mxcsr;
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/* load i387 register file */
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for(index=0; index < 8; index++)
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{
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Bit8u *r387 = (Bit8u *) &(BX_CPU_THIS_PTR the_i387.soft.st_space[index]);
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readVirtualDQwordAligned(i->seg(), RMAddr(i)+index*16+32, r387);
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}
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/* load XMM register file */
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for(index=0; index < BX_XMM_REGISTERS; index++)
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{
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Bit8u *r128 = (Bit8u *) &(BX_CPU_THIS_PTR xmm[index]);
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readVirtualDQwordAligned(i->seg(), RMAddr(i)+index*16+160, r128);
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}
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#else
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BX_INFO(("FXRSTOR: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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