- update patch so it apply cleanly
This commit is contained in:
Christophe Bothamy
parent
44502c00dc
commit
298903fbed
@ -1,102 +1,224 @@
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----------------------------------------------------------------------
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Patch name: patch.sysenterexit-mrieker
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Author: Mike Rieker
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Date: 27 June 2002
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Author: Mike Rieker, updated by cbothamy
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Date: Mon Jan 20 14:42:21 CET 2003
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Detailed description:
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This patch adds sysenter/sysexit functions support
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for cpu >= Pentium-Pro
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For now, support must be explicitely enabled in config.h
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#define BX_SUPPORT_SYSENTEREXIT 1
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for cpu >= Pentium-Pro.
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SEP is not implemented for x86-64 yet.
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Support must be explicitely enabled with ./configure --enable-sep
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Patch was created with:
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cvs diff -u
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Apply patch to what version:
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cvs checked out on 27 June 2002
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cvs checked out on Mon Jan 20 14:42:21 CET 2003
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Instructions:
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To patch, go to main bochs directory.
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Type "patch -p0 < THIS_PATCH_FILE".
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----------------------------------------------------------------------
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Index: configure
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===================================================================
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RCS file: /cvsroot/bochs/bochs/configure,v
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retrieving revision 1.197
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diff -u -r1.197 configure
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--- configure 10 Jan 2003 22:31:41 -0000 1.197
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+++ configure 20 Jan 2003 14:36:47 -0000
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@@ -1,5 +1,5 @@
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#! /bin/sh
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-# From configure.in Id: configure.in,v 1.196 2003/01/04 19:22:47 bdenney Exp .
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+# From configure.in Id: configure.in,v 1.197 2003/01/10 22:32:38 cbothamy Exp .
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# Guess values for system-dependent variables and create Makefiles.
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# Generated by GNU Autoconf 2.53.
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#
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@@ -1041,6 +1041,7 @@
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--enable-mmx compile in MMX emulation
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--enable-fpu compile in FPU emulation
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--enable-sse SSE/SSE2 support (--enable-sse=no|1|2)
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+ --enable-sep SYSENTER/SYSEXIT support
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--enable-x86-debugger x86 debugger support
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--enable-cdrom CDROM support
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--enable-sb16=xxx Sound Blaster 16 Support (xxx=dummy|win|linux|freebsd)
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@@ -4207,7 +4208,7 @@
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case $host in
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*-*-irix6*)
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# Find out which ABI we are using.
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- echo '#line 4210 "configure"' > conftest.$ac_ext
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+ echo '#line 4211 "configure"' > conftest.$ac_ext
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if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
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(eval $ac_compile) 2>&5
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ac_status=$?
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@@ -4757,7 +4758,7 @@
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save_CFLAGS="$CFLAGS"
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CFLAGS="$CFLAGS -o out/conftest2.$ac_objext"
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compiler_c_o=no
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-if { (eval echo configure:4760: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>out/conftest.err; } && test -s out/conftest2.$ac_objext; then
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+if { (eval echo configure:4761: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>out/conftest.err; } && test -s out/conftest2.$ac_objext; then
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# The compiler can only warn and ignore the option if not recognized
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# So say no if there are warnings
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if test -s out/conftest.err; then
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@@ -6588,7 +6589,7 @@
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lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
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lt_status=$lt_dlunknown
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cat > conftest.$ac_ext <<EOF
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-#line 6591 "configure"
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+#line 6592 "configure"
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#include "confdefs.h"
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#if HAVE_DLFCN_H
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@@ -6686,7 +6687,7 @@
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lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
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lt_status=$lt_dlunknown
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cat > conftest.$ac_ext <<EOF
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-#line 6689 "configure"
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+#line 6690 "configure"
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#include "confdefs.h"
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#if HAVE_DLFCN_H
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@@ -8728,7 +8729,7 @@
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lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
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lt_status=$lt_dlunknown
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cat > conftest.$ac_ext <<EOF
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-#line 8731 "configure"
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+#line 8732 "configure"
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#include "confdefs.h"
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#if HAVE_DLFCN_H
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@@ -20607,6 +20608,39 @@
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_ACEOF
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fi
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+
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+echo "$as_me:$LINENO: checking for SEP support" >&5
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+echo $ECHO_N "checking for SEP support... $ECHO_C" >&6
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+# Check whether --enable-sep or --disable-sep was given.
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+if test "${enable_sep+set}" = set; then
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+ enableval="$enable_sep"
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+ if test "$enableval" = yes; then
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+ echo "$as_me:$LINENO: result: yes" >&5
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+echo "${ECHO_T}yes" >&6
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+ cat >>confdefs.h <<\_ACEOF
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+#define BX_SUPPORT_SEP 1
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+_ACEOF
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+
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+ elif test "$enableval" = no; then
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+ echo "$as_me:$LINENO: result: no" >&5
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+echo "${ECHO_T}no" >&6
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+ cat >>confdefs.h <<\_ACEOF
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+#define BX_SUPPORT_SEP 0
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+_ACEOF
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+
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+ fi
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+
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+else
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+
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+ echo "$as_me:$LINENO: result: no" >&5
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+echo "${ECHO_T}no" >&6
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+ cat >>confdefs.h <<\_ACEOF
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+#define BX_SUPPORT_SEP 0
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+_ACEOF
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+
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+
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+
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+fi;
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echo "$as_me:$LINENO: checking for x86 debugger support" >&5
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echo $ECHO_N "checking for x86 debugger support... $ECHO_C" >&6
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Index: configure.in
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===================================================================
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RCS file: /cvsroot/bochs/bochs/configure.in,v
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retrieving revision 1.197
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diff -u -r1.197 configure.in
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--- configure.in 10 Jan 2003 22:32:38 -0000 1.197
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+++ configure.in 20 Jan 2003 14:36:48 -0000
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@@ -1371,6 +1371,23 @@
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AC_DEFINE(BX_SUPPORT_SSE, 0)
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fi
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+AC_MSG_CHECKING(for SEP support)
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+AC_ARG_ENABLE(sep,
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+ [ --enable-sep SYSENTER/SYSEXIT support],
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+ [if test "$enableval" = yes; then
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+ AC_MSG_RESULT(yes)
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+ AC_DEFINE(BX_SUPPORT_SEP, 1)
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+ elif test "$enableval" = no; then
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+ AC_MSG_RESULT(no)
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+ AC_DEFINE(BX_SUPPORT_SEP, 0)
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+ fi
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+ ],
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+ [
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+ AC_MSG_RESULT(no)
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+ AC_DEFINE(BX_SUPPORT_SEP, 0)
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+ ]
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+ )
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+
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AC_MSG_CHECKING(for x86 debugger support)
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AC_ARG_ENABLE(x86-debugger,
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[ --enable-x86-debugger x86 debugger support],
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Index: config.h.in
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===================================================================
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RCS file: /cvsroot/bochs/bochs/config.h.in,v
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retrieving revision 1.50
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diff -u -r1.50 config.h.in
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--- config.h.in 5 Jun 2002 03:59:30 -0000 1.50
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+++ config.h.in 27 Jun 2002 21:27:40 -0000
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@@ -189,6 +189,13 @@
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retrieving revision 1.102
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diff -u -r1.102 config.h.in
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--- config.h.in 10 Jan 2003 22:32:42 -0000 1.102
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+++ config.h.in 20 Jan 2003 14:36:48 -0000
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@@ -683,6 +683,7 @@
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#define BX_SUPPORT_FPU 0
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#define BX_SUPPORT_MMX 0
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#define BX_SUPPORT_SSE 0
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+#define BX_SUPPORT_SEP 0
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#define BX_SUPPORT_4MEG_PAGES 0
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#define BX_SupportGuest2HostTLB 0
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#define BX_SupportRepeatSpeedups 0
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@@ -735,6 +736,10 @@
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#endif
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#endif
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#define BX_SUPPORT_V8086_MODE 1
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+// SYSENTER / SYSEXIT support
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+#define BX_SUPPORT_SYSENTEREXIT 0
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+
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+#if (BX_CPU_LEVEL<6 && BX_SUPPORT_SYSENTEREXIT)
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+#if (BX_CPU_LEVEL<6 && BX_SUPPORT_SEP)
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+#error SYSENTER/SYSEXIT only supported with CPU_LEVEL >= 6
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+#endif
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+
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// Support shadowing of ROM from C0000 to FFFFF.
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// This allows that region to be written to.
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#define BX_SHADOW_RAM 0
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#if BX_SUPPORT_X86_64
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// Sanity checks to ensure that you cannot accidently use conflicting options.
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@@ -752,6 +757,10 @@
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#endif
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#if !BX_SUPPORT_4MEG_PAGES
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#error X86-64 requires Page Size Extension (PSE)
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+#endif
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+
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+#if BX_SUPPORT_SEP
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+#error SYSENTER/SYSEXIT not implemented for X86-64
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#endif
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#endif
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Index: cpu/cpu.h
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
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retrieving revision 1.22
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diff -u -r1.22 cpu.h
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--- cpu/cpu.h 5 Jun 2002 21:51:30 -0000 1.22
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+++ cpu/cpu.h 27 Jun 2002 21:27:47 -0000
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@@ -219,6 +219,11 @@
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#define BX_MSR_BBL_CR_TRIG 0x011a
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#define BX_MSR_BBL_CR_BUSY 0x011b
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#define BX_MSR_BBL_CR_CTL3 0x011e
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+#if BX_SUPPORT_SYSENTEREXIT
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+# define BX_MSR_SYSENTER_CS 0x0174
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+# define BX_MSR_SYSENTER_ESP 0x0175
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+# define BX_MSR_SYSENTER_EIP 0x0176
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retrieving revision 1.125
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diff -u -r1.125 cpu.h
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--- cpu/cpu.h 22 Dec 2002 20:48:45 -0000 1.125
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+++ cpu/cpu.h 20 Jan 2003 14:36:49 -0000
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@@ -289,6 +289,11 @@
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#define BX_MSR_BBL_CR_TRIG 0x011a
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#define BX_MSR_BBL_CR_BUSY 0x011b
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#define BX_MSR_BBL_CR_CTL3 0x011e
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+#if BX_SUPPORT_SEP
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+# define BX_MSR_SYSENTER_CS 0x0174
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+# define BX_MSR_SYSENTER_ESP 0x0175
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+# define BX_MSR_SYSENTER_EIP 0x0176
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+#endif
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#define BX_MSR_MCG_CAP 0x0179
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#define BX_MSR_MCG_STATUS 0x017a
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#define BX_MSR_MCG_CTL 0x017b
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@@ -276,7 +281,6 @@
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#endif
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} bx_flags_reg_t;
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-
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#if BX_CPU_LEVEL >= 2
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typedef struct {
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Bit32u val32; // 32bit value of register
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@@ -581,6 +585,7 @@
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virtual ~bx_generic_apic_c ();
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virtual void init ();
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virtual void hwreset () { }
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+ virtual BX_CPU_C *get_cpu (void);
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Bit32u get_base (void) { return base_addr; }
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void set_base (Bit32u newbase);
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void set_id (Bit8u newid);
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@@ -641,7 +646,7 @@
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BX_CPU_C *cpu;
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virtual void hwreset ();
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virtual void init ();
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- BX_CPU_C *get_cpu (Bit8u id);
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+ virtual BX_CPU_C *get_cpu (void);
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void set_id (Bit8u newid); // redefine to set cpu->name
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virtual char *get_name();
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virtual void write (Bit32u addr, Bit32u *data, unsigned len);
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@@ -820,6 +825,7 @@
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volatile Boolean async_event;
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volatile Boolean INTR;
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volatile Boolean kill_bochs_request;
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+ volatile Boolean nmi_queued;
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/* wether this CPU is the BSP always set for UP */
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Boolean bsp;
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@@ -871,6 +877,13 @@
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bx_guard_found_t guard_found;
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#define BX_MSR_MCG_CAP 0x0179
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#define BX_MSR_MCG_STATUS 0x017a
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#define BX_MSR_MCG_CTL 0x017b
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@@ -1504,6 +1509,13 @@
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#define TLB_GENERATION_MAX (BX_TLB_SIZE-1)
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#endif
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+ // SYSENTER/SYSEXIT instruction msr's
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+#if BX_SUPPORT_SYSENTEREXIT
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+#if BX_SUPPORT_SEP
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+ Bit32u sysenter_cs_msr;
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+ Bit32u sysenter_esp_msr;
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+ Bit32u sysenter_eip_msr;
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@ -105,115 +227,110 @@ diff -u -r1.22 cpu.h
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// for paging
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#if BX_USE_TLB
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struct {
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@@ -1349,6 +1362,8 @@
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BX_SMF void WRMSR(BxInstruction_t *);
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BX_SMF void RDTSC(BxInstruction_t *);
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BX_SMF void RDMSR(BxInstruction_t *);
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+ BX_SMF void SYSENTER(BxInstruction_t *);
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+ BX_SMF void SYSEXIT(BxInstruction_t *);
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@@ -2498,6 +2510,8 @@
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BX_SMF void WRMSR(bxInstruction_c *);
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BX_SMF void RDTSC(bxInstruction_c *);
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BX_SMF void RDMSR(bxInstruction_c *);
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+ BX_SMF void SYSENTER(bxInstruction_c *);
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+ BX_SMF void SYSEXIT(bxInstruction_c *);
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BX_SMF void SetCR0(Bit32u val_32);
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BX_SMF void dynamic_translate(void);
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BX_SMF void dynamic_init(void);
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#if BX_CPU_LEVEL >= 4
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BX_SMF void SetCR4(Bit32u val_32);
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Index: cpu/fetchdecode.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/fetchdecode.cc,v
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retrieving revision 1.7
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diff -u -r1.7 fetchdecode.cc
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--- cpu/fetchdecode.cc 3 Oct 2001 13:10:37 -0000 1.7
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+++ cpu/fetchdecode.cc 27 Jun 2002 21:27:48 -0000
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@@ -1174,8 +1174,13 @@
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/* 0F 31 */ { 0, &BX_CPU_C::RDTSC },
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/* 0F 32 */ { 0, &BX_CPU_C::RDMSR },
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/* 0F 33 */ { 0, &BX_CPU_C::BxError },
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retrieving revision 1.41
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diff -u -r1.41 fetchdecode.cc
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--- cpu/fetchdecode.cc 22 Dec 2002 21:48:22 -0000 1.41
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+++ cpu/fetchdecode.cc 20 Jan 2003 14:36:50 -0000
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@@ -1620,8 +1620,13 @@
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/* 0F 31 */ { 0, &BX_CPU_C::RDTSC },
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/* 0F 32 */ { 0, &BX_CPU_C::RDMSR },
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/* 0F 33 */ { 0, &BX_CPU_C::BxError },
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- /* 0F 34 */ { 0, &BX_CPU_C::BxError },
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- /* 0F 35 */ { 0, &BX_CPU_C::BxError },
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+#if BX_SUPPORT_SYSENTEREXIT
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+ /* 0F 34 */ { 0, &BX_CPU_C::SYSENTER },
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+ /* 0F 35 */ { 0, &BX_CPU_C::SYSEXIT },
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+#else
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/* 0F 34 */ { 0, &BX_CPU_C::BxError },
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/* 0F 35 */ { 0, &BX_CPU_C::BxError },
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+ /* 0F 34 */ { 0, &BX_CPU_C::BxError },
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+ /* 0F 35 */ { 0, &BX_CPU_C::BxError },
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+#endif
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/* 0F 36 */ { 0, &BX_CPU_C::BxError },
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/* 0F 37 */ { 0, &BX_CPU_C::BxError },
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/* 0F 38 */ { 0, &BX_CPU_C::BxError },
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/* 0F 36 */ { 0, &BX_CPU_C::BxError },
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/* 0F 37 */ { 0, &BX_CPU_C::BxError },
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/* 0F 38 */ { 0, &BX_CPU_C::BxError },
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Index: cpu/proc_ctrl.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/proc_ctrl.cc,v
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retrieving revision 1.22
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diff -u -r1.22 proc_ctrl.cc
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--- cpu/proc_ctrl.cc 19 Jun 2002 15:49:07 -0000 1.22
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+++ cpu/proc_ctrl.cc 27 Jun 2002 21:27:48 -0000
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@@ -968,8 +968,8 @@
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// ECX: vendor ID string
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EAX = 1; // 486 or pentium
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EBX = 0x756e6547; // "Genu"
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- EDX = 0x49656e69; // "ineI"
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- ECX = 0x6c65746e; // "ntel"
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+ EDX = 0x42656e69; // "ineB"
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+ ECX = 0x7368636f; // "ochs"
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break;
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retrieving revision 1.65
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diff -u -r1.65 proc_ctrl.cc
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--- cpu/proc_ctrl.cc 14 Jan 2003 07:46:05 -0000 1.65
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+++ cpu/proc_ctrl.cc 20 Jan 2003 14:36:51 -0000
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@@ -1358,7 +1358,8 @@
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// [7:7] MCE: Machine Check Exception
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// [8:8] CXS: CMPXCHG8B instruction
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// [9:9] APIC: APIC on Chip
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- // [11:10] Reserved
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+ // [10:10] Reserved
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+ // [11:11] SYSENTER/SYSEXIT support
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// [12:12] MTRR: Memory Type Range Reg
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// [13:13] PGE/PTE Global Bit
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// [14:14] MCA: Machine Check Architecture
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@@ -1413,7 +1414,11 @@
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#endif
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case 1:
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@@ -1030,16 +1030,20 @@
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model = 1; // Pentium Pro
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stepping = 3; // ???
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features |= (1<<4); // implement TSC
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+ features |= (1<<3); // implement 4M pages
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# if BX_SUPPORT_APIC
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features |= (1<<9); // APIC on chip
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# endif
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# if BX_SUPPORT_FPU
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features |= 0x01; // has FPU
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# endif
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+# if BX_SUPPORT_SYSENTEREXIT
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+ features |= (1<<11); // SYSENTER/SYSEXIT
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+# endif
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#if BX_SUPPORT_X86_64
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- features |= (1<<5); //AMD specific MSR's
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+ features |= (1<<5); // AMD specific MSR's
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+#endif
|
||||
+
|
||||
#else
|
||||
BX_PANIC(("CPUID: not implemented for > 6"));
|
||||
-#endif
|
||||
- features |= 8; // support page-size extension (4m pages)
|
||||
+#endif
|
||||
+#if BX_SUPPORT_SEP
|
||||
+ features |= (1<<11); // SYSENTER/SYSEXIT
|
||||
#endif
|
||||
|
||||
EAX = (family <<8) | (model<<4) | stepping;
|
||||
EBX = ECX = 0; // reserved
|
||||
@@ -1160,6 +1164,11 @@
|
||||
return features;
|
||||
@@ -1732,6 +1737,13 @@
|
||||
|
||||
/* We have the requested MSR register in ECX */
|
||||
switch(ECX) {
|
||||
+#if BX_SUPPORT_SYSENTEREXIT
|
||||
+ case BX_MSR_SYSENTER_CS: { EAX = BX_CPU_THIS_PTR sysenter_cs_msr; EDX = 0; return; }
|
||||
+ case BX_MSR_SYSENTER_ESP: { EAX = BX_CPU_THIS_PTR sysenter_esp_msr; EDX = 0; return; }
|
||||
+ case BX_MSR_SYSENTER_EIP: { EAX = BX_CPU_THIS_PTR sysenter_eip_msr; EDX = 0; return; }
|
||||
+#endif
|
||||
/* We have the requested MSR register in ECX */
|
||||
switch(ECX) {
|
||||
+
|
||||
+#if BX_SUPPORT_SEP
|
||||
+ case BX_MSR_SYSENTER_CS: { EAX = BX_CPU_THIS_PTR sysenter_cs_msr; EDX = 0; return; }
|
||||
+ case BX_MSR_SYSENTER_ESP: { EAX = BX_CPU_THIS_PTR sysenter_esp_msr; EDX = 0; return; }
|
||||
+ case BX_MSR_SYSENTER_EIP: { EAX = BX_CPU_THIS_PTR sysenter_eip_msr; EDX = 0; return; }
|
||||
+#endif
|
||||
+
|
||||
#if BX_CPU_LEVEL == 5
|
||||
/* The following registers are defined for Pentium only */
|
||||
case BX_MSR_P5_MC_ADDR:
|
||||
@@ -1236,6 +1245,15 @@
|
||||
/* The following registers are defined for Pentium only */
|
||||
case BX_MSR_P5_MC_ADDR:
|
||||
@@ -1857,6 +1869,17 @@
|
||||
|
||||
/* ECX has the MSR to write to */
|
||||
switch(ECX) {
|
||||
+#if BX_SUPPORT_SYSENTEREXIT
|
||||
+ case BX_MSR_SYSENTER_CS: {
|
||||
+ if (EAX & 3) BX_PANIC (("writing sysenter_cs_msr with non-kernel mode selector %X", EAX)); // not a bug according to book
|
||||
+ BX_CPU_THIS_PTR sysenter_cs_msr = EAX; // ... but very stOOpid
|
||||
+ return;
|
||||
+ }
|
||||
+ case BX_MSR_SYSENTER_ESP: { BX_CPU_THIS_PTR sysenter_esp_msr = EAX; return; }
|
||||
+ case BX_MSR_SYSENTER_EIP: { BX_CPU_THIS_PTR sysenter_eip_msr = EAX; return; }
|
||||
/* ECX has the MSR to write to */
|
||||
switch(ECX) {
|
||||
+
|
||||
+#if BX_SUPPORT_SEP
|
||||
+ case BX_MSR_SYSENTER_CS: {
|
||||
+ if (EAX & 3) BX_PANIC (("writing sysenter_cs_msr with non-kernel mode selector %X", EAX)); // not a bug according to book
|
||||
+ BX_CPU_THIS_PTR sysenter_cs_msr = EAX; // ... but very stOOpid
|
||||
+ return;
|
||||
+ }
|
||||
+ case BX_MSR_SYSENTER_ESP: { BX_CPU_THIS_PTR sysenter_esp_msr = EAX; return; }
|
||||
+ case BX_MSR_SYSENTER_EIP: { BX_CPU_THIS_PTR sysenter_eip_msr = EAX; return; }
|
||||
+#endif
|
||||
+
|
||||
#if BX_CPU_LEVEL == 5
|
||||
/* The following registers are defined for Pentium only */
|
||||
case BX_MSR_P5_MC_ADDR:
|
||||
@@ -1283,6 +1301,127 @@
|
||||
/* The following registers are defined for Pentium only */
|
||||
case BX_MSR_P5_MC_ADDR:
|
||||
@@ -1943,6 +1966,127 @@
|
||||
do_exception:
|
||||
exception(BX_GP_EXCEPTION, 0, 0);
|
||||
exception(BX_GP_EXCEPTION, 0, 0);
|
||||
|
||||
+}
|
||||
+
|
||||
+ void
|
||||
+BX_CPU_C::SYSENTER (BxInstruction_t *i)
|
||||
+BX_CPU_C::SYSENTER (bxInstruction_c *i)
|
||||
+{
|
||||
+#if BX_SUPPORT_SYSENTEREXIT
|
||||
+#if BX_SUPPORT_SEP
|
||||
+ if (!protected_mode ()) {
|
||||
+ BX_INFO (("sysenter not from protected mode"));
|
||||
+ exception (BX_GP_EXCEPTION, 0, 0);
|
||||
@ -227,39 +344,39 @@ diff -u -r1.22 proc_ctrl.cc
|
||||
+
|
||||
+ invalidate_prefetch_q ();
|
||||
+
|
||||
+ BX_CPU_THIS_PTR eflags.vm = 0; // do this just like the book says to do
|
||||
+ BX_CPU_THIS_PTR eflags.if_ = 0;
|
||||
+ BX_CPU_THIS_PTR eflags.rf = 0;
|
||||
+ BX_CPU_THIS_PTR set_VM(0); // do this just like the book says to do
|
||||
+ BX_CPU_THIS_PTR set_IF(0);
|
||||
+ BX_CPU_THIS_PTR set_RF(0);
|
||||
+
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value = BX_CPU_THIS_PTR sysenter_cs_msr;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.index = BX_CPU_THIS_PTR sysenter_cs_msr >> 3;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl = 0;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; // code segment
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; // non-conforming
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; // readable
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; // accessed
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; // segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // 4k granularity
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1; // 32-bit mode
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; // code segment
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; // non-conforming
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; // readable
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; // accessed
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; // segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // 4k granularity
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1; // 32-bit mode
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
|
||||
+
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = BX_CPU_THIS_PTR sysenter_cs_msr + 8;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index = (BX_CPU_THIS_PTR sysenter_cs_msr + 8) >> 3;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl = 0;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0; // data segment
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; // expand-up
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; // writeable
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; // accessed
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; // base address
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xFFFF; // segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; // 4k granularity
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; // 32-bit mode
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; // available for use by system
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0; // data segment
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; // expand-up
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; // writeable
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; // accessed
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; // base address
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xFFFF; // segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; // 4k granularity
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; // 32-bit mode
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; // available for use by system
|
||||
+
|
||||
+ // BX_INFO (("sysenter: old eip %X, esp %x, new eip %x, esp %X, edx %X", BX_CPU_THIS_PTR prev_eip, ESP, BX_CPU_THIS_PTR sysenter_eip_msr, BX_CPU_THIS_PTR sysenter_esp_msr, EDX));
|
||||
+
|
||||
@ -271,9 +388,9 @@ diff -u -r1.22 proc_ctrl.cc
|
||||
+}
|
||||
+
|
||||
+ void
|
||||
+BX_CPU_C::SYSEXIT (BxInstruction_t *i)
|
||||
+BX_CPU_C::SYSEXIT (bxInstruction_c *i)
|
||||
+{
|
||||
+#if BX_SUPPORT_SYSENTEREXIT
|
||||
+#if BX_SUPPORT_SEP
|
||||
+ if (!protected_mode ()) {
|
||||
+ BX_INFO (("sysexit not from protected mode"));
|
||||
+ exception (BX_GP_EXCEPTION, 0, 0);
|
||||
@ -296,31 +413,31 @@ diff -u -r1.22 proc_ctrl.cc
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.index = (BX_CPU_THIS_PTR sysenter_cs_msr + 16) >> 3;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl = 3;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; // code segment
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; // non-conforming
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; // readable
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; // accessed
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; // segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // 4k granularity
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1; // 32-bit mode
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; // code segment
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; // non-conforming
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; // readable
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; // accessed
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; // segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // 4k granularity
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1; // 32-bit mode
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
|
||||
+
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = (BX_CPU_THIS_PTR sysenter_cs_msr + 24) | 3;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index = (BX_CPU_THIS_PTR sysenter_cs_msr + 24) >> 3;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti = (BX_CPU_THIS_PTR sysenter_cs_msr >> 2) & 1;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl = 3;
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0; // data segment
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; // expand-up
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; // writeable
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; // accessed
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; // base address
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xFFFF; // segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; // 4k granularity
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; // 32-bit mode
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; // available for use by system
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0; // data segment
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; // expand-up
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; // writeable
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; // accessed
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; // base address
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xFFFF; // segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; // 4k granularity
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; // 32-bit mode
|
||||
+ BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; // available for use by system
|
||||
+
|
||||
+ // BX_INFO (("sysexit: old eip %X, esp %x, new eip %x, esp %X, eax %X", BX_CPU_THIS_PTR prev_eip, ESP, EDX, ECX, EAX));
|
||||
+
|
||||
@ -331,4 +448,4 @@ diff -u -r1.22 proc_ctrl.cc
|
||||
+#endif
|
||||
}
|
||||
|
||||
#if BX_X86_DEBUGGER
|
||||
#if BX_SUPPORT_X86_64
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user