- the CR start bit has no meaning in the PCI version
- set CR TXP bit during transmit operation - improved various debug and error messages
This commit is contained in:
Volker Ruppert
parent
c7dd4185a7
commit
28e36a2671
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ne2k.cc,v 1.78 2005-12-24 22:35:04 vruppert Exp $
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// $Id: ne2k.cc,v 1.79 2006-01-28 20:18:18 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -118,7 +118,7 @@ bx_ne2k_c::reset(unsigned type)
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// Set power-up conditions
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BX_NE2K_THIS s.CR.stop = 1;
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BX_NE2K_THIS s.CR.rdma_cmd = 4;
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BX_NE2K_THIS s.CR.rdma_cmd = 4;
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BX_NE2K_THIS s.ISR.reset = 1;
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BX_NE2K_THIS s.DCR.longaddr = 1;
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@ -138,7 +138,7 @@ bx_ne2k_c::read_cr(void)
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(BX_NE2K_THIS s.CR.tx_packet << 2) |
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(BX_NE2K_THIS s.CR.start << 1) |
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(BX_NE2K_THIS s.CR.stop));
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BX_DEBUG(("read CR returns 0x%08x", val));
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BX_DEBUG(("read CR returns 0x%02x", val));
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return val;
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}
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@ -191,7 +191,7 @@ bx_ne2k_c::write_cr(Bit32u value)
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BX_NE2K_THIS s.tx_bytes);
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}
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} else if (value & 0x04) {
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if (BX_NE2K_THIS s.CR.stop || !BX_NE2K_THIS s.CR.start) {
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if (BX_NE2K_THIS s.CR.stop || (!BX_NE2K_THIS s.CR.start && !BX_NE2K_THIS s.pci_enabled)) {
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if (BX_NE2K_THIS s.tx_bytes == 0) /* njh@bandsman.co.uk */
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return; /* Solaris9 probe */
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BX_PANIC(("CR write - tx start, dev in reset"));
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@ -201,6 +201,7 @@ bx_ne2k_c::write_cr(Bit32u value)
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BX_PANIC(("CR write - tx start, tx bytes == 0"));
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// Send the packet to the system driver
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BX_NE2K_THIS s.CR.tx_packet = 1;
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BX_NE2K_THIS ethdev->sendpkt(& BX_NE2K_THIS s.mem[BX_NE2K_THIS s.tx_page_start*256 - BX_NE2K_MEMSTART], BX_NE2K_THIS s.tx_bytes);
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// some more debug
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@ -428,113 +429,113 @@ bx_ne2k_c::asic_write(Bit32u offset, Bit32u value, unsigned io_len)
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Bit32u
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bx_ne2k_c::page0_read(Bit32u offset, unsigned int io_len)
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{
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BX_DEBUG(("page 0 read from port %04x, len=%u", (unsigned) offset,
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(unsigned) io_len));
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if (io_len > 1) {
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BX_ERROR(("bad length! page 0 read from port %04x, len=%u", (unsigned) offset,
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(unsigned) io_len)); /* encountered with win98 hardware probe */
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return 0;
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}
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Bit8u value = 0;
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if (io_len > 1) {
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BX_ERROR(("bad length! page 0 read from register 0x%02x, len=%u", offset,
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io_len)); /* encountered with win98 hardware probe */
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return value;
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}
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switch (offset) {
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case 0x1: // CLDA0
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return (BX_NE2K_THIS s.local_dma & 0xff);
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value = (BX_NE2K_THIS s.local_dma & 0xff);
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break;
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case 0x2: // CLDA1
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return (BX_NE2K_THIS s.local_dma >> 8);
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value = (BX_NE2K_THIS s.local_dma >> 8);
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break;
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case 0x3: // BNRY
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return (BX_NE2K_THIS s.bound_ptr);
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value = BX_NE2K_THIS s.bound_ptr;
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break;
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case 0x4: // TSR
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return ((BX_NE2K_THIS s.TSR.ow_coll << 7) |
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(BX_NE2K_THIS s.TSR.cd_hbeat << 6) |
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(BX_NE2K_THIS s.TSR.fifo_ur << 5) |
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(BX_NE2K_THIS s.TSR.no_carrier << 4) |
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(BX_NE2K_THIS s.TSR.aborted << 3) |
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(BX_NE2K_THIS s.TSR.collided << 2) |
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(BX_NE2K_THIS s.TSR.tx_ok));
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value = ((BX_NE2K_THIS s.TSR.ow_coll << 7) |
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(BX_NE2K_THIS s.TSR.cd_hbeat << 6) |
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(BX_NE2K_THIS s.TSR.fifo_ur << 5) |
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(BX_NE2K_THIS s.TSR.no_carrier << 4) |
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(BX_NE2K_THIS s.TSR.aborted << 3) |
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(BX_NE2K_THIS s.TSR.collided << 2) |
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(BX_NE2K_THIS s.TSR.tx_ok));
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break;
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case 0x5: // NCR
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return (BX_NE2K_THIS s.num_coll);
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value = BX_NE2K_THIS s.num_coll;
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break;
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case 0x6: // FIFO
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// reading FIFO is only valid in loopback mode
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BX_ERROR(("reading FIFO not supported yet"));
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return (BX_NE2K_THIS s.fifo);
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value = BX_NE2K_THIS s.fifo;
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break;
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case 0x7: // ISR
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return ((BX_NE2K_THIS s.ISR.reset << 7) |
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(BX_NE2K_THIS s.ISR.rdma_done << 6) |
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(BX_NE2K_THIS s.ISR.cnt_oflow << 5) |
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(BX_NE2K_THIS s.ISR.overwrite << 4) |
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(BX_NE2K_THIS s.ISR.tx_err << 3) |
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(BX_NE2K_THIS s.ISR.rx_err << 2) |
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(BX_NE2K_THIS s.ISR.pkt_tx << 1) |
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(BX_NE2K_THIS s.ISR.pkt_rx));
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value = ((BX_NE2K_THIS s.ISR.reset << 7) |
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(BX_NE2K_THIS s.ISR.rdma_done << 6) |
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(BX_NE2K_THIS s.ISR.cnt_oflow << 5) |
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(BX_NE2K_THIS s.ISR.overwrite << 4) |
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(BX_NE2K_THIS s.ISR.tx_err << 3) |
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(BX_NE2K_THIS s.ISR.rx_err << 2) |
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(BX_NE2K_THIS s.ISR.pkt_tx << 1) |
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(BX_NE2K_THIS s.ISR.pkt_rx));
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break;
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case 0x8: // CRDA0
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return (BX_NE2K_THIS s.remote_dma & 0xff);
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value = (BX_NE2K_THIS s.remote_dma & 0xff);
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break;
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case 0x9: // CRDA1
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return (BX_NE2K_THIS s.remote_dma >> 8);
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value = (BX_NE2K_THIS s.remote_dma >> 8);
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break;
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case 0xa: // reserved / RTL8029ID0
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if (BX_NE2K_THIS s.pci_enabled) {
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return (0x50);
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value = 0x50;
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} else {
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BX_INFO(("reserved read - page 0, 0xa"));
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return (0xff);
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value = 0xff;
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}
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break;
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case 0xb: // reserved / RTL8029ID1
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if (BX_NE2K_THIS s.pci_enabled) {
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return (0x43);
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value = 0x43;
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} else {
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BX_INFO(("reserved read - page 0, 0xb"));
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return (0xff);
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value = 0xff;
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}
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break;
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case 0xc: // RSR
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return ((BX_NE2K_THIS s.RSR.deferred << 7) |
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(BX_NE2K_THIS s.RSR.rx_disabled << 6) |
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(BX_NE2K_THIS s.RSR.rx_mbit << 5) |
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(BX_NE2K_THIS s.RSR.rx_missed << 4) |
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(BX_NE2K_THIS s.RSR.fifo_or << 3) |
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(BX_NE2K_THIS s.RSR.bad_falign << 2) |
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(BX_NE2K_THIS s.RSR.bad_crc << 1) |
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(BX_NE2K_THIS s.RSR.rx_ok));
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value = ((BX_NE2K_THIS s.RSR.deferred << 7) |
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(BX_NE2K_THIS s.RSR.rx_disabled << 6) |
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(BX_NE2K_THIS s.RSR.rx_mbit << 5) |
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(BX_NE2K_THIS s.RSR.rx_missed << 4) |
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(BX_NE2K_THIS s.RSR.fifo_or << 3) |
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(BX_NE2K_THIS s.RSR.bad_falign << 2) |
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(BX_NE2K_THIS s.RSR.bad_crc << 1) |
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(BX_NE2K_THIS s.RSR.rx_ok));
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break;
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case 0xd: // CNTR0
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return (BX_NE2K_THIS s.tallycnt_0);
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value = BX_NE2K_THIS s.tallycnt_0;
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break;
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case 0xe: // CNTR1
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return (BX_NE2K_THIS s.tallycnt_1);
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value = BX_NE2K_THIS s.tallycnt_1;
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break;
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case 0xf: // CNTR2
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return (BX_NE2K_THIS s.tallycnt_2);
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value = BX_NE2K_THIS s.tallycnt_2;
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break;
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default:
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BX_PANIC(("page 0 offset %04x out of range", (unsigned) offset));
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BX_PANIC(("page 0 register 0x%02x out of range", offset));
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}
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return(0);
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BX_DEBUG(("page 0 read from register 0x%02x, value=0x%02x", offset, value));
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return value;
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}
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void
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@ -542,9 +543,6 @@ bx_ne2k_c::page0_write(Bit32u offset, Bit32u value, unsigned io_len)
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{
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Bit8u value2;
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BX_DEBUG(("page 0 write to port %04x, len=%u", (unsigned) offset,
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(unsigned) io_len));
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// It appears to be a common practice to use outw on page0 regs...
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// break up outw into two outb's
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@ -556,6 +554,8 @@ bx_ne2k_c::page0_write(Bit32u offset, Bit32u value, unsigned io_len)
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return;
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}
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BX_DEBUG(("page 0 write to register 0x%02x, value=0x%02x", offset, value));
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switch (offset) {
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case 0x1: // PSTART
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BX_NE2K_THIS s.page_start = value;
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@ -731,7 +731,7 @@ bx_ne2k_c::page0_write(Bit32u offset, Bit32u value, unsigned io_len)
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break;
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default:
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BX_PANIC(("page 0 write, bad offset %0x", offset));
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BX_PANIC(("page 0 write, bad register 0x%02x", offset));
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}
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}
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@ -743,11 +743,10 @@ bx_ne2k_c::page0_write(Bit32u offset, Bit32u value, unsigned io_len)
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Bit32u
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bx_ne2k_c::page1_read(Bit32u offset, unsigned int io_len)
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{
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BX_DEBUG(("page 1 read from port %04x, len=%u", (unsigned) offset,
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(unsigned) io_len));
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BX_DEBUG(("page 1 read from register 0x%02x, len=%u", offset, io_len));
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if (io_len > 1)
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BX_PANIC(("bad length! page 1 read from port %04x, len=%u", (unsigned) offset,
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(unsigned) io_len));
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BX_PANIC(("bad length! page 1 read from register 0x%02x, len=%u", offset, io_len));
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switch (offset) {
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case 0x1: // PAR0-5
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@ -760,7 +759,7 @@ bx_ne2k_c::page1_read(Bit32u offset, unsigned int io_len)
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break;
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case 0x7: // CURR
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BX_DEBUG(("returning current page: %02x", (BX_NE2K_THIS s.curr_page)));
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BX_DEBUG(("returning current page: 0x%02x", (BX_NE2K_THIS s.curr_page)));
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return (BX_NE2K_THIS s.curr_page);
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case 0x8: // MAR0-7
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@ -775,7 +774,7 @@ bx_ne2k_c::page1_read(Bit32u offset, unsigned int io_len)
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break;
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default:
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BX_PANIC(("page 1 r offset %04x out of range", (unsigned) offset));
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BX_PANIC(("page 1 read register 0x%02x out of range", offset));
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}
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return (0);
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@ -784,7 +783,9 @@ bx_ne2k_c::page1_read(Bit32u offset, unsigned int io_len)
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void
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bx_ne2k_c::page1_write(Bit32u offset, Bit32u value, unsigned io_len)
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{
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BX_DEBUG(("page 1 w offset %04x", (unsigned) offset));
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BX_DEBUG(("page 1 write to register 0x%02x, len=%u, value=0x%04x", offset,
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io_len, value));
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switch (offset) {
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case 0x1: // PAR0-5
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case 0x2:
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@ -811,7 +812,7 @@ bx_ne2k_c::page1_write(Bit32u offset, Bit32u value, unsigned io_len)
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break;
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default:
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BX_PANIC(("page 1 w offset %04x out of range", (unsigned) offset));
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BX_PANIC(("page 1 write register 0x%02x out of range", offset));
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}
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}
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@ -823,10 +824,10 @@ bx_ne2k_c::page1_write(Bit32u offset, Bit32u value, unsigned io_len)
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Bit32u
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bx_ne2k_c::page2_read(Bit32u offset, unsigned int io_len)
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{
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BX_DEBUG(("page 2 read from port %04x, len=%u", (unsigned) offset, (unsigned) io_len));
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BX_DEBUG(("page 2 read from register 0x%02x, len=%u", offset, io_len));
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if (io_len > 1)
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BX_PANIC(("bad length! page 2 read from port %04x, len=%u", (unsigned) offset, (unsigned) io_len));
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BX_PANIC(("bad length! page 2 read from register 0x%02x, len=%u", offset, io_len));
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switch (offset) {
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case 0x1: // PSTART
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@ -861,7 +862,7 @@ bx_ne2k_c::page2_read(Bit32u offset, unsigned int io_len)
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case 0x9:
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case 0xa:
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case 0xb:
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BX_ERROR(("reserved read - page 2, 0x%02x", (unsigned) offset));
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BX_ERROR(("reserved read - page 2, register 0x%02x", offset));
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return (0xff);
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break;
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@ -901,7 +902,7 @@ bx_ne2k_c::page2_read(Bit32u offset, unsigned int io_len)
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break;
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default:
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BX_PANIC(("page 2 offset %04x out of range", (unsigned) offset));
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BX_PANIC(("page 2 register 0x%02x out of range", offset));
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}
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return (0);
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@ -913,8 +914,8 @@ bx_ne2k_c::page2_write(Bit32u offset, Bit32u value, unsigned io_len)
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// Maybe all writes here should be BX_PANIC()'d, since they
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// affect internal operation, but let them through for now
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// and print a warning.
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if (offset != 0)
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BX_ERROR(("page 2 write ?"));
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BX_ERROR(("page 2 write to register 0x%02x, len=%u, value=0x%04x", offset,
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io_len, value));
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switch (offset) {
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case 0x1: // CLDA0
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@ -934,7 +935,7 @@ bx_ne2k_c::page2_write(Bit32u offset, Bit32u value, unsigned io_len)
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break;
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case 0x4:
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BX_PANIC(("page 2 write to reserved offset 4"));
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BX_PANIC(("page 2 write to reserved register 0x04"));
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break;
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case 0x5: // Local Next-packet pointer
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@ -961,11 +962,11 @@ bx_ne2k_c::page2_write(Bit32u offset, Bit32u value, unsigned io_len)
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case 0xd:
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case 0xe:
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case 0xf:
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BX_PANIC(("page 2 write to reserved offset %0x", offset));
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BX_PANIC(("page 2 write to reserved register 0x%02x", offset));
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break;
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default:
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BX_PANIC(("page 2 write, illegal offset %0x", offset));
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BX_PANIC(("page 2 write, illegal register 0x%02x", offset));
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break;
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}
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}
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@ -1015,6 +1016,7 @@ void
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bx_ne2k_c::tx_timer(void)
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{
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BX_DEBUG(("tx_timer"));
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BX_NE2K_THIS s.CR.tx_packet = 0;
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BX_NE2K_THIS s.TSR.tx_ok = 1;
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// Generate an interrupt if not masked and not one in progress
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if (BX_NE2K_THIS s.IMR.tx_inte && !BX_NE2K_THIS s.ISR.pkt_tx) {
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@ -1315,7 +1317,7 @@ bx_ne2k_c::init(void)
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{
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char devname[16];
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BX_DEBUG(("Init $Id: ne2k.cc,v 1.78 2005-12-24 22:35:04 vruppert Exp $"));
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BX_DEBUG(("Init $Id: ne2k.cc,v 1.79 2006-01-28 20:18:18 vruppert Exp $"));
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// Read in values from config file
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memcpy(BX_NE2K_THIS s.physaddr, bx_options.ne2k.Omacaddr->getptr (), 6);
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