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- apply patch "patch.ifdef-paging-tlb"

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This commit is contained in:
Bryce Denney 2001-08-10 18:42:24 +00:00
parent 89b7a82ad4
commit 284178479b
5 changed files with 14 additions and 125 deletions
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5
bochs/cpu/cpu.cc
View File

@ -577,12 +577,15 @@ BX_CPU_C::prefetch(void)
BX_PANIC(("prefetch: EIP > CS.limit"));
}
#if BX_SUPPORT_PAGING
if (BX_CPU_THIS_PTR cr0.pg) {
// aligned block guaranteed to be all in one page, same A20 address
new_phy_addr = itranslate_linear(new_linear_addr, CPL==3);
new_phy_addr = A20ADDR(new_phy_addr);
}
else {
else
#endif // BX_SUPPORT_PAGING
{
new_phy_addr = A20ADDR(new_linear_addr);
}

6
bochs/cpu/init.cc
View File

@ -46,7 +46,7 @@ BX_CPU_C::BX_CPU_C()
void BX_CPU_C::init(BX_MEM_C *addrspace)
{
BX_DEBUG(( "Init $Id: init.cc,v 1.12 2001-06-27 20:27:48 fries Exp $"));
BX_DEBUG(( "Init $Id: init.cc,v 1.13 2001-08-10 18:42:24 bdenney Exp $"));
// BX_CPU_C constructor
BX_CPU_THIS_PTR set_INTR (0);
#if BX_SUPPORT_APIC
@ -555,7 +555,11 @@ BX_CPU_C::reset(unsigned source)
BX_CPU_THIS_PTR EXT = 0;
//BX_INTR = 0;
#if BX_SUPPORT_PAGING
#if BX_USE_TLB
TLB_init();
#endif // BX_USE_TLB
#endif // BX_SUPPORT_PAGING
BX_CPU_THIS_PTR bytesleft = 0;
BX_CPU_THIS_PTR fetch_ptr = NULL;

4
bochs/cpu/paging.cc
View File

@ -953,6 +953,8 @@ BX_CPU_C::access_linear(Bit32u laddress, unsigned length, unsigned pl,
BX_PANIC(("access_linear: paging not supported"));
}
void
BX_CPU_C::INVLPG(BxInstruction_t* i)
{}
#endif // BX_SUPPORT_PAGING

3
bochs/cpu/tasking.cc
View File

@ -211,7 +211,7 @@ BX_CPU_C::task_switch(bx_selector_t *tss_selector,
BX_PANIC(("task_switch(): TR not valid"));
exception(BX_TS_EXCEPTION, tss_selector->value & 0xfffc, 0);
}
#if BX_SUPPORT_PAGING
// Check that old TSS, new TSS, and all segment descriptors
// used in the task switch are paged in.
if (BX_CPU_THIS_PTR cr0.pg) {
@ -227,6 +227,7 @@ BX_CPU_C::task_switch(bx_selector_t *tss_selector,
// ??? fix RW above
// ??? touch old/new TSS descriptors here when necessary.
}
#endif // BX_SUPPORT_PAGING
// Need to fetch all new registers and temporarily store them.

121
bochs/patches/patch.ifdef-paging-tlb
View File

@ -1,121 +0,0 @@
----------------------------------------------------------------------
Patch name: patch.ifdef-paging-tlb
Author: Thomas Fitzsimmons <fitzsim@cygnus.com>
Date: Mon, 30 Jul 2001 16:31:41 -0400
RCS Id: $Id: patch.ifdef-paging-tlb,v 1.1 2001-08-10 18:31:53 bdenney Exp $
Detailed description:
When I set BX_SUPPORT_PAGING to 0 and BX_USE_TLB to 0, both in config.h.in,
I get compile errors. This patch contains #ifdef's that I think should fix
the problems.
Patch was created with:
diff -c
Apply patch to what version:
current cvs
Instructions:
To patch, go to main bochs directory.
Type "patch -p1 < THIS_PATCH_FILE".
----------------------------------------------------------------------
diff -c -r bochs-1.2.1/cpu/cpu.cc bochs-1.2.1-new/cpu/cpu.cc
*** bochs-1.2.1/cpu/cpu.cc Tue Jun 12 11:00:47 2001
--- bochs-1.2.1-new/cpu/cpu.cc Fri Jul 13 10:32:13 2001
***************
*** 575,586 ****
BX_PANIC(("prefetch: EIP > CS.limit\n"));
}
if (BX_CPU_THIS_PTR cr0.pg) {
// aligned block guaranteed to be all in one page, same A20 address
new_phy_addr = itranslate_linear(new_linear_addr, CPL==3);
new_phy_addr = A20ADDR(new_phy_addr);
}
! else {
new_phy_addr = A20ADDR(new_linear_addr);
}
--- 575,589 ----
BX_PANIC(("prefetch: EIP > CS.limit\n"));
}
+ #if BX_SUPPORT_PAGING
if (BX_CPU_THIS_PTR cr0.pg) {
// aligned block guaranteed to be all in one page, same A20 address
new_phy_addr = itranslate_linear(new_linear_addr, CPL==3);
new_phy_addr = A20ADDR(new_phy_addr);
}
! else
! #endif // BX_SUPPORT_PAGING
! {
new_phy_addr = A20ADDR(new_linear_addr);
}
diff -c -r bochs-1.2.1/cpu/init.cc bochs-1.2.1-new/cpu/init.cc
*** bochs-1.2.1/cpu/init.cc Tue Jun 12 11:03:20 2001
--- bochs-1.2.1-new/cpu/init.cc Fri Jul 13 10:32:13 2001
***************
*** 554,560 ****
--- 554,564 ----
BX_CPU_THIS_PTR EXT = 0;
//BX_INTR = 0;
+ #if BX_SUPPORT_PAGING
+ #if BX_USE_TLB
TLB_init();
+ #endif // BX_USE_TLB
+ #endif // BX_SUPPORT_PAGING
BX_CPU_THIS_PTR bytesleft = 0;
BX_CPU_THIS_PTR fetch_ptr = NULL;
diff -c -r bochs-1.2.1/cpu/paging.cc bochs-1.2.1-new/cpu/paging.cc
*** bochs-1.2.1/cpu/paging.cc Thu May 24 14:46:34 2001
--- bochs-1.2.1-new/cpu/paging.cc Fri Jul 13 10:32:15 2001
***************
*** 953,958 ****
BX_PANIC(("access_linear: paging not supported\n"));
}
!
#endif // BX_SUPPORT_PAGING
--- 953,960 ----
BX_PANIC(("access_linear: paging not supported\n"));
}
! void
! BX_CPU_C::INVLPG(BxInstruction_t* i)
! {}
#endif // BX_SUPPORT_PAGING
Only in bochs-1.2.1-new/cpu: paging.cc~
diff -c -r bochs-1.2.1/cpu/tasking.cc bochs-1.2.1-new/cpu/tasking.cc
*** bochs-1.2.1/cpu/tasking.cc Thu May 24 14:46:34 2001
--- bochs-1.2.1-new/cpu/tasking.cc Fri Jul 13 10:32:14 2001
***************
*** 211,217 ****
BX_PANIC(("task_switch(): TR not valid\n"));
exception(BX_TS_EXCEPTION, tss_selector->value & 0xfffc, 0);
}
!
// Check that old TSS, new TSS, and all segment descriptors
// used in the task switch are paged in.
if (BX_CPU_THIS_PTR cr0.pg) {
--- 211,217 ----
BX_PANIC(("task_switch(): TR not valid\n"));
exception(BX_TS_EXCEPTION, tss_selector->value & 0xfffc, 0);
}
! #if BX_SUPPORT_PAGING
// Check that old TSS, new TSS, and all segment descriptors
// used in the task switch are paged in.
if (BX_CPU_THIS_PTR cr0.pg) {
***************
*** 227,232 ****
--- 227,233 ----
// ??? fix RW above
// ??? touch old/new TSS descriptors here when necessary.
}
+ #endif // BX_SUPPORT_PAGING
// Need to fetch all new registers and temporarily store them.