From 283f9ae5d25b7c92a78e23d774163c791e642592 Mon Sep 17 00:00:00 2001 From: Stanislav Shwartsman Date: Tue, 14 Sep 2004 20:19:54 +0000 Subject: [PATCH] Simplify cpu.h Speedup FYL2X and FYL2XP1 instructions --- bochs/cpu/cpu.h | 76 ++++++++++++++++-------------------------- bochs/cpu/exception.cc | 7 ++-- bochs/fpu/fyl2x.cc | 10 +++--- 3 files changed, 38 insertions(+), 55 deletions(-) diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h index e675550b9..90a33db8b 100644 --- a/bochs/cpu/cpu.h +++ b/bochs/cpu/cpu.h @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: cpu.h,v 1.176 2004-09-13 20:48:10 sshwarts Exp $ +// $Id: cpu.h,v 1.177 2004-09-14 20:19:54 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -124,7 +124,6 @@ // access to 16 bit instruction pointer #define IP (* (Bit16u *) (((Bit8u *) &BX_CPU_THIS_PTR dword.eip) + BX_REG16_OFFSET)) - // accesss to 32 bit general registers #define EAX BX_CPU_THIS_PTR gen_reg[0].dword.erx #define ECX BX_CPU_THIS_PTR gen_reg[1].dword.erx @@ -244,9 +243,7 @@ #endif -#ifndef CPL #define CPL (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl) -#endif #if BX_SMP_PROCESSORS==1 #define BX_CPU_ID 0 @@ -1002,7 +999,6 @@ typedef void (BX_CPU_C::*BxExecutePtr_tR)(bxInstruction_c *) BX_CPP_AttrRegparmN // ========== iCache ============================================= - #if BX_SUPPORT_ICACHE #define BxICacheEntries (32 * 1024) // Must be a power of 2. @@ -1186,11 +1182,16 @@ typedef struct { class BX_MEM_C; -#if BX_SUPPORT_FPU -#include "cpu/i387.h" +#if BX_SUPPORT_X86_64 +# define BX_GENERAL_REGISTERS 16 +#else +# define BX_GENERAL_REGISTERS 8 #endif +#if BX_SUPPORT_FPU +#include "cpu/i387.h" #include "cpu/xmm.h" +#endif class BOCHSAPI BX_CPU_C : public logfunctions { @@ -1209,39 +1210,36 @@ public: // for now... // esi: source index // edi: destination index // esp: stack pointer + bx_gen_reg_t gen_reg[BX_GENERAL_REGISTERS]; + + // instruction pointer #if BX_SUPPORT_X86_64 - bx_gen_reg_t gen_reg[16]; - -union { -#ifdef BX_BIG_ENDIAN - struct { - Bit32u rip_upper; - Bit32u eip; - } dword; -#else - struct { - Bit32u eip; - Bit32u rip_upper; - } dword; -#endif - Bit64u rip; - }; - -#else - - bx_gen_reg_t gen_reg[8]; - union { - Bit32u eip; // instruction pointer +#ifdef BX_BIG_ENDIAN + struct { + Bit32u rip_upper; + Bit32u eip; + } dword; +#else + struct { + Bit32u eip; + Bit32u rip_upper; + } dword; +#endif + Bit64u rip; + }; +#else + union { + Bit32u eip; // instruction pointer } dword; #endif -#if BX_CPU_LEVEL > 0 // so that we can back up when handling faults, exceptions, etc. // we need to store the value of the instruction pointer, before // each fetch/execute cycle. bx_address prev_eip; -#endif + bx_address prev_esp; + // status and control flags register set Bit32u lf_flags_status; bx_flags_reg_t eflags; @@ -1249,8 +1247,6 @@ union { bx_lf_flags_entry oszapc; bx_lf_flags_entry oszap; - bx_address prev_esp; - #define BX_INHIBIT_INTERRUPTS 0x01 #define BX_INHIBIT_DEBUG 0x02 // What events to inhibit at any given time. Certain instructions @@ -1354,8 +1350,6 @@ union { jmp_buf jmp_buf_env; Bit8u curr_exception[2]; - static const bx_bool is_exception_OK[3][3]; - bx_segment_reg_t save_cs; bx_segment_reg_t save_ss; Bit32u save_eip; @@ -1450,13 +1444,6 @@ union { // for a direct write access. } address_xlation; -#if BX_SUPPORT_X86_64 - // data upper 32 bits - not used any longer - //Bit32s daddr_upper; // upper bits must be canonical (-virtmax --> + virtmax) - // instruction upper 32 bits - not used any longer - //Bit32s iaddr_upper; // upper bits must be canonical (-virtmax --> + virtmax) -#endif - #if BX_EXTERNAL_DEBUGGER virtual void ask (int level, const char *prefix, const char *fmt, va_list ap); #endif @@ -1594,19 +1581,14 @@ union { BX_SMF void MOV_EEbGb(bxInstruction_c *); BX_SMF void MOV_EGbGb(bxInstruction_c *); - BX_SMF void MOV_EEdGd(bxInstruction_c *); BX_SMF void MOV_EGdGd(bxInstruction_c *); - BX_SMF void MOV_EEwGw(bxInstruction_c *); BX_SMF void MOV_EGwGw(bxInstruction_c *); - BX_SMF void MOV_GbEEb(bxInstruction_c *); BX_SMF void MOV_GbEGb(bxInstruction_c *); - BX_SMF void MOV_GdEEd(bxInstruction_c *); BX_SMF void MOV_GdEGd(bxInstruction_c *); - BX_SMF void MOV_GwEEw(bxInstruction_c *); BX_SMF void MOV_GwEGw(bxInstruction_c *); diff --git a/bochs/cpu/exception.cc b/bochs/cpu/exception.cc index 5a8bf04eb..8d6948cb4 100644 --- a/bochs/cpu/exception.cc +++ b/bochs/cpu/exception.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: exception.cc,v 1.41 2004-08-28 08:41:46 sshwarts Exp $ +// $Id: exception.cc,v 1.42 2004-09-14 20:19:54 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -41,12 +41,11 @@ #define BX_ET_DOUBLE_FAULT 10 - -const bx_bool BX_CPU_C::is_exception_OK[3][3] = { +static const bx_bool is_exception_OK[3][3] = { { 1, 1, 1 }, /* 1st exception is BENIGN */ { 1, 0, 1 }, /* 1st exception is CONTRIBUTORY */ { 1, 0, 0 } /* 1st exception is PAGE_FAULT */ - }; +}; void diff --git a/bochs/fpu/fyl2x.cc b/bochs/fpu/fyl2x.cc index e4e846a5a..5ce9e047d 100755 --- a/bochs/fpu/fyl2x.cc +++ b/bochs/fpu/fyl2x.cc @@ -214,7 +214,9 @@ invalid: /* using float128 for approximation */ /* ******************************** */ - float128 x = normalizeRoundAndPackFloat128(0, aExp+0x3FEF, aSig, 0, status); + Bit64u zSig0, zSig1; + shift128Right(aSig<<1, 0, 16, &zSig0, &zSig1); + float128 x = packFloat128(0, aExp+0x3FFF, zSig0, zSig1); x = poly_l2(x, status); x = float128_add(x, floatx80_to_float128(int32_to_floatx80(ExpDiff), status), status); return floatx80_mul(b, x, status); @@ -247,8 +249,8 @@ invalid: floatx80 fyl2xp1(floatx80 a, floatx80 b, float_status_t &status) { - Bit64u aSig, bSig; Bit32s aExp, bExp; + Bit64u aSig, bSig, zSig0, zSig1, zSig2; int aSign, bSign; // handle unsupported extended double-precision floating encodings @@ -321,7 +323,6 @@ invalid: if (aExp < EXP_BIAS-70) { // first order approximation, return (a*b)/ln(2) - Bit64u zSig0, zSig1, zSig2; Bit32s zExp = aExp + FLOAT_LN2INV_EXP - 0x3FFE; mul128By64To192(FLOAT_LN2INV_HI, FLOAT_LN2INV_LO, aSig, &zSig0, &zSig1, &zSig2); @@ -345,7 +346,8 @@ invalid: /* using float128 for approximation */ /* ******************************** */ - float128 x = normalizeRoundAndPackFloat128(aSign, aExp-0x10, aSig, 0, status); + shift128Right(aSig<<1, 0, 16, &zSig0, &zSig1); + float128 x = packFloat128(aSign, aExp, zSig0, zSig1); x = poly_l2p1(x, status); return floatx80_mul(b, x, status); }