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HandlersChaining Optimization: mark IN/OUT instructions as TraceEnd, they could have significant side effects like raising interrupts which have to be handled 

resolves issue #207
This commit is contained in:
Shwartsman 2024-01-05 08:44:40 +02:00
parent 1f8eb7b608
commit 27d48ecb94
1 changed files with 18 additions and 18 deletions
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36
bochs/cpu/decoder/ia_opcodes.def
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@ -335,19 +335,19 @@ bx_define_opcode(BX_IA_IMUL_GwEw, "imul", "imulw", &BX_CPU_C::LOAD_Ew, &BX_CPU_C
bx_define_opcode(BX_IA_IMUL_GwEwIw, "imul", "imulw", &BX_CPU_C::LOAD_Ew, &BX_CPU_C::IMUL_GwEwIwR, 0, OP_Gw, OP_Ew, OP_Iw, OP_NONE, 0) bx_define_opcode(BX_IA_IMUL_GwEwIw, "imul", "imulw", &BX_CPU_C::LOAD_Ew, &BX_CPU_C::IMUL_GwEwIwR, 0, OP_Gw, OP_Ew, OP_Iw, OP_NONE, 0)
bx_define_opcode(BX_IA_IMUL_GwEwsIb, "imul", "imulw", &BX_CPU_C::LOAD_Ew, &BX_CPU_C::IMUL_GwEwIwR, 0, OP_Gw, OP_Ew, OP_sIbw, OP_NONE, 0) bx_define_opcode(BX_IA_IMUL_GwEwsIb, "imul", "imulw", &BX_CPU_C::LOAD_Ew, &BX_CPU_C::IMUL_GwEwIwR, 0, OP_Gw, OP_Ew, OP_sIbw, OP_NONE, 0)
bx_define_opcode(BX_IA_IN_ALDX, "in", "inb", NULL, &BX_CPU_C::IN_ALDX, 0, OP_ALReg, OP_DXReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_IN_ALDX, "in", "inb", NULL, &BX_CPU_C::IN_ALDX, 0, OP_ALReg, OP_DXReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_IN_ALIb, "in", "inb", NULL, &BX_CPU_C::IN_ALIb, 0, OP_ALReg, OP_Ib, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_IN_ALIb, "in", "inb", NULL, &BX_CPU_C::IN_ALIb, 0, OP_ALReg, OP_Ib, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_IN_AXDX, "in", "inw", NULL, &BX_CPU_C::IN_AXDX, 0, OP_AXReg, OP_DXReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_IN_AXDX, "in", "inw", NULL, &BX_CPU_C::IN_AXDX, 0, OP_AXReg, OP_DXReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_IN_AXIb, "in", "inw", NULL, &BX_CPU_C::IN_AXIb, 0, OP_AXReg, OP_Ib, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_IN_AXIb, "in", "inw", NULL, &BX_CPU_C::IN_AXIb, 0, OP_AXReg, OP_Ib, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_IN_EAXDX, "in", "inl", NULL, &BX_CPU_C::IN_EAXDX, 0, OP_EAXReg, OP_DXReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_IN_EAXDX, "in", "inl", NULL, &BX_CPU_C::IN_EAXDX, 0, OP_EAXReg, OP_DXReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_IN_EAXIb, "in", "inl", NULL, &BX_CPU_C::IN_EAXIb, 0, OP_EAXReg, OP_Ib, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_IN_EAXIb, "in", "inl", NULL, &BX_CPU_C::IN_EAXIb, 0, OP_EAXReg, OP_Ib, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_OUT_DXAL, "out", "outb", NULL, &BX_CPU_C::OUT_DXAL, 0, OP_DXReg, OP_ALReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_OUT_DXAL, "out", "outb", NULL, &BX_CPU_C::OUT_DXAL, 0, OP_DXReg, OP_ALReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_OUT_DXAX, "out", "outw", NULL, &BX_CPU_C::OUT_DXAX, 0, OP_DXReg, OP_AXReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_OUT_DXAX, "out", "outw", NULL, &BX_CPU_C::OUT_DXAX, 0, OP_DXReg, OP_AXReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_OUT_DXEAX, "out", "outl", NULL, &BX_CPU_C::OUT_DXEAX, 0, OP_DXReg, OP_EAXReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_OUT_DXEAX, "out", "outl", NULL, &BX_CPU_C::OUT_DXEAX, 0, OP_DXReg, OP_EAXReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_OUT_IbAL, "out", "outb", NULL, &BX_CPU_C::OUT_IbAL, 0, OP_Ib, OP_ALReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_OUT_IbAL, "out", "outb", NULL, &BX_CPU_C::OUT_IbAL, 0, OP_Ib, OP_ALReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_OUT_IbAX, "out", "outw", NULL, &BX_CPU_C::OUT_IbAX, 0, OP_Ib, OP_AXReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_OUT_IbAX, "out", "outw", NULL, &BX_CPU_C::OUT_IbAX, 0, OP_Ib, OP_AXReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_OUT_IbEAX, "out", "outl", NULL, &BX_CPU_C::OUT_IbEAX, 0, OP_Ib, OP_EAXReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_OUT_IbEAX, "out", "outl", NULL, &BX_CPU_C::OUT_IbEAX, 0, OP_Ib, OP_EAXReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_INT_Ib, "int", "int", NULL, &BX_CPU_C::INT_Ib, 0, OP_Ib, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END) bx_define_opcode(BX_IA_INT_Ib, "int", "int", NULL, &BX_CPU_C::INT_Ib, 0, OP_Ib, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_INT1, "int1", "int1", NULL, &BX_CPU_C::INT1, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END) bx_define_opcode(BX_IA_INT1, "int1", "int1", NULL, &BX_CPU_C::INT1, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
@ -545,18 +545,18 @@ bx_define_opcode(BX_IA_PUSHF_Fd, "pushf", "pushfl", NULL, &BX_CPU_C::PUSHF_Fd, 0
bx_define_opcode(BX_IA_REP_CMPSB_XbYb, "cmpsb", "cmpsb", NULL, &BX_CPU_C::REP_CMPSB_XbYb, 0, OP_Xb, OP_Yb, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_CMPSB_XbYb, "cmpsb", "cmpsb", NULL, &BX_CPU_C::REP_CMPSB_XbYb, 0, OP_Xb, OP_Yb, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_CMPSD_XdYd, "cmpsd", "cmpsl", NULL, &BX_CPU_C::REP_CMPSD_XdYd, 0, OP_Xd, OP_Yd, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_CMPSD_XdYd, "cmpsd", "cmpsl", NULL, &BX_CPU_C::REP_CMPSD_XdYd, 0, OP_Xd, OP_Yd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_CMPSW_XwYw, "cmpsw", "cmpsw", NULL, &BX_CPU_C::REP_CMPSW_XwYw, 0, OP_Xw, OP_Yw, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_CMPSW_XwYw, "cmpsw", "cmpsw", NULL, &BX_CPU_C::REP_CMPSW_XwYw, 0, OP_Xw, OP_Yw, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_INSB_YbDX, "insb", "insb", NULL, &BX_CPU_C::REP_INSB_YbDX, 0, OP_Yb, OP_DXReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_INSB_YbDX, "insb", "insb", NULL, &BX_CPU_C::REP_INSB_YbDX, 0, OP_Yb, OP_DXReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_REP_INSD_YdDX, "insd", "insl", NULL, &BX_CPU_C::REP_INSD_YdDX, 0, OP_Yd, OP_DXReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_INSD_YdDX, "insd", "insl", NULL, &BX_CPU_C::REP_INSD_YdDX, 0, OP_Yd, OP_DXReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_REP_INSW_YwDX, "insw", "insw", NULL, &BX_CPU_C::REP_INSW_YwDX, 0, OP_Yw, OP_DXReg, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_INSW_YwDX, "insw", "insw", NULL, &BX_CPU_C::REP_INSW_YwDX, 0, OP_Yw, OP_DXReg, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_REP_LODSB_ALXb, "lodsb", "lodsb", NULL, &BX_CPU_C::REP_LODSB_ALXb, 0, OP_ALReg, OP_Xb, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_LODSB_ALXb, "lodsb", "lodsb", NULL, &BX_CPU_C::REP_LODSB_ALXb, 0, OP_ALReg, OP_Xb, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_LODSD_EAXXd, "lodsd", "lodsl", NULL, &BX_CPU_C::REP_LODSD_EAXXd, 0, OP_EAXReg, OP_Xd, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_LODSD_EAXXd, "lodsd", "lodsl", NULL, &BX_CPU_C::REP_LODSD_EAXXd, 0, OP_EAXReg, OP_Xd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_LODSW_AXXw, "lodsw", "lodsw", NULL, &BX_CPU_C::REP_LODSW_AXXw, 0, OP_AXReg, OP_Xw, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_LODSW_AXXw, "lodsw", "lodsw", NULL, &BX_CPU_C::REP_LODSW_AXXw, 0, OP_AXReg, OP_Xw, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_MOVSB_YbXb, "movsb", "movsb", NULL, &BX_CPU_C::REP_MOVSB_YbXb, 0, OP_Yb, OP_Xb, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_MOVSB_YbXb, "movsb", "movsb", NULL, &BX_CPU_C::REP_MOVSB_YbXb, 0, OP_Yb, OP_Xb, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_MOVSD_YdXd, "movsd", "movsl", NULL, &BX_CPU_C::REP_MOVSD_YdXd, 0, OP_Yd, OP_Xd, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_MOVSD_YdXd, "movsd", "movsl", NULL, &BX_CPU_C::REP_MOVSD_YdXd, 0, OP_Yd, OP_Xd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_MOVSW_YwXw, "movsw", "movsw", NULL, &BX_CPU_C::REP_MOVSW_YwXw, 0, OP_Yw, OP_Xw, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_MOVSW_YwXw, "movsw", "movsw", NULL, &BX_CPU_C::REP_MOVSW_YwXw, 0, OP_Yw, OP_Xw, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_OUTSB_DXXb, "outsb", "outsb", NULL, &BX_CPU_C::REP_OUTSB_DXXb, 0, OP_DXReg, OP_Xb, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_OUTSB_DXXb, "outsb", "outsb", NULL, &BX_CPU_C::REP_OUTSB_DXXb, 0, OP_DXReg, OP_Xb, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_REP_OUTSD_DXXd, "outsd", "outsl", NULL, &BX_CPU_C::REP_OUTSD_DXXd, 0, OP_DXReg, OP_Xd, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_OUTSD_DXXd, "outsd", "outsl", NULL, &BX_CPU_C::REP_OUTSD_DXXd, 0, OP_DXReg, OP_Xd, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_REP_OUTSW_DXXw, "outsw", "outsw", NULL, &BX_CPU_C::REP_OUTSW_DXXw, 0, OP_DXReg, OP_Xw, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_OUTSW_DXXw, "outsw", "outsw", NULL, &BX_CPU_C::REP_OUTSW_DXXw, 0, OP_DXReg, OP_Xw, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_REP_SCASB_ALYb, "scasb", "scasb", NULL, &BX_CPU_C::REP_SCASB_ALYb, 0, OP_ALReg, OP_Yb, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_SCASB_ALYb, "scasb", "scasb", NULL, &BX_CPU_C::REP_SCASB_ALYb, 0, OP_ALReg, OP_Yb, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_SCASD_EAXYd, "scasd", "scasl", NULL, &BX_CPU_C::REP_SCASD_EAXYd, 0, OP_EAXReg, OP_Yd, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_SCASD_EAXYd, "scasd", "scasl", NULL, &BX_CPU_C::REP_SCASD_EAXYd, 0, OP_EAXReg, OP_Yd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_SCASW_AXYw, "scasw", "scasw", NULL, &BX_CPU_C::REP_SCASW_AXYw, 0, OP_AXReg, OP_Yw, OP_NONE, OP_NONE, 0) bx_define_opcode(BX_IA_REP_SCASW_AXYw, "scasw", "scasw", NULL, &BX_CPU_C::REP_SCASW_AXYw, 0, OP_AXReg, OP_Yw, OP_NONE, OP_NONE, 0)