mirror of https://github.com/bochs-emu/Bochs
implemented SM4 instructions
This commit is contained in:
Stanislav Shwartsman
parent
721745921c
commit
25a90ac493
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@ -41,105 +41,106 @@ BX_INCDIRS = -I.. -I$(srcdir)/.. -I../@INSTRUMENT_DIR@ -I$(srcdir)/../@INSTRUMEN
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# Objects which are synced between the cpu and cpu64 code and
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# are used for either compile.
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OBJS = \
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init.o \
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cpu.o \
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event.o \
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icache.o \
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decoder/fetchdecode32.o \
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access.o \
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access2.o \
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shift16.o \
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logical16.o \
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ctrl_xfer32.o \
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ctrl_xfer16.o \
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mmx.o \
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3dnow.o \
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fpu_emu.o \
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sse.o \
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sse_move.o \
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sse_pfp.o \
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sse_rcp.o \
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sse_string.o \
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xsave.o \
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aes.o \
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gf2.o \
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sha.o \
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sm3.o \
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svm.o \
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vmx.o \
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vmcs.o \
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vmexit.o \
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vmfunc.o \
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soft_int.o \
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apic.o \
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bcd.o \
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mult16.o \
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tasking.o \
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shift32.o \
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shift8.o \
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arith8.o \
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stack.o \
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stack16.o \
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protect_ctrl.o \
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mult8.o \
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load.o \
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data_xfer8.o \
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vm8086.o \
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logical8.o \
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logical32.o \
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arith16.o \
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segment_ctrl.o \
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data_xfer16.o \
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data_xfer32.o \
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exception.o \
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cpuid.o \
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generic_cpuid.o \
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proc_ctrl.o \
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mwait.o \
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crregs.o \
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cet.o \
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msr.o \
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smm.o \
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flag_ctrl_pro.o \
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stack32.o \
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debugstuff.o \
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flag_ctrl.o \
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mult32.o \
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arith32.o \
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jmp_far.o \
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call_far.o \
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ret_far.o \
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iret.o \
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ctrl_xfer_pro.o \
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segment_ctrl_pro.o \
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io.o \
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crc32.o \
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bit.o \
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bit16.o \
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bit32.o \
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bmi32.o \
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cmpccxadd32.o \
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string.o \
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faststring.o \
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paging.o \
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rdrand.o \
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wide_int.o \
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decoder/disasm.o
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init.o \
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cpu.o \
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event.o \
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icache.o \
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decoder/fetchdecode32.o \
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access.o \
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access2.o \
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shift16.o \
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logical16.o \
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ctrl_xfer32.o \
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ctrl_xfer16.o \
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mmx.o \
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3dnow.o \
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fpu_emu.o \
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sse.o \
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sse_move.o \
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sse_pfp.o \
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sse_rcp.o \
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sse_string.o \
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xsave.o \
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aes.o \
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gf2.o \
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sha.o \
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sm3.o \
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sm4.o \
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svm.o \
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vmx.o \
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vmcs.o \
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vmexit.o \
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vmfunc.o \
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soft_int.o \
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apic.o \
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bcd.o \
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mult16.o \
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tasking.o \
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shift32.o \
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shift8.o \
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arith8.o \
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stack.o \
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stack16.o \
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protect_ctrl.o \
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mult8.o \
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load.o \
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data_xfer8.o \
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vm8086.o \
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logical8.o \
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logical32.o \
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arith16.o \
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segment_ctrl.o \
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data_xfer16.o \
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data_xfer32.o \
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exception.o \
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cpuid.o \
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generic_cpuid.o \
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proc_ctrl.o \
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mwait.o \
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crregs.o \
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cet.o \
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msr.o \
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smm.o \
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flag_ctrl_pro.o \
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stack32.o \
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debugstuff.o \
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flag_ctrl.o \
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mult32.o \
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arith32.o \
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jmp_far.o \
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call_far.o \
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ret_far.o \
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iret.o \
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ctrl_xfer_pro.o \
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segment_ctrl_pro.o \
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io.o \
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crc32.o \
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bit.o \
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bit16.o \
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bit32.o \
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bmi32.o \
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cmpccxadd32.o \
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string.o \
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faststring.o \
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paging.o \
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rdrand.o \
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wide_int.o \
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decoder/disasm.o
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# Objects which are only used for x86-64 code
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OBJS64 = \
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arith64.o \
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ctrl_xfer64.o \
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data_xfer64.o \
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decoder/fetchdecode64.o \
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logical64.o \
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mult64.o \
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shift64.o \
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bit64.o \
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stack64.o \
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bmi64.o \
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cmpccxadd64.o \
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vapic.o
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arith64.o \
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ctrl_xfer64.o \
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data_xfer64.o \
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decoder/fetchdecode64.o \
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logical64.o \
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mult64.o \
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shift64.o \
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bit64.o \
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stack64.o \
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bmi64.o \
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cmpccxadd64.o \
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vapic.o
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BX_INCLUDES = ../bochs.h ../config.h
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@ -147,25 +148,25 @@ BX_INCLUDES = ../bochs.h ../config.h
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all: libcpu.a
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.@CPP_SUFFIX@.o:
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$(CXX) @DASH@c $(BX_INCDIRS) $(CPPFLAGS) $(CXXFLAGS) @CXXFP@$< @OFP@$@
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$(CXX) @DASH@c $(BX_INCDIRS) $(CPPFLAGS) $(CXXFLAGS) @CXXFP@$< @OFP@$@
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libcpu.a: $(OBJS) @OBJS64@
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@RMCOMMAND@ libcpu.a
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@MAKELIB@ $(OBJS) @OBJS64@
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$(RANLIB) libcpu.a
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@RMCOMMAND@ libcpu.a
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@MAKELIB@ $(OBJS) @OBJS64@
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$(RANLIB) libcpu.a
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$(OBJS): $(BX_INCLUDES)
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$(OBJS64): $(BX_INCLUDES)
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clean:
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@RMCOMMAND@ *.o
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@RMCOMMAND@ *.a
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@RMCOMMAND@ decoder@SLASH@*.o
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@RMCOMMAND@ *.o
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@RMCOMMAND@ *.a
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@RMCOMMAND@ decoder@SLASH@*.o
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dist-clean: clean
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@RMCOMMAND@ Makefile
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@RMCOMMAND@ Makefile
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###########################################
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# dependencies generated by
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@ -631,7 +632,13 @@ sm3.o: sm3.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
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../logio.h ../instrument/stubs/instrument.h cpu.h \
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decoder/decoder.h i387.h fpu/softfloat.h fpu/tag_w.h fpu/status_w.h \
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fpu/control_w.h crregs.h descriptor.h decoder/instr.h lazy_flags.h tlb.h \
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icache.h apic.h xmm.h vmx.h svm.h cpuid.h stack.h access.h
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icache.h apic.h xmm.h vmx.h svm.h cpuid.h stack.h access.h scalar_arith.h
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sm4.o: sm4.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
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../config.h ../osdep.h ../cpu/decoder/decoder.h ../gui/paramtree.h \
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../logio.h ../instrument/stubs/instrument.h cpu.h \
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decoder/decoder.h i387.h fpu/softfloat.h fpu/tag_w.h fpu/status_w.h \
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fpu/control_w.h crregs.h descriptor.h decoder/instr.h lazy_flags.h tlb.h \
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icache.h apic.h xmm.h vmx.h svm.h cpuid.h stack.h access.h scalar_arith.h
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shift16.o: shift16.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
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../bx_debug/debug.h ../config.h ../osdep.h ../cpu/decoder/decoder.h \
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../gui/paramtree.h ../logio.h \
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@ -639,7 +646,7 @@ shift16.o: shift16.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
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fpu/softfloat.h fpu/tag_w.h fpu/status_w.h fpu/control_w.h crregs.h \
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descriptor.h decoder/instr.h lazy_flags.h tlb.h icache.h apic.h xmm.h \
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vmx.h svm.h cpuid.h stack.h access.h decoder/ia_opcodes.h \
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decoder/ia_opcodes.def
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scalar_arith.h decoder/ia_opcodes.def
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shift32.o: shift32.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
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../bx_debug/debug.h ../config.h ../osdep.h ../cpu/decoder/decoder.h \
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../gui/paramtree.h ../logio.h \
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@ -647,7 +654,7 @@ shift32.o: shift32.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
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fpu/softfloat.h fpu/tag_w.h fpu/status_w.h fpu/control_w.h crregs.h \
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descriptor.h decoder/instr.h lazy_flags.h tlb.h icache.h apic.h xmm.h \
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vmx.h svm.h cpuid.h stack.h access.h decoder/ia_opcodes.h \
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decoder/ia_opcodes.def
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scalar_arith.h decoder/ia_opcodes.def
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shift64.o: shift64.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
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../bx_debug/debug.h ../config.h ../osdep.h ../cpu/decoder/decoder.h \
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../gui/paramtree.h ../logio.h \
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@ -655,14 +662,14 @@ shift64.o: shift64.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
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fpu/softfloat.h fpu/tag_w.h fpu/status_w.h fpu/control_w.h crregs.h \
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descriptor.h decoder/instr.h lazy_flags.h tlb.h icache.h apic.h xmm.h \
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vmx.h svm.h cpuid.h stack.h access.h decoder/ia_opcodes.h \
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decoder/ia_opcodes.def
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scalar_arith.h decoder/ia_opcodes.def
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shift8.o: shift8.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
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../config.h ../osdep.h ../cpu/decoder/decoder.h ../gui/paramtree.h \
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../logio.h ../instrument/stubs/instrument.h cpu.h \
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decoder/decoder.h i387.h fpu/softfloat.h fpu/tag_w.h fpu/status_w.h \
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fpu/control_w.h crregs.h descriptor.h decoder/instr.h lazy_flags.h tlb.h \
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icache.h apic.h xmm.h vmx.h svm.h cpuid.h stack.h access.h \
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decoder/ia_opcodes.h decoder/ia_opcodes.def
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scalar_arith.h decoder/ia_opcodes.h decoder/ia_opcodes.def
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smm.o: smm.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
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../config.h ../osdep.h ../cpu/decoder/decoder.h ../gui/paramtree.h \
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../logio.h ../instrument/stubs/instrument.h cpu.h \
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@ -1174,7 +1174,9 @@ static const Bit64u BxOpcodeGroup_VEX_0F38CF[] = { last_opcode(ATTR_SSE_PREFIX_6
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static const Bit64u BxOpcodeGroup_VEX_0F38DA[] = {
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form_opcode(ATTR_SSE_NO_PREFIX | ATTR_VL128 | ATTR_VEX_W0, BX_IA_VSM3MSG1_VdqHdqWdq),
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last_opcode(ATTR_SSE_PREFIX_66 | ATTR_VL128 | ATTR_VEX_W0, BX_IA_VSM3MSG2_VdqHdqWdq)
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form_opcode(ATTR_SSE_PREFIX_66 | ATTR_VL128 | ATTR_VEX_W0, BX_IA_VSM3MSG2_VdqHdqWdq),
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form_opcode(ATTR_SSE_PREFIX_F3 | ATTR_VEX_W0, BX_IA_VSM4KEY4_VdqHdqWdq),
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last_opcode(ATTR_SSE_PREFIX_F2 | ATTR_VEX_W0, BX_IA_VSM4RNDS4_VdqHdqWdq)
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};
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static const Bit64u BxOpcodeGroup_VEX_0F38DB[] = { last_opcode(ATTR_SSE_PREFIX_66 | ATTR_VL128, BX_IA_V128_VAESIMC_VdqWdq) };
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@ -2237,6 +2237,10 @@ bx_define_opcode(BX_IA_VSM3MSG1_VdqHdqWdq, "vsm3msg1", "vsm3msg1", &BX_CPU_C::LO
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bx_define_opcode(BX_IA_VSM3MSG2_VdqHdqWdq, "vsm3msg2", "vsm3msg2", &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::VSM3MSG2_VdqHdqWdqR, BX_ISA_SM3, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VSM3RNDS2_VdqHdqWdqIb, "vsm3rnds2", "vsm3rnds2", &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::VSM3RNDS2_VdqHdqWdqIbR, BX_ISA_SM3, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_AVX)
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// SM4 instructions
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bx_define_opcode(BX_IA_VSM4KEY4_VdqHdqWdq, "vsm4key4", "vsm4key4", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSM4KEY4_VdqHdqWdqR, BX_ISA_SM4, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VSM4RNDS4_VdqHdqWdq, "vsm4rnds4", "vsm4rnds4", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSM4RNDS4_VdqHdqWdqR, BX_ISA_SM4, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVD_VdqEd, "vmovd", "vmovd", &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVD_VdqEdR, BX_ISA_AVX, OP_Vdq, OP_Ed, OP_NONE, OP_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVQ_VdqEq, "vmovq", "vmovq", &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VdqEqR, BX_ISA_AVX, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVD_EdVd, "vmovd", "vmovd", &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, BX_ISA_AVX, OP_Ed, OP_Vd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
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@ -0,0 +1,162 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2023 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_AVX
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#include "scalar_arith.h"
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// Additional details can be found at: https://tools.ietf.org/html/draft-ribose-cfrg-sm4-10
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static const Bit8u sm4_sbox[256] = {
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0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05,
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0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
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0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
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0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6,
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0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8,
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0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
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0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87,
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0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E,
|
||||
0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
|
||||
0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3,
|
||||
0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F,
|
||||
0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
|
||||
0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,
|
||||
0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0,
|
||||
0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
|
||||
0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48
|
||||
};
|
||||
|
||||
BX_CPP_INLINE Bit32u lower_t(Bit32u val32)
|
||||
{
|
||||
// do sbox per byte
|
||||
Bit32u tmp0 = sm4_sbox[val32 & 0xff];
|
||||
Bit32u tmp1 = sm4_sbox[(val32 >> 8) & 0xff];
|
||||
Bit32u tmp2 = sm4_sbox[(val32 >> 16) & 0xff];
|
||||
Bit32u tmp3 = sm4_sbox[(val32 >> 24) & 0xff];
|
||||
// form 32-bit value back
|
||||
return tmp0 | (tmp1 << 8) | (tmp2 << 16) | (tmp3 << 24);
|
||||
}
|
||||
|
||||
BX_CPP_INLINE Bit32u L_KEY(Bit32u val32)
|
||||
{
|
||||
return val32 ^ rol32(val32, 13) ^ rol32(val32, 23);
|
||||
}
|
||||
|
||||
BX_CPP_INLINE Bit32u T_KEY(Bit32u val32)
|
||||
{
|
||||
return L_KEY(lower_t(val32));
|
||||
}
|
||||
|
||||
BX_CPP_INLINE Bit32u F_KEY(Bit32u x0, Bit32u x1, Bit32u x2, Bit32u x3, Bit32u round_key)
|
||||
{
|
||||
return x0 ^ T_KEY(x1 ^ x2 ^ x3 ^ round_key);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VSM4KEY4_VdqHdqWdqR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister r;
|
||||
unsigned len = i->getVL();
|
||||
r.clear();
|
||||
|
||||
for (unsigned n=0; n < len; n++) {
|
||||
BxPackedXmmRegister op1 = BX_READ_AVX_REG_LANE(i->src1(), n), op2 = BX_READ_AVX_REG_LANE(i->src2(), n);
|
||||
|
||||
Bit32u P[4], C[4];
|
||||
P[0] = op1.xmm32u(0);
|
||||
P[1] = op1.xmm32u(1);
|
||||
P[2] = op1.xmm32u(2);
|
||||
P[3] = op1.xmm32u(3);
|
||||
|
||||
C[0] = F_KEY(P[0], P[1], P[2], P[3], op2.xmm32u(0));
|
||||
C[1] = F_KEY(P[1], P[2], P[3], C[0], op2.xmm32u(1));
|
||||
C[2] = F_KEY(P[2], P[3], C[0], C[1], op2.xmm32u(2));
|
||||
C[3] = F_KEY(P[3], C[0], C[1], C[2], op2.xmm32u(3));
|
||||
|
||||
r.vmm32u(4*n + 0) = C[0];
|
||||
r.vmm32u(4*n + 1) = C[1];
|
||||
r.vmm32u(4*n + 2) = C[2];
|
||||
r.vmm32u(4*n + 3) = C[3];
|
||||
}
|
||||
|
||||
BX_WRITE_AVX_REG(i->dst(), r);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_CPP_INLINE Bit32u L_RND(Bit32u val32)
|
||||
{
|
||||
Bit32u tmp = val32;
|
||||
tmp ^= rol32(val32, 2);
|
||||
tmp ^= rol32(val32, 10);
|
||||
tmp ^= rol32(val32, 18);
|
||||
tmp ^= rol32(val32, 24);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
BX_CPP_INLINE Bit32u T_RND(Bit32u val32)
|
||||
{
|
||||
return L_RND(lower_t(val32));
|
||||
}
|
||||
|
||||
BX_CPP_INLINE Bit32u F_RND(Bit32u x0, Bit32u x1, Bit32u x2, Bit32u x3, Bit32u round_key)
|
||||
{
|
||||
return x0 ^ T_RND(x1 ^ x2 ^ x3 ^ round_key);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VSM4RNDS4_VdqHdqWdqR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister r;
|
||||
unsigned len = i->getVL();
|
||||
r.clear();
|
||||
|
||||
for (unsigned n=0; n < len; n++) {
|
||||
BxPackedXmmRegister op1 = BX_READ_AVX_REG_LANE(i->src1(), n), op2 = BX_READ_AVX_REG_LANE(i->src2(), n);
|
||||
|
||||
Bit32u P[4], C[4];
|
||||
P[0] = op1.xmm32u(0);
|
||||
P[1] = op1.xmm32u(1);
|
||||
P[2] = op1.xmm32u(2);
|
||||
P[3] = op1.xmm32u(3);
|
||||
|
||||
C[0] = F_RND(P[0], P[1], P[2], P[3], op2.xmm32u(0));
|
||||
C[1] = F_RND(P[1], P[2], P[3], C[0], op2.xmm32u(1));
|
||||
C[2] = F_RND(P[2], P[3], C[0], C[1], op2.xmm32u(2));
|
||||
C[3] = F_RND(P[3], C[0], C[1], C[2], op2.xmm32u(3));
|
||||
|
||||
r.vmm32u(4*n + 0) = C[0];
|
||||
r.vmm32u(4*n + 1) = C[1];
|
||||
r.vmm32u(4*n + 2) = C[2];
|
||||
r.vmm32u(4*n + 3) = C[3];
|
||||
}
|
||||
|
||||
BX_WRITE_AVX_REG(i->dst(), r);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue