mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

add APX CPUID and XCR0 flag to enums in header files

Browse Source
This commit is contained in:
Stanislav Shwartsman 2024-11-14 20:14:48 +02:00
parent 16959231ed
commit 241a3900bb
3 changed files with 11 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
bochs/cpu/cpuid.h
View File

@ -648,7 +648,9 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [17:17] Flexible UIRET: UIRET sets UIF to the RFLAGS[1] image loaded from the stack
// [18:18] CET_SSS
// [19:19] AVX10 support and CPUID leaf 0x24
// [22:20] reserved
// [20:20] reserved
// [21:21] APX support
// [22:22] reserved
// [23:23] MWAIT and CPUID LEAF5 support (to be used by VMM)
// [31:24] reserved
@ -673,7 +675,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPUID_STD7_SUBLEAF1_EDX_CET_SSS (1 << 18)
#define BX_CPUID_STD7_SUBLEAF1_EDX_AVX10 (1 << 19)
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED20 (1 << 20)
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED21 (1 << 21)
#define BX_CPUID_STD7_SUBLEAF1_EDX_APX (1 << 21)
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED22 (1 << 22)
#define BX_CPUID_STD7_SUBLEAF1_EDX_MWAIT_AND_LEAF5 (1 << 23)
// ...

2
bochs/cpu/crregs.cc
View File

@ -1856,6 +1856,8 @@ void BX_CPU_C::xsave_xrestor_init(void)
xsave_restore[xcr0_t::BX_XCR0_XTILEDATA_BIT].xrstor_init_method = &BX_CPU_C::xrstor_init_tiledata_state;
}
#endif
// XCR0[19]: APX state (not implemented)
}
#if BX_CPU_LEVEL >= 5

5
bochs/cpu/crregs.h
View File

@ -268,6 +268,7 @@ const unsigned XSAVE_LBR_STATE_LEN = 808;
const unsigned XSAVE_HWP_STATE_LEN = 8;
const unsigned XSAVE_XTILECFG_STATE_LEN = 64;
const unsigned XSAVE_XTILEDATA_STATE_LEN = 8192;
const unsigned XSAVE_APX_STATE_LEN = 128;
const unsigned XSAVE_FPU_STATE_OFFSET = 0;
const unsigned XSAVE_SSE_STATE_OFFSET = 160;
@ -278,6 +279,7 @@ const unsigned XSAVE_HI_ZMM_STATE_OFFSET = 1664;
const unsigned XSAVE_PKRU_STATE_OFFSET = 2688;
const unsigned XSAVE_XTILECFG_STATE_OFFSET = 2752;
const unsigned XSAVE_XTILEDATA_STATE_OFFSET = 2816;
const unsigned XSAVE_APX_STATE_OFFSET = 960; // repurpose deprecated BND (MPX) state
struct xcr0_t {
Bit32u val32; // 32bit value of register
@ -302,6 +304,7 @@ struct xcr0_t {
BX_XCR0_HWP_BIT = 16, // not implemented yet
BX_XCR0_XTILECFG_BIT = 17,
BX_XCR0_XTILEDATA_BIT = 18,
BX_XCR0_APX_BIT = 19,
BX_XCR0_LAST // make sure it is < 32
};
@ -324,6 +327,7 @@ struct xcr0_t {
#define BX_XCR0_HWP_MASK (1 << xcr0_t::BX_XCR0_HWP_BIT)
#define BX_XCR0_XTILECFG_MASK (1 << xcr0_t::BX_XCR0_XTILECFG_BIT)
#define BX_XCR0_XTILEDATA_MASK (1 << xcr0_t::BX_XCR0_XTILEDATA_BIT)
#define BX_XCR0_APX_MASK (1 << xcr0_t::BX_XCR0_APX_BIT)
#define BX_XCR0_XTILE_BITS_MASK (BX_XCR0_XTILECFG_MASK | BX_XCR0_XTILEDATA_MASK)
@ -345,6 +349,7 @@ struct xcr0_t {
IMPLEMENT_CRREG_ACCESSORS(HWP, BX_XCR0_HWP_BIT);
IMPLEMENT_CRREG_ACCESSORS(XTILECFG, BX_XCR0_XTILECFG_BIT);
IMPLEMENT_CRREG_ACCESSORS(XTILEDATA, BX_XCR0_XTILEDATA_BIT);
IMPLEMENT_CRREG_ACCESSORS(APX, BX_XCR0_APX_BIT);
BX_CPP_INLINE Bit32u get32() const { return val32; }
BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }