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- behaviour of the busmaster dma registers fixed and info messages improved

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(BM-DMA feature still not implemented)
This commit is contained in:
Volker Ruppert 2005-02-06 13:05:20 +00:00
parent 8affb6d10b
commit 2137cef71f
2 changed files with 65 additions and 26 deletions
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83
bochs/iodev/pci_ide.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: pci_ide.cc,v 1.7 2004-08-06 15:49:54 vruppert Exp $
// $Id: pci_ide.cc,v 1.8 2005-02-06 13:05:19 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -40,7 +40,7 @@
bx_pci_ide_c *thePciIdeController = NULL;
const Bit8u bmide_iomask[16] = {1, 0, 1, 0, 4, 0, 0, 0, 1, 0, 1, 0, 4, 0, 0, 0};
const Bit8u bmdma_iomask[16] = {1, 0, 1, 0, 4, 0, 0, 0, 1, 0, 1, 0, 4, 0, 0, 0};
int
libpci_ide_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
@ -107,11 +107,16 @@ bx_pci_ide_c::reset(unsigned type)
BX_PIDE_THIS s.pci_conf[0x43] = 0x80;
}
BX_PIDE_THIS s.pci_conf[0x44] = 0x00;
for (unsigned i=0; i<2; i++) {
BX_PIDE_THIS s.bmdma_command[i] = 0;
BX_PIDE_THIS s.bmdma_status[i] = 0;
BX_PIDE_THIS s.bmdma_dtpr[i] = 0;
}
// This should be done by the PCI BIOS
WriteHostDWordToLittleEndian(&BX_PIDE_THIS s.pci_conf[0x20], 0x0000);
DEV_pci_set_base_io(this, read_handler, write_handler,
&BX_PIDE_THIS s.bmide_addr, &BX_PIDE_THIS s.pci_conf[0x20],
16, &bmide_iomask[0], "PIIX3 PCI IDE controller");
&BX_PIDE_THIS s.bmdma_addr, &BX_PIDE_THIS s.pci_conf[0x20],
16, &bmdma_iomask[0], "PIIX3 PCI IDE controller");
}
@ -135,15 +140,28 @@ bx_pci_ide_c::read(Bit32u address, unsigned io_len)
#else
UNUSED(this_ptr);
#endif // !BX_USE_PIDE_SMF
Bit8u offset;
Bit8u offset, channel;
Bit32u value = 0xffffffff;
offset = address - BX_PIDE_THIS s.bmide_addr;
BX_INFO(("BM-IDE read register 0x%08x len %d", offset, io_len));
return BX_PIDE_THIS s.bmide_regs[offset];
/* switch (address) {
}
offset = address - BX_PIDE_THIS s.bmdma_addr;
channel = (offset >> 3);
offset &= 0x07;
switch (offset) {
case 0x00:
value = BX_PIDE_THIS s.bmdma_command[channel];
BX_INFO(("BM-DMA read command register, channel %d, value = 0x%02x", channel, value));
break;
case 0x02:
value = BX_PIDE_THIS s.bmdma_status[channel];
BX_INFO(("BM-DMA read status register, channel %d, value = 0x%02x", channel, value));
break;
case 0x04:
value = BX_PIDE_THIS s.bmdma_dtpr[channel];
BX_INFO(("BM-DMA read DTP register, channel %d, value = 0x%04x", channel, value));
break;
}
return(0xffffffff);*/
return value;
}
@ -165,13 +183,32 @@ bx_pci_ide_c::write(Bit32u address, Bit32u value, unsigned io_len)
#else
UNUSED(this_ptr);
#endif // !BX_USE_PIDE_SMF
Bit8u offset;
Bit8u offset, channel;
offset = address - BX_PIDE_THIS s.bmide_addr;
BX_INFO(("BM-IDE write register 0x%08x len %d", offset, io_len));
BX_PIDE_THIS s.bmide_regs[offset] = (Bit8u)value;
/* switch (address) {
}*/
offset = address - BX_PIDE_THIS s.bmdma_addr;
channel = (offset >> 3);
offset &= 0x07;
switch (offset) {
case 0x00:
if (value & 0x01) {
BX_PIDE_THIS s.bmdma_status[channel] |= 0x01;
} else {
BX_PIDE_THIS s.bmdma_status[channel] &= ~0x01;
}
BX_PIDE_THIS s.bmdma_command[channel] = (value & 0x09);
BX_INFO(("BM-DMA write command register, channel %d, value = 0x%02x", channel, value));
break;
case 0x02:
BX_PIDE_THIS s.bmdma_status[channel] = (value & 0x60)
| (BX_PIDE_THIS s.bmdma_status[channel] & 0x01)
| (BX_PIDE_THIS s.bmdma_status[channel] & (~value & 0x06));
BX_INFO(("BM-DMA write status register, channel %d, value = 0x%02x", channel, value));
break;
case 0x04:
BX_PIDE_THIS s.bmdma_dtpr[channel] = value;
BX_INFO(("BM-DMA write DTP register, channel %d, value = 0x%04x", channel, value));
break;
}
}
@ -229,7 +266,7 @@ bx_pci_ide_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
#endif // !BX_USE_PIDE_SMF
Bit8u value8, oldval;
bx_bool bmide_change = 0;
bx_bool bmdma_change = 0;
if (io_len <= 4) {
for (unsigned i=0; i<io_len; i++) {
@ -246,18 +283,18 @@ bx_pci_ide_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
break;
case 0x20:
case 0x21:
bmide_change |= (value8 != oldval);
bmdma_change |= (value8 != oldval);
default:
BX_PIDE_THIS s.pci_conf[address+i] = value8;
BX_DEBUG(("PIIX3 PCI IDE write register 0x%02x value 0x%02x", address,
value8));
}
}
if (bmide_change) {
if (bmdma_change) {
DEV_pci_set_base_io(BX_PIDE_THIS_PTR, read_handler, write_handler,
&BX_PIDE_THIS s.bmide_addr, &BX_PIDE_THIS s.pci_conf[0x20],
16, &bmide_iomask[0], "PIIX3 PCI IDE controller");
BX_INFO(("new BM-IDE address: 0x%04x", BX_PIDE_THIS s.bmide_addr));
&BX_PIDE_THIS s.bmdma_addr, &BX_PIDE_THIS s.pci_conf[0x20],
16, &bmdma_iomask[0], "PIIX3 PCI IDE controller");
BX_INFO(("new BM-DMA address: 0x%04x", BX_PIDE_THIS s.bmdma_addr));
}
}
}

8
bochs/iodev/pci_ide.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: pci_ide.h,v 1.3 2004-07-11 20:38:48 vruppert Exp $
// $Id: pci_ide.h,v 1.4 2005-02-06 13:05:20 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2004 MandrakeSoft S.A.
@ -48,8 +48,10 @@ private:
struct {
Bit8u pci_conf[256];
Bit32u bmide_addr;
Bit8u bmide_regs[16];
Bit32u bmdma_addr;
Bit8u bmdma_command[2];
Bit8u bmdma_status[2];
Bit32u bmdma_dtpr[2];
} s;
static Bit32u read_handler(void *this_ptr, Bit32u address, unsigned io_len);