Recommitted SSE code reorganization.
Fix in FXSAVE/FXRESTOR opcodes -> If the OSFXSR bitCR4 is not set, the FXRSTOR instruction does not restore the states of the XMM and MXCSR registers.
This commit is contained in:
Stanislav Shwartsman
parent
486b19ae29
commit
1cd38bb7dd
@ -63,7 +63,8 @@ OBJS = \
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ctrl_xfer16.o \
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mmx.o \
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sse.o \
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sse2.o \
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sse_move.o \
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sse_pfp.o \
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soft_int.o \
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io_pro.o \
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$(APIC_OBJS) \
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@ -732,7 +733,18 @@ sse.o: sse.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../debug/debug.h \
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../iodev/serial.h ../iodev/unmapped.h ../iodev/eth.h ../iodev/ne2k.h \
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../iodev/guest2host.h ../iodev/slowdown_timer.h \
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../instrument/stubs/instrument.h
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sse2.o: sse2.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../debug/debug.h \
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sse_move.o: sse.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../debug/debug.h \
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../bxversion.h ../gui/siminterface.h ../state_file.h ../cpu/cpu.h \
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../cpu/lazy_flags.h ../cpu/i387.h ../memory/memory.h ../pc_system.h \
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../plugin.h ../extplugin.h ../ltdl.h ../gui/gui.h ../gui/textconfig.h \
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../gui/keymap.h ../iodev/iodev.h ../iodev/vga.h ../iodev/biosdev.h \
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../iodev/cmos.h ../iodev/dma.h ../iodev/floppy.h ../iodev/harddrv.h \
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../iodev/cdrom.h ../iodev/keyboard.h ../iodev/parallel.h \
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../iodev/pic.h ../iodev/pit.h ../iodev/pit_wrap.h ../iodev/pit82c54.h \
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../iodev/serial.h ../iodev/unmapped.h ../iodev/eth.h ../iodev/ne2k.h \
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../iodev/guest2host.h ../iodev/slowdown_timer.h \
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../instrument/stubs/instrument.h
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sse_pfp.o: sse_pfp.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../debug/debug.h \
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../bxversion.h ../gui/siminterface.h ../state_file.h ../cpu/cpu.h \
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../cpu/lazy_flags.h ../cpu/i387.h ../memory/memory.h ../pc_system.h \
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../plugin.h ../extplugin.h ../ltdl.h ../gui/gui.h ../gui/textconfig.h \
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.123 2002-12-20 09:11:37 sshwarts Exp $
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// $Id: cpu.h,v 1.124 2002-12-22 20:12:59 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1278,7 +1278,7 @@ class BX_MEM_C;
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#include "cpu/i387.h"
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#if BX_SUPPORT_SSE != 0
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#if BX_SUPPORT_SSE
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#include "cpu/xmm.h"
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#endif
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@ -1416,7 +1416,7 @@ union {
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i387_t the_i387;
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#if BX_SUPPORT_SSE != 0
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#if BX_SUPPORT_SSE
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bx_xmm_reg_t xmm[BX_XMM_REGISTERS];
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bx_mxcsr_t mxcsr;
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#endif
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@ -2037,12 +2037,12 @@ union {
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BX_SMF void PSLLQ_PqIb(bxInstruction_c *i);
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/* MMX */
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#if BX_SUPPORT_MMX || BX_SUPPORT_SSE != 0
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#if BX_SUPPORT_MMX || BX_SUPPORT_SSE
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BX_SMF void prepareMMX(void);
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BX_SMF void printMmxRegisters(void);
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#endif
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#if BX_SUPPORT_SSE != 0
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#if BX_SUPPORT_SSE
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BX_SMF void prepareSSE(void);
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#endif
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@ -2704,7 +2704,7 @@ union {
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#define Write_RMW_virtual_dword(val32) write_RMW_virtual_dword(val32)
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#define Write_RMW_virtual_qword(val64) write_RMW_virtual_qword(val64)
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#if BX_SUPPORT_SSE != 0
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#if BX_SUPPORT_SSE
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BX_SMF void readVirtualDQword(unsigned s, bx_address off, Bit8u *data);
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BX_SMF void readVirtualDQwordAligned(unsigned s, bx_address off, Bit8u *data);
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BX_SMF void writeVirtualDQword(unsigned s, bx_address off, Bit8u *data);
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2219
bochs/cpu/sse.cc
2219
bochs/cpu/sse.cc
File diff suppressed because it is too large
Load Diff
2971
bochs/cpu/sse2.cc
2971
bochs/cpu/sse2.cc
File diff suppressed because it is too large
Load Diff
878
bochs/cpu/sse_move.cc
Normal file
878
bochs/cpu/sse_move.cc
Normal file
@ -0,0 +1,878 @@
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2002 Stanislav Shwartsman
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// Written by Stanislav Shwartsman <gate@fidonet.org.il>
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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/* *************************** */
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/* SSE: MEMORY MOVE OPERATIONS */
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/* *************************** */
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/* MOVUPS: 0F 10 */
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/* MOVUPD: 66 0F 10 */
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/* MOVDQU: F3 0F 6F */
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void BX_CPU_C::MOVUPS_VpsWps(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BxPackedXmmRegister op;
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/* op is a register or memory reference */
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if (i->modC0()) {
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op = BX_READ_XMM_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
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}
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/* now write result back to destination */
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BX_WRITE_XMM_REG(i->nnn(), op);
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#else
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BX_INFO(("MOVUPS/PD/MOVDQU_VpsWps: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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/* MOVUPS: 0F 11 */
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/* MOVUPD: 66 0F 11 */
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/* MOVDQU: F3 0F 7F */
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void BX_CPU_C::MOVUPS_WpsVps(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
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/* op is a register or memory reference */
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if (i->modC0()) {
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BX_WRITE_XMM_REG(i->rm(), op);
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}
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else {
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writeVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
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}
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#else
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BX_INFO(("MOVUPS/PD/MOVDQU_WpsVps: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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/* MOVAPS: 0F 28 */
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/* MOVAPD: 66 0F 28 */
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/* MOVDQA: F3 0F 6F */
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void BX_CPU_C::MOVAPS_VpsWps(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BxPackedXmmRegister op;
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/* op is a register or memory reference */
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if (i->modC0()) {
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op = BX_READ_XMM_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op);
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}
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/* now write result back to destination */
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BX_WRITE_XMM_REG(i->nnn(), op);
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#else
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BX_INFO(("MOVAPS/PD/MOVDQA_VpsWps: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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/* MOVAPS: 0F 29 */
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/* MOVAPD: 66 0F 29 */
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/* MOVDQA: F3 0F 7F */
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void BX_CPU_C::MOVAPS_WpsVps(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
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/* op is a register or memory reference */
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if (i->modC0()) {
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BX_WRITE_XMM_REG(i->rm(), op);
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}
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else {
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writeVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op);
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}
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#else
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BX_INFO(("MOVAPS/PD/MOVDQA_WpsVps: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVSS_VssWss: SSE instruction still not implemented"));
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#else
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BX_INFO(("MOVSS_VssWss: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVSS_WssVss(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVSS_WssVss: SSE instruction still not implemented"));
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#else
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BX_INFO(("MOVSS_WssVss: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVSD_VsdWsd(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVSD_VsdWsd: SSE2 instruction still not implemented"));
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#else
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BX_INFO(("MOVSD_VsdWsd: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVSD_WsdVsd(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVSD_WsdVsd: SSE2 instruction still not implemented"));
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#else
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BX_INFO(("MOVSD_WsdVsd: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVLPS_VpsMq: SSE instruction still not implemented"));
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#else
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BX_INFO(("MOVLPS_VpsMq: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVLPS_MqVps(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVLPS_MqVps: SSE instruction still not implemented"));
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#else
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BX_INFO(("MOVLPS_MqVps: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVHPS_VpsMq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVHPS_VpsMq: SSE instruction still not implemented"));
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#else
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BX_INFO(("MOVHPS_VpsMq: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVHPS_MqVps: SSE instruction still not implemented"));
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#else
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BX_INFO(("MOVHPS_MqVps: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MASKMOVQ_PqPRq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_PANIC(("MASKMOVQ_PqPRq: SSE instruction still not implemented"));
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#else
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BX_INFO(("MASKMOVQ_PqPRq: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVMSKPS_GdVRps: SSE instruction still not implemented"));
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#else
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BX_INFO(("MOVMSKPS_GdVRps: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVMSKPD_EdVRpd(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVMSKPD_EdVRpd: SSE2 instruction still not implemented"));
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#else
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BX_INFO(("MOVMSKPD_EdVRpd: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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/* 66 0F 6E */
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void BX_CPU_C::MOVD_VdqEd(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareSSE();
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BxPackedXmmRegister op;
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Bit32u val32;
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/* val32 is a register or memory reference */
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if (i->modC0()) {
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val32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &val32);
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}
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op.xmm64u(1) = 0;
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op.xmm32u(1) = 0;
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op.xmm32u(0) = val32;
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/* now write result back to destination */
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BX_WRITE_XMM_REG(i->nnn(), op);
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#else
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BX_INFO(("MOVD_VdqEd: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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/* 66 0F 7E */
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void BX_CPU_C::MOVD_EdVd(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareSSE();
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BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
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Bit32u val32 = op.xmm32u(0);
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/* destination is a register or memory reference */
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if (i->modC0()) {
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BX_WRITE_32BIT_REG(i->rm(), val32);
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}
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else {
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write_virtual_dword(i->seg(), RMAddr(i), &val32);
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}
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#else
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BX_INFO(("MOVD_EdVd: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVQ_VqWq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVQ_VqWq: SSE2 instruction still not implemented"));
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#else
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BX_INFO(("MOVQ_VqWq: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MOVQ_WqVq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVQ_WqVq: SSE2 instruction still not implemented"));
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#else
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BX_INFO(("MOVQ_WqVq: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::MASKMOVDQU_VdqVRdq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MASKMOVDQU_VdqVRdq: SSE2 instruction still not implemented"));
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#else
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BX_INFO(("MASKMOVDQU_VdqVRdq: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
|
||||
|
||||
/* F2 0F D6 */
|
||||
void BX_CPU_C::MOVDQ2Q_PqVRq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
BxPackedMmxRegister mm;
|
||||
MMXUQ(mm) = op.xmm64u(0);
|
||||
|
||||
FPU_TWD = 0;
|
||||
FPU_TOS = 0; /* Each time an MMX instruction is */
|
||||
FPU_SWD &= 0xc7ff; /* executed, the TOS value is set to 000b */
|
||||
|
||||
BX_WRITE_MMX_REG(i->rm(), mm);
|
||||
#else
|
||||
BX_INFO(("MOVDQ2Q_PqVRq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* F3 0F D6 */
|
||||
void BX_CPU_C::MOVQ2DQ_VdqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op;
|
||||
BxPackedMmxRegister mm = BX_READ_MMX_REG(i->nnn());
|
||||
op.xmm64u(0) = MMXUQ(mm);
|
||||
op.xmm64u(1) = 0;
|
||||
|
||||
FPU_TWD = 0;
|
||||
FPU_TOS = 0; /* Each time an MMX instruction is */
|
||||
FPU_SWD &= 0xc7ff; /* executed, the TOS value is set to 000b */
|
||||
|
||||
BX_WRITE_XMM_REG(i->rm(), op);
|
||||
#else
|
||||
BX_INFO(("MOVQ2DQ_VdqQq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ****************************** */
|
||||
/* SSE: MEMORY SHUFFLE OPERATIONS */
|
||||
/* ****************************** */
|
||||
|
||||
void BX_CPU_C::SHUFPS_VpsWpsIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SHUFPS_VpsWpsIb: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("SHUFPS_VpsWpsIb: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::SHUFPD_VpdWpdIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SHUFPD_VpdWpdIb: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("SHUFPD_VpdWpdIb: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::UNPCKLPS_VpsWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("UNPCKLPS_VpsWq: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("UNPCKLPS_VpsWq: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::UNPCKHPS_VpsWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("UNPCKHPS_VpsWq: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("UNPCKHPS_VpsWq: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::UNPCKLPD_VpdWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("UNPCKLPD_VpdWq: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("UNPCKLPD_VpdWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::UNPCKHPD_VpdWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("UNPCKHPD_VpdWq: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("UNPCKHPD_VpdWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 60 */
|
||||
void BX_CPU_C::PUNPCKLBW_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmmubyte(0x0) = op1.xmmubyte(0);
|
||||
result.xmmubyte(0x1) = op2.xmmubyte(0);
|
||||
result.xmmubyte(0x2) = op1.xmmubyte(1);
|
||||
result.xmmubyte(0x3) = op2.xmmubyte(1);
|
||||
result.xmmubyte(0x4) = op1.xmmubyte(2);
|
||||
result.xmmubyte(0x5) = op2.xmmubyte(2);
|
||||
result.xmmubyte(0x6) = op1.xmmubyte(3);
|
||||
result.xmmubyte(0x7) = op2.xmmubyte(3);
|
||||
result.xmmubyte(0x8) = op1.xmmubyte(4);
|
||||
result.xmmubyte(0x9) = op2.xmmubyte(4);
|
||||
result.xmmubyte(0xA) = op1.xmmubyte(5);
|
||||
result.xmmubyte(0xB) = op2.xmmubyte(5);
|
||||
result.xmmubyte(0xC) = op1.xmmubyte(6);
|
||||
result.xmmubyte(0xD) = op2.xmmubyte(6);
|
||||
result.xmmubyte(0xE) = op1.xmmubyte(7);
|
||||
result.xmmubyte(0xF) = op2.xmmubyte(7);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKLBW_VdqWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 61 */
|
||||
void BX_CPU_C::PUNPCKLWD_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm16u(0) = op1.xmm16u(0);
|
||||
result.xmm16u(1) = op2.xmm16u(0);
|
||||
result.xmm16u(2) = op1.xmm16u(1);
|
||||
result.xmm16u(3) = op2.xmm16u(1);
|
||||
result.xmm16u(4) = op1.xmm16u(2);
|
||||
result.xmm16u(5) = op2.xmm16u(2);
|
||||
result.xmm16u(6) = op1.xmm16u(3);
|
||||
result.xmm16u(7) = op2.xmm16u(3);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKLWD_VdqWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 62 */
|
||||
void BX_CPU_C::PUNPCKLDQ_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = op1.xmm32u(0);
|
||||
result.xmm32u(1) = op2.xmm32u(0);
|
||||
result.xmm32u(2) = op1.xmm32u(1);
|
||||
result.xmm32u(3) = op2.xmm32u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKLDQ_VdqWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 68 */
|
||||
void BX_CPU_C::PUNPCKHBW_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmmubyte(0x0) = op1.xmmubyte(0x8);
|
||||
result.xmmubyte(0x1) = op2.xmmubyte(0x8);
|
||||
result.xmmubyte(0x2) = op1.xmmubyte(0x9);
|
||||
result.xmmubyte(0x3) = op2.xmmubyte(0x9);
|
||||
result.xmmubyte(0x4) = op1.xmmubyte(0xA);
|
||||
result.xmmubyte(0x5) = op2.xmmubyte(0xA);
|
||||
result.xmmubyte(0x6) = op1.xmmubyte(0xB);
|
||||
result.xmmubyte(0x7) = op2.xmmubyte(0xB);
|
||||
result.xmmubyte(0x8) = op1.xmmubyte(0xC);
|
||||
result.xmmubyte(0x9) = op2.xmmubyte(0xC);
|
||||
result.xmmubyte(0xA) = op1.xmmubyte(0xD);
|
||||
result.xmmubyte(0xB) = op2.xmmubyte(0xD);
|
||||
result.xmmubyte(0xC) = op1.xmmubyte(0xE);
|
||||
result.xmmubyte(0xD) = op2.xmmubyte(0xE);
|
||||
result.xmmubyte(0xE) = op1.xmmubyte(0xF);
|
||||
result.xmmubyte(0xF) = op2.xmmubyte(0xF);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKHBW_VdqWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 69 */
|
||||
void BX_CPU_C::PUNPCKHWD_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm16u(0) = op1.xmm16u(4);
|
||||
result.xmm16u(1) = op2.xmm16u(4);
|
||||
result.xmm16u(2) = op1.xmm16u(5);
|
||||
result.xmm16u(3) = op2.xmm16u(5);
|
||||
result.xmm16u(4) = op1.xmm16u(6);
|
||||
result.xmm16u(5) = op2.xmm16u(6);
|
||||
result.xmm16u(6) = op1.xmm16u(7);
|
||||
result.xmm16u(7) = op2.xmm16u(7);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKHWD_VdqWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 6A */
|
||||
void BX_CPU_C::PUNPCKHDQ_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = op1.xmm32u(2);
|
||||
result.xmm32u(1) = op2.xmm32u(2);
|
||||
result.xmm32u(2) = op1.xmm32u(3);
|
||||
result.xmm32u(3) = op2.xmm32u(3);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKHDQ_VdqWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 6C */
|
||||
void BX_CPU_C::PUNPCKLQDQ_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(1) = op2.xmm64u(0);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("PUNPCKLQDQ_VdqWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 6D */
|
||||
void BX_CPU_C::PUNPCKHQDQ_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = op1.xmm64u(1);
|
||||
result.xmm64u(1) = op2.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKHQDQ_VdqWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 70 */
|
||||
void BX_CPU_C::PSHUFD_VdqWdqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op, result;
|
||||
Bit8u order = i->Ib();
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = op.xmm32u((order >> 0) & 0x3);
|
||||
result.xmm32u(1) = op.xmm32u((order >> 2) & 0x3);
|
||||
result.xmm32u(2) = op.xmm32u((order >> 4) & 0x3);
|
||||
result.xmm32u(3) = op.xmm32u((order >> 6) & 0x3);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PSHUFD_VdqWdqIb: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* F2 0F 70 */
|
||||
void BX_CPU_C::PSHUFHW_VqWqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op, result;
|
||||
Bit8u order = i->Ib();
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = op.xmm64u(0);
|
||||
result.xmm16u(4) = op.xmm16u(4 + ((order >> 0) & 0x3));
|
||||
result.xmm16u(5) = op.xmm16u(4 + ((order >> 2) & 0x3));
|
||||
result.xmm16u(6) = op.xmm16u(4 + ((order >> 4) & 0x3));
|
||||
result.xmm16u(7) = op.xmm16u(4 + ((order >> 6) & 0x3));
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PSHUFHW_VqWqIb: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* F3 0F 70 */
|
||||
void BX_CPU_C::PSHUFLW_VqWqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op, result;
|
||||
Bit8u order = i->Ib();
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
result.xmm16u(0) = op.xmm16u((order >> 0) & 0x3);
|
||||
result.xmm16u(1) = op.xmm16u((order >> 2) & 0x3);
|
||||
result.xmm16u(2) = op.xmm16u((order >> 4) & 0x3);
|
||||
result.xmm16u(3) = op.xmm16u((order >> 6) & 0x3);
|
||||
result.xmm64u(1) = op.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PSHUFLW_VqWqIb: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* **************************** */
|
||||
/* SSE: STORE DATA NON-TEMPORAL */
|
||||
/* **************************** */
|
||||
|
||||
/* 0F C3 */
|
||||
void BX_CPU_C::MOVNTI_MdGd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
|
||||
if (i->modC0()) {
|
||||
BX_INFO(("MOVNTI_MdGd: must be memory reference"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
Bit32u val32 = BX_READ_32BIT_REG(i->nnn());
|
||||
write_virtual_dword(i->seg(), RMAddr(i), &val32);
|
||||
|
||||
#else
|
||||
BX_INFO(("MOVNTI_MdGd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* MOVNTPS: 0F 2B */
|
||||
/* MOVNTPD: 66 0F 2B */
|
||||
/* MOVNTDQ: 66 0F E7 */
|
||||
|
||||
void BX_CPU_C::MOVNTPS_MdqVps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
if (i->modC0()) {
|
||||
BX_INFO(("MOVNTPS_MdqVps: must be memory reference"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
BxPackedXmmRegister val128 = BX_READ_XMM_REG(i->nnn());
|
||||
writeVirtualDQword(i->seg(), RMAddr(i), (Bit8u *)(&val128));
|
||||
|
||||
#else
|
||||
BX_INFO(("MOVNTPS/PD/MOVNTDQ_MdqVdq: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
770
bochs/cpu/sse_pfp.cc
Normal file
770
bochs/cpu/sse_pfp.cc
Normal file
@ -0,0 +1,770 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2002 Stanislav Shwartsman
|
||||
// Written by Stanislav Shwartsman <gate@fidonet.org.il>
|
||||
//
|
||||
// This library is free software; you can redistribute it and/or
|
||||
// modify it under the terms of the GNU Lesser General Public
|
||||
// License as published by the Free Software Foundation; either
|
||||
// version 2 of the License, or (at your option) any later version.
|
||||
//
|
||||
// This library is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
// Lesser General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU Lesser General Public
|
||||
// License along with this library; if not, write to the Free Software
|
||||
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
//
|
||||
|
||||
|
||||
|
||||
#define NEED_CPU_REG_SHORTCUTS 1
|
||||
#include "bochs.h"
|
||||
#define LOG_THIS BX_CPU_THIS_PTR
|
||||
|
||||
|
||||
void BX_CPU_C::CVTSI2SD_VsdEd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTSI2SD_VsdEd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTSI2SD_VsdEd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTPI2PD_VpdQd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTPI2PD_VpdQd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTPI2PD_VpdQd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTTSD2SI_GdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTTSD2SI_GdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTTSD2SI_GdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTSD2SI_GdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTSD2SI_GdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTSD2SI_GdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTTPD2PI_PqWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTTPD2PI_PqWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTTPD2PI_PqWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTPS2PD_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTPS2PD_VpsWps: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTPS2PD_VpsWps: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTPD2PS_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTPD2PS_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTPD2PS_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTPD2PI_PqWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTPD2PI_PqWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTPD2PI_PqWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTSD2SS_VsdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTSD2SS_VsdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTSD2SS_VsdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTSS2SD_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTSS2SD_VssWss: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTSS2SD_VssWss: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTDQ2PS_VpsWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTDQ2PS_VpsWdq: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTDQ2PS_VpsWdq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTPS2DQ_VdqWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTPS2DQ_VdqWps: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTPS2DQ_VdqWps: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTTPS2DQ_VdqWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTTPS2DQ_VdqWps: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTTPS2DQ_VdqWps: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTPI2PS_VpsQq: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTPI2PS_VpsQq: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTSI2SS_VssEd: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTSI2SS_VssEd: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTTPS2PI_PqWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTTPS2PI_PqWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTTPS2PI_PqWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTTSS2SI_GdWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTTSS2SI_GdWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTTSS2SI_GdWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTPS2PI_PqWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTPS2PI_PqWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTPS2PI_PqWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTSS2SI_GdWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTSS2SI_GdWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTSS2SI_GdWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTTPD2DQ_VqWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTTPD2DQ_VqWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTTPD2DQ_VqWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTPD2DQ_VqWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTPD2DQ_VqWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTPD2DQ_VqWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CVTDQ2PD_VpdWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTDQ2PD_VpdWq: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CVTDQ2PD_VpdWq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::COMISS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("COMISS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("COMISS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::COMISD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("COMISD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("COMISD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::UCOMISS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("UCOMISS_VssWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("UCOMISS_VssWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::UCOMISD_VsdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("UCOMISD_VsdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("UCOMISD_VsdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::SQRTSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SQRTSS_VssWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("SQRTSS_VssWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::SQRTSD_VsdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SQRTSD_VsdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("SQRTSD_VsdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::SQRTPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SQRTPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("SQRTPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::SQRTPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SQRTPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("SQRTPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::RSQRTPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("RSQRTPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("RSQRTPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("RSQRTSS_VssWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("RSQRTSS_VssWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::RCPPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("RCPPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("RCPPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("RCPSS_VssWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("RCPSS_VssWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ADDSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ADDSS_VssWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("ADDSS_VssWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ADDSD_VsdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ADDSD_VsdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("ADDSD_VsdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ADDPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ADDPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("ADDPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ADDPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ADDPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("ADDPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MULSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MULSS_VssWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MULSS_VssWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MULSD_VsdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MULSD_VsdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MULSD_VsdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MULPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MULPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MULPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MULPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MULPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MULPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::SUBSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SUBSS_VssWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("SUBSS_VssWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::SUBSD_VsdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SUBSD_VsdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("SUBSD_VsdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::SUBPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SUBPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("SUBPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::SUBPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SUBPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("SUBPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MINSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MINSS_VssWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MINSS_VssWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MINSD_VsdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MINSD_VsdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MINSD_VsdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MINPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MINPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MINPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MINPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MINPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MINPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::DIVSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("DIVSS_VssWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("DIVSS_VssWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::DIVSD_VsdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("DIVSD_VsdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("DIVSD_VsdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::DIVPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("DIVPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("DIVPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::DIVPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("DIVPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("DIVPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MAXPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MAXPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MAXPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MAXSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MAXSS_VssWss: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MAXSS_VssWss: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MAXSD_VsdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MAXSD_VsdWsd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MAXSD_VsdWsd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MAXPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MAXPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MAXPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CMPSS_VssWssIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CMPSS_VssWssIb: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CMPSS_VssWssIb: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CMPPS_VpsWpsIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CMPPS_VpsWpsIb: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CMPPS_VpsWpsIb: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CMPSD_VsdWsdIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CMPSD_VsdWsdIb: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CMPSD_VsdWsdIb: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CMPPD_VpdWpdIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CMPPD_VpdWpdIb: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("CMPPD_VpdWpdIb: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user