- check in Zwane's latest patch
This commit is contained in:
Bryce Denney
parent
03939e07de
commit
1c1cfc8e7c
@ -1,17 +1,11 @@
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----------------------------------------------------------------------
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Patch name: patch.tsc-zwane
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Author: Zwane Mwaikambo <zwane@linuxpower.ca>
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Date: Tue, 24 Sep 2002 19:44:51 -0400 (EDT)
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Date: Sat Dec 14 01:30:22 EST 2002
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Detailed description:
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This patch will seperate the TSC from the other timers, this helps a lot
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in speeding up SMP boot and allows TSC synch to be possible. Seperation is
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definitely necessary for writing to the TSC (e.g. via WRMSR)
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Minor bug fixes by Bryce:
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1. I had to move the definition of tsc into BX_CPU_C.
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2. remove duplicate case label BX_MSR_TSC in proc_ctrl.cc
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Revised TSC patch that calls tick at the right time
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Patch was created with:
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cvs diff -u
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@ -22,107 +16,137 @@ Instructions:
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Type "patch -p0 < THIS_PATCH_FILE".
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----------------------------------------------------------------------
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Index: pc_system.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/pc_system.cc,v
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retrieving revision 1.23
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diff -u -r1.23 pc_system.cc
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--- pc_system.cc 20 Sep 2002 15:35:44 -0000 1.23
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+++ pc_system.cc 28 Sep 2002 04:01:05 -0000
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@@ -370,6 +370,12 @@
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UNUSED(this_ptr);
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bx_pc_system.counter++;
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+
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+#if BX_CPU_LEVEL >= 5
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+ // This really belongs in CPU code...
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+ for (int i = 0; i < BX_SMP_PROCESSORS; i++)
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+ BX_CPU(i)->tsc++;
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+#endif
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}
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#if BX_DEBUGGER
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Index: cpu/cpu.h
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
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retrieving revision 1.84
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diff -u -r1.84 cpu.h
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--- cpu/cpu.h 27 Sep 2002 09:56:40 -0000 1.84
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+++ cpu/cpu.h 28 Sep 2002 04:01:09 -0000
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@@ -1390,6 +1390,7 @@
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retrieving revision 1.119
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diff -u -r1.119 cpu.h
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--- cpu/cpu.h 25 Nov 2002 21:58:47 -0000 1.119
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+++ cpu/cpu.h 14 Dec 2002 06:21:24 -0000
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@@ -1411,7 +1411,8 @@
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#endif
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#if BX_CPU_LEVEL >= 5
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bx_regs_msr_t msr;
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- bx_regs_msr_t msr;
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+ bx_regs_msr_t msr;
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+ Bit64u tsc;
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#endif
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i387_t the_i387;
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Index: cpu/init.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/init.cc,v
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retrieving revision 1.32
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diff -u -r1.32 init.cc
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--- cpu/init.cc 22 Sep 2002 18:22:24 -0000 1.32
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+++ cpu/init.cc 28 Sep 2002 04:01:10 -0000
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@@ -497,7 +497,9 @@
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#if BX_CPU_LEVEL >= 4
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BX_CPU_THIS_PTR clear_AC ();
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#endif
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-
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+#if BX_CPU_LEVEL >= 5
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+ BX_CPU_THIS_PTR tsc = 0;
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+#endif
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BX_CPU_THIS_PTR inhibit_mask = 0;
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BX_CPU_THIS_PTR debug_trap = 0;
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Index: cpu/proc_ctrl.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/proc_ctrl.cc,v
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retrieving revision 1.51
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diff -u -r1.51 proc_ctrl.cc
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--- cpu/proc_ctrl.cc 25 Sep 2002 14:09:08 -0000 1.51
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+++ cpu/proc_ctrl.cc 28 Sep 2002 04:01:13 -0000
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@@ -1652,9 +1652,11 @@
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Boolean cpl = CPL;
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retrieving revision 1.63
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diff -u -r1.63 proc_ctrl.cc
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--- cpu/proc_ctrl.cc 13 Nov 2002 21:00:04 -0000 1.63
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+++ cpu/proc_ctrl.cc 14 Dec 2002 06:21:27 -0000
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@@ -1682,9 +1682,9 @@
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bx_bool cpl = CPL;
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if ((tsd==0) || (tsd==1 && cpl==0)) {
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// return ticks
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- Bit64u ticks = bx_pc_system.time_ticks ();
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- RAX = (Bit32u) (ticks & 0xffffffff);
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- RDX = (Bit32u) ((ticks >> 32) & 0xffffffff);
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+ Bit64u ticks = BX_CPU_THIS_PTR tsc;
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+ EAX = (Bit32u) (ticks & 0xffffffff);
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+ EDX = (Bit32u) ((ticks >> 32) & 0xffffffff);
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+ EDX = (Bit32u) (ticks >> 32);
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+
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RAX = (Bit32u) (ticks & 0xffffffff);
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- RDX = (Bit32u) ((ticks >> 32) & 0xffffffff);
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+ RDX = (Bit32u) ticks >> 32;
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//BX_INFO(("RDTSC: returning EDX:EAX = %08x:%08x", EDX, EAX));
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} else {
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// not allowed to use RDTSC!
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@@ -1812,7 +1814,6 @@
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/* The following registers are defined for Pentium only */
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case BX_MSR_P5_MC_ADDR:
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case BX_MSR_MC_TYPE:
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- case BX_MSR_TSC:
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case BX_MSR_CESR:
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/* TODO */
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return;
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@@ -1820,7 +1821,6 @@
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/* These are noops on i686... */
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case BX_MSR_P5_MC_ADDR:
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case BX_MSR_MC_TYPE:
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- case BX_MSR_TSC:
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/* do nothing */
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return;
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@@ -1720,10 +1720,6 @@
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/* TODO */
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return;
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@@ -1830,6 +1830,12 @@
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case BX_MSR_CTR1:
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goto do_exception;
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#endif /* BX_CPU_LEVEL == 5 */
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- case BX_MSR_TSC:
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- RDTSC(i);
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- return;
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-
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case BX_MSR_CESR:
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/* TODO */
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return;
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@@ -1734,10 +1730,6 @@
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/* do nothing */
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return;
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- case BX_MSR_TSC:
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- RDTSC(i);
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- return;
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-
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/* ... And these cause an exception on i686 */
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case BX_MSR_CESR:
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case BX_MSR_CTR0:
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@@ -1745,6 +1737,10 @@
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goto do_exception;
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#endif /* BX_CPU_LEVEL == 5 */
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+ case BX_MSR_TSC:
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+ RDTSC(i);
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+ return;
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+
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+ case BX_MSR_TSC:
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+ /* we ignore the high 32bits */
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+ BX_CPU_THIS_PTR tsc = (Bit64u)EAX;
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+ BX_INFO(("WRMSR: wrote %08x:%08x to MSR_TSC\n", 0, EAX));
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+ return;
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/* MSR_APICBASE
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0:7 Reserved
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8 This is set if its the BSP
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@@ -1842,7 +1838,6 @@
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/* The following registers are defined for Pentium only */
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case BX_MSR_P5_MC_ADDR:
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case BX_MSR_MC_TYPE:
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- case BX_MSR_TSC:
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case BX_MSR_CESR:
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/* TODO */
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return;
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@@ -1850,7 +1845,6 @@
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/* These are noops on i686... */
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case BX_MSR_P5_MC_ADDR:
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case BX_MSR_MC_TYPE:
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- case BX_MSR_TSC:
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/* do nothing */
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return;
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/* MSR_APICBASE
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0:7 Reserved
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@@ -1860,6 +1854,12 @@
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case BX_MSR_CTR1:
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goto do_exception;
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#endif /* BX_CPU_LEVEL == 5 */
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+
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+ case BX_MSR_TSC:
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+ /* we ignore the high 32bits */
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+ BX_CPU_THIS_PTR tsc = (Bit64u)EAX;
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+ BX_INFO(("WRMSR: wrote %08x:%08x to MSR_TSC\n", 0, EAX));
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+ return;
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/* MSR_APICBASE
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0:7 Reserved
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Index: pc_system.h
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===================================================================
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RCS file: /cvsroot/bochs/bochs/pc_system.h,v
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retrieving revision 1.22
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diff -u -r1.22 pc_system.h
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--- pc_system.h 25 Oct 2002 11:44:33 -0000 1.22
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+++ pc_system.h 14 Dec 2002 06:21:28 -0000
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@@ -27,7 +27,7 @@
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-#define BX_MAX_TIMERS (15+BX_SMP_PROCESSORS)
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+#define BX_MAX_TIMERS (128+BX_SMP_PROCESSORS)
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#define BX_NULL_TIMER_HANDLE 10000
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@@ -113,6 +113,9 @@
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if (--bx_pc_system.currCountdown == 0) {
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bx_pc_system.countdownEvent();
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}
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+ for (int i = 0; i < BX_SMP_PROCESSORS; i++)
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+ BX_CPU(i)->tsc++;
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+
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}
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static BX_CPP_INLINE void tickn(Bit64u n) {
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#if BX_SHOW_IPS
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@@ -130,6 +133,9 @@
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// 'n' is not (or no longer) >= the countdown size. We can just decrement
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// the remaining requested ticks and continue.
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bx_pc_system.currCountdown -= Bit32u(n);
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+ for (int i = 0; i < BX_SMP_PROCESSORS; i++)
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+ BX_CPU(i)->tsc+=n;
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+
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}
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int register_timer_ticks(void* this_ptr, bx_timer_handler_t, Bit64u ticks,
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