- replaced old style i/o and irq register mechanism by the new one for pci devices
This commit is contained in:
Volker Ruppert
parent
79b1cfdc1c
commit
1ae1930be2
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pcipnic.cc,v 1.6 2004-06-29 19:24:34 vruppert Exp $
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// $Id: pcipnic.cc,v 1.7 2004-07-13 17:45:34 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2003 Fen Systems Ltd.
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@ -31,6 +31,8 @@
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bx_pcipnic_c* thePNICDevice = NULL;
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const Bit8u pnic_iomask[16] = {2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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int
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libpcipnic_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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@ -66,33 +68,14 @@ bx_pcipnic_c::init(void)
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if (!bx_options.pnic.Oenabled->get()) return;
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Bit16u base_ioaddr = bx_options.pnic.Oioaddr->get();
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Bit8u irq = bx_options.pnic.Oirq->get();
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memcpy ( BX_PNIC_THIS s.macaddr, bx_options.pnic.Omacaddr->getptr(),
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sizeof( BX_PNIC_THIS s.macaddr ) );
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DEV_register_irq(irq, "PNIC");
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BX_PNIC_THIS s.irq = irq;
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// Call our timer routine every 1mS (1,000uS)
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// Continuous and active
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/* BX_PNIC_THIS s.timer_index =
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bx_pc_system.register_timer(this, pnic_timer_handler, 1000, 1,1, "pnic.timer"); */
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for ( unsigned addr = base_ioaddr;
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addr <= (unsigned)( base_ioaddr + PNIC_MAX_REG );
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addr++ ) {
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BX_DEBUG(("register read/write: 0x%04x", addr));
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DEV_register_ioread_handler(this, read_handler, addr, "PNIC", 7);
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DEV_register_iowrite_handler(this, write_handler, addr, "PNIC", 7);
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}
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BX_PNIC_THIS s.base_ioaddr = base_ioaddr;
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Bit8u devfunc = 0x00;
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BX_PNIC_THIS s.devfunc = 0x00;
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DEV_register_pci_handlers(this,
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pci_read_handler,
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pci_write_handler,
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&devfunc, BX_PLUGIN_PCIPNIC,
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&BX_PNIC_THIS s.devfunc, BX_PLUGIN_PCIPNIC,
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"Experimental PCI Pseudo NIC");
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for (unsigned i=0; i<256; i++) {
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@ -149,6 +132,11 @@ bx_pcipnic_c::init(void)
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BX_PANIC(("could not locate null module"));
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}
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BX_PNIC_THIS s.base_ioaddr = 0;
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Bit16u base_ioaddr = bx_options.pnic.Oioaddr->get();
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Bit8u irq = bx_options.pnic.Oirq->get();
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BX_INFO( ( "pnic at 0x%04x-0x%04x irq %d",
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base_ioaddr, base_ioaddr + PNIC_MAX_REG, irq ) );
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}
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@ -179,7 +167,7 @@ bx_pcipnic_c::reset(unsigned type)
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{ 0x21, ( bx_options.pnic.Oioaddr->get() >> 8) },
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{ 0x22, 0x00 }, { 0x23, 0x00 },
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{ 0x3c, bx_options.pnic.Oirq->get() }, // IRQ
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{ 0x3d, 0x04 }, // INT
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{ 0x3d, BX_PCI_INTA }, // INT
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{ 0x6a, 0x01 }, // PNIC clock
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{ 0xc1, 0x20 } // PIRQ enable
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@ -197,8 +185,20 @@ bx_pcipnic_c::reset(unsigned type)
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BX_PNIC_THIS s.recvQueueLength = 0;
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BX_PNIC_THIS s.irqEnabled = 0;
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// This should be done by the PCI BIOS
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DEV_pci_set_base_io(BX_PNIC_THIS_PTR, read_handler, write_handler,
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&BX_PNIC_THIS s.base_ioaddr,
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&BX_PNIC_THIS s.pci_conf[0x20],
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16, &pnic_iomask[0], "PNIC");
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DEV_pci_init_irq(BX_PNIC_THIS s.devfunc, BX_PNIC_THIS s.pci_conf[0x3d], bx_options.pnic.Oirq->get());
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// Deassert IRQ
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DEV_pic_lower_irq ( BX_PNIC_THIS s.irq );
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set_irq_level(0);
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}
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void
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bx_pcipnic_c::set_irq_level(bx_bool level)
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{
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DEV_pci_set_irq(BX_PNIC_THIS s.devfunc, BX_PNIC_THIS s.pci_conf[0x3d], level);
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}
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@ -222,7 +222,7 @@ bx_pcipnic_c::read(Bit32u address, unsigned io_len)
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UNUSED(this_ptr);
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#endif // !BX_USE_PCIPNIC_SMF
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Bit32u val = 0x0;
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Bit8u offset,port;
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Bit8u offset;
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BX_DEBUG(("register read from address 0x%04x - ", (unsigned) address));
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@ -283,7 +283,7 @@ bx_pcipnic_c::write(Bit32u address, Bit32u value, unsigned io_len)
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCIPNIC_SMF
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Bit8u offset,port;
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Bit8u offset;
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BX_DEBUG(("register write to address 0x%04x - ", (unsigned) address));
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@ -432,61 +432,51 @@ bx_pcipnic_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
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UNUSED(this_ptr);
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#endif // !BX_USE_PCIPNIC_SMF
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if (io_len > 4 || io_len == 0) {
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BX_ERROR(("Experimental PNIC PCI write register 0x%02x, len=%u !",
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(unsigned) address, (unsigned) io_len));
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Bit8u value8, oldval;
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bx_bool baseaddr_change = 0;
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if (((address >= 0x10) && (address < 0x20)) ||
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((address > 0x23) && (address < 0x34)))
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return;
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}
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// This odd code is to display only what bytes actually were written.
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char szTmp[9];
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char szTmp2[3];
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szTmp[0] = '\0';
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szTmp2[0] = '\0';
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for (unsigned i=0; i<io_len; i++) {
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const Bit8u value8 = (value >> (i*8)) & 0xFF;
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switch (address+i) {
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case 0x20: // Base address
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BX_PNIC_THIS s.pci_conf[address+i] = (value8 & 0xe0) | 0x01;
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sprintf(szTmp2, "%02x", (value8 & 0xe0) | 0x01);
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break;
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case 0x10: // Reserved
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case 0x11: //
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case 0x12: //
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case 0x13: //
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case 0x14: //
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case 0x15: //
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case 0x16: //
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case 0x17: //
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case 0x18: //
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case 0x19: //
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case 0x1a: //
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case 0x1b: //
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case 0x1c: //
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case 0x1d: //
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case 0x1e: //
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case 0x1f: //
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case 0x22: // Always 0
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case 0x23: //
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case 0x24: // Reserved
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case 0x25: //
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case 0x26: //
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case 0x27: //
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case 0x30: // Oh, no, you're not writing to rom_base!
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case 0x31: //
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case 0x32: //
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case 0x33: //
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case 0x3d: //
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case 0x05: // disallowing write to command hi-byte
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case 0x06: // disallowing write to status lo-byte (is that expected?)
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strcpy(szTmp2, "..");
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break;
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default:
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BX_PNIC_THIS s.pci_conf[address+i] = value8;
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sprintf(szTmp2, "%02x", value8);
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if (io_len <= 4) {
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for (unsigned i=0; i<io_len; i++) {
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value8 = (value >> (i*8)) & 0xFF;
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oldval = BX_PNIC_THIS s.pci_conf[address+i];
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switch (address+i) {
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case 0x3d: //
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case 0x05: // disallowing write to command hi-byte
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case 0x06: // disallowing write to status lo-byte (is that expected?)
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strcpy(szTmp2, "..");
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break;
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case 0x3c:
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if (value8 != oldval) {
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BX_INFO(("new irq line = %d", value8));
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BX_PNIC_THIS s.pci_conf[address+i] = value8;
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}
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break;
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case 0x20:
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case 0x21:
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baseaddr_change = (value8 != oldval);
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default:
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BX_PNIC_THIS s.pci_conf[address+i] = value8;
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sprintf(szTmp2, "%02x", value8);
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}
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strrev(szTmp2);
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strcat(szTmp, szTmp2);
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}
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if (baseaddr_change) {
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DEV_pci_set_base_io(BX_PNIC_THIS_PTR, read_handler, write_handler,
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&BX_PNIC_THIS s.base_ioaddr,
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&BX_PNIC_THIS s.pci_conf[0x20],
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16, &pnic_iomask[0], "PNIC");
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BX_INFO(("new base address: 0x%04x", BX_PNIC_THIS s.base_ioaddr));
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}
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strrev(szTmp2);
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strcat(szTmp, szTmp2);
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}
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strrev(szTmp);
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BX_DEBUG(("Experimental PNIC PCI write register 0x%02x value 0x%s", address, szTmp));
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@ -551,7 +541,7 @@ bx_pcipnic_c::exec_command(void)
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BX_PNIC_THIS s.recvQueueLength --;
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}
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if ( ! BX_PNIC_THIS s.recvQueueLength ) {
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DEV_pic_lower_irq ( BX_PNIC_THIS s.irq );
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set_irq_level(0);
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}
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status = PNIC_STATUS_OK;
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break;
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@ -571,15 +561,15 @@ bx_pcipnic_c::exec_command(void)
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enabled = *((Bit8u*)data);
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BX_PNIC_THIS s.irqEnabled = enabled;
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if ( enabled && BX_PNIC_THIS s.recvQueueLength ) {
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DEV_pic_raise_irq ( BX_PNIC_THIS s.irq );
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set_irq_level(1);
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} else {
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DEV_pic_lower_irq ( BX_PNIC_THIS s.irq );
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set_irq_level(0);
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}
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status = PNIC_STATUS_OK;
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break;
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case PNIC_CMD_FORCE_IRQ :
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DEV_pic_raise_irq ( BX_PNIC_THIS s.irq );
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set_irq_level(1);
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status = PNIC_STATUS_OK;
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break;
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@ -640,7 +630,7 @@ bx_pcipnic_c::rx_frame(const void *buf, unsigned io_len)
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// Generate interrupt if enabled
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if ( BX_PNIC_THIS s.irqEnabled ) {
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DEV_pic_raise_irq ( BX_PNIC_THIS s.irq );
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set_irq_level(1);
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}
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pcipnic.h,v 1.2 2004-03-26 03:22:46 mcb30 Exp $
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// $Id: pcipnic.h,v 1.3 2004-07-13 17:45:34 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2003 Fen Systems Ltd.
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@ -24,9 +24,11 @@
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#if BX_USE_PCIPNIC_SMF
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# define BX_PNIC_SMF static
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# define BX_PNIC_THIS thePNICDevice->
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# define BX_PNIC_THIS_PTR thePNICDevice
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#else
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# define BX_PNIC_SMF
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# define BX_PNIC_THIS this->
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# define BX_PNIC_THIS_PTR this
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#endif
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#define PNIC_DATA_SIZE 4096
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@ -34,8 +36,7 @@
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typedef struct {
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Bit16u base_ioaddr;
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Bit8u irq;
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Bit32u base_ioaddr;
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Bit8u macaddr[6];
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Bit8u irqEnabled;
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@ -50,6 +51,7 @@ typedef struct {
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Bit8u recvRing[PNIC_RECV_RINGS][PNIC_DATA_SIZE]; // Receive buffer
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Bit16u recvRingLength[PNIC_RECV_RINGS];
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Bit8u devfunc;
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Bit8u pci_conf[256];
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} bx_pnic_t;
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@ -67,6 +69,8 @@ private:
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bx_pnic_t s;
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static void set_irq_level(bx_bool level);
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static void pnic_timer_handler(void *);
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void pnic_timer(void);
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