Small cleanup in he APIC code, removed unused methods
This commit is contained in:
Stanislav Shwartsman
parent
719eb78a25
commit
1aa7ae677d
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: apic.cc,v 1.94 2006-06-20 16:51:03 sshwarts Exp $
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// $Id: apic.cc,v 1.95 2006-10-02 21:49:49 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -36,6 +36,9 @@
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#define APIC_BROADCAST_PHYSICAL_DESTINATION_MODE (APIC_MAX_ID)
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#define BX_LAPIC_FIRST_VECTOR 0x10
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#define BX_LAPIC_LAST_VECTOR 0xfe
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///////////// APIC BUS /////////////
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int apic_bus_deliver_interrupt(Bit8u vector, Bit8u dest, Bit8u delivery_mode, Bit8u dest_mode, bx_bool level, bx_bool trig_mode)
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@ -273,7 +276,7 @@ void bx_local_apic_c::init()
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log_dest = 0;
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task_priority = 0;
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for(i=0; i<BX_LOCAL_APIC_MAX_INTS; i++) {
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for(i=0; i<BX_LAPIC_MAX_INTS; i++) {
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irr[i] = isr[i] = tmr[i] = 0;
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}
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@ -643,7 +646,7 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
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int bx_local_apic_c::highest_priority_int(Bit8u *array)
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{
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for(int i=BX_APIC_LAST_VECTOR; i>=BX_APIC_FIRST_VECTOR; i--)
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for(int i=BX_LAPIC_LAST_VECTOR; i>=BX_LAPIC_FIRST_VECTOR; i--)
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if(array[i]) return i;
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return -1;
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@ -715,7 +718,7 @@ void bx_local_apic_c::trigger_irq(unsigned vector, unsigned trigger_mode, bx_boo
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{
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BX_DEBUG(("Local apic on %s: trigger interrupt vector=0x%x", cpu->name, vector));
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if(vector > BX_APIC_LAST_VECTOR || vector < BX_APIC_FIRST_VECTOR) {
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if(vector > BX_LAPIC_LAST_VECTOR || vector < BX_LAPIC_FIRST_VECTOR) {
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shadow_error_status |= APIC_ERR_RX_ILLEGAL_VEC;
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BX_INFO(("bogus vector %#x, ignoring ...", vector));
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return;
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@ -779,7 +782,7 @@ spurious:
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void bx_local_apic_c::print_status(void)
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{
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BX_INFO(("%s local apic: status is {:", cpu->name));
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for(int vec=0; vec<BX_LOCAL_APIC_MAX_INTS; vec++) {
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for(int vec=0; vec<BX_LAPIC_MAX_INTS; vec++) {
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if(irr[vec] || isr[vec]) {
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BX_INFO(("vec 0x%x: irr=%d, isr=%d", vec,(int)irr[vec],(int)isr[vec]));
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}
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@ -953,10 +956,10 @@ void bx_local_apic_c::register_state(bx_param_c *parent)
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BXRS_HEX_PARAM_SIMPLE(lapic, log_dest);
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BXRS_HEX_PARAM_SIMPLE(lapic, dest_format);
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bx_list_c *ISR = new bx_list_c(lapic, "isr", BX_LOCAL_APIC_MAX_INTS);
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bx_list_c *TMR = new bx_list_c(lapic, "tmr", BX_LOCAL_APIC_MAX_INTS);
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bx_list_c *IRR = new bx_list_c(lapic, "irr", BX_LOCAL_APIC_MAX_INTS);
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for (i=0; i<BX_LOCAL_APIC_MAX_INTS; i++) {
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bx_list_c *ISR = new bx_list_c(lapic, "isr", BX_LAPIC_MAX_INTS);
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bx_list_c *TMR = new bx_list_c(lapic, "tmr", BX_LAPIC_MAX_INTS);
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bx_list_c *IRR = new bx_list_c(lapic, "irr", BX_LAPIC_MAX_INTS);
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for (i=0; i<BX_LAPIC_MAX_INTS; i++) {
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sprintf(name, "0x%02x", i);
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new bx_shadow_num_c(ISR, name, &isr[i]);
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new bx_shadow_num_c(TMR, name, &tmr[i]);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: apic.h,v 1.33 2006-06-05 05:39:21 sshwarts Exp $
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// $Id: apic.h,v 1.34 2006-10-02 21:49:49 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -35,11 +35,6 @@
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#if BX_SUPPORT_APIC
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typedef enum {
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APIC_TYPE_IOAPIC,
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APIC_TYPE_LOCAL_APIC
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} bx_apic_type_t;
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#define APIC_LEVEL_TRIGGERED 1
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#define APIC_EDGE_TRIGGERED 0
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@ -63,7 +58,6 @@ public:
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virtual void read_aligned(bx_phy_address address, Bit32u *data) = 0;
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void write(bx_phy_address address, void *value, unsigned len);
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virtual void write_aligned(bx_phy_address address, Bit32u *data) = 0;
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virtual bx_apic_type_t get_type() = 0;
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};
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#ifdef BX_INCLUDE_LOCAL_APIC
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@ -77,12 +71,8 @@ public:
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#endif
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#define BX_LAPIC_BASE_ADDR 0xfee00000 // default Local APIC address
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#define BX_NUM_LOCAL_APICS BX_SMP_PROCESSORS
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#define BX_APIC_FIRST_VECTOR 0x10
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#define BX_APIC_LAST_VECTOR 0xfe
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#define BX_LOCAL_APIC_MAX_INTS 256
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#define BX_NUM_LOCAL_APICS BX_SMP_PROCESSORS
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#define BX_LAPIC_MAX_INTS 256
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class BOCHSAPI bx_local_apic_c : public bx_generic_apic_c
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{
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@ -96,15 +86,15 @@ class BOCHSAPI bx_local_apic_c : public bx_generic_apic_c
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// ISR=in-service register. When an IRR bit is cleared, the corresponding
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// bit in ISR is set.
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Bit8u isr[BX_LOCAL_APIC_MAX_INTS];
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Bit8u isr[BX_LAPIC_MAX_INTS];
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// TMR=trigger mode register. Cleared for edge-triggered interrupts
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// and set for level-triggered interrupts. If set, local APIC must send
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// EOI message to all other APICs.
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Bit8u tmr[BX_LOCAL_APIC_MAX_INTS];
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Bit8u tmr[BX_LAPIC_MAX_INTS];
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// IRR=interrupt request register. When an interrupt is triggered by
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// the I/O APIC or another processor, it sets a bit in irr. The bit is
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// cleared when the interrupt is acknowledged by the processor.
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Bit8u irr[BX_LOCAL_APIC_MAX_INTS];
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Bit8u irr[BX_LAPIC_MAX_INTS];
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#define APIC_ERR_ILLEGAL_ADDR 0x80
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#define APIC_ERR_RX_ILLEGAL_VEC 0x40
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@ -158,10 +148,9 @@ class BOCHSAPI bx_local_apic_c : public bx_generic_apic_c
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public:
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bx_bool INTR;
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bx_local_apic_c(BX_CPU_C *cpu);
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virtual ~bx_local_apic_c(void) { }
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virtual ~bx_local_apic_c() { }
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virtual void reset(void);
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virtual void init(void);
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BX_CPU_C *get_cpu() { return cpu; }
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void set_id(Bit8u newid); // redefine to set cpu->name
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virtual void write_aligned(bx_phy_address addr, Bit32u *data);
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virtual void read_aligned(bx_phy_address address, Bit32u *data);
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@ -179,7 +168,6 @@ public:
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void service_local_apic(void);
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void print_status(void);
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bx_bool match_logical_addr (Bit8u address);
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virtual bx_apic_type_t get_type(void) { return APIC_TYPE_LOCAL_APIC; }
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bx_bool deliver(Bit8u vector, Bit8u delivery_mode, Bit8u trig_mode);
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Bit8u get_tpr(void);
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void set_tpr(Bit8u tpr);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ioapic.h,v 1.22 2006-06-05 05:39:21 sshwarts Exp $
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// $Id: ioapic.h,v 1.23 2006-10-02 21:49:49 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -95,7 +95,6 @@ public:
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void set_irq_level(Bit8u int_in, bx_bool level);
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void receive_eoi(Bit8u vector);
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void service_ioapic(void);
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virtual bx_apic_type_t get_type() { return APIC_TYPE_IOAPIC; }
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#if BX_SUPPORT_SAVE_RESTORE
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virtual void register_state(void);
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#endif
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