From 1a6656ce91f951ef2e3427be1e18431562a7423c Mon Sep 17 00:00:00 2001 From: Stanislav Shwartsman Date: Thu, 4 Nov 2004 22:41:24 +0000 Subject: [PATCH] Fixed compilation warnings (g++, -Wall) Improve speed and precision of FPATAN FPU instruction --- bochs/cpu/apic.cc | 7 +++---- bochs/cpu/ctrl_xfer64.cc | 4 +--- bochs/cpu/exception.cc | 16 +++++----------- bochs/cpu/proc_ctrl.cc | 30 ++++++++++++++++-------------- bochs/cpu/stack64.cc | 3 +-- bochs/fpu/fpatan.cc | 26 ++++++++++++-------------- bochs/fpu/softfloat-macros.h | 4 ++-- bochs/fpu/softfloat.cc | 6 +----- bochs/iodev/cdrom.cc | 15 +++------------ 9 files changed, 44 insertions(+), 67 deletions(-) diff --git a/bochs/cpu/apic.cc b/bochs/cpu/apic.cc index 19b9e910b..fccf9be84 100644 --- a/bochs/cpu/apic.cc +++ b/bochs/cpu/apic.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: apic.cc,v 1.34 2004-10-16 19:34:16 sshwarts Exp $ +// $Id: apic.cc,v 1.35 2004-11-04 22:41:23 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// #define NEED_CPU_REG_SHORTCUTS 1 @@ -215,12 +215,11 @@ bx_bool bx_generic_apic_c::deliver (Bit8u dest, Bit8u dest_mode, Bit8u delivery_ // return false if we can't deliver for any reason, so that the caller // knows not to clear its IRR. Bit32u deliver_bitmask = get_delivery_bitmask (dest, dest_mode); - int lowest_priority = 0x100, lowest_mask = -1; // arbitrate by default int arbitrate = 1; int broadcast = (deliver_bitmask == BX_CPU_C::cpu_online_map); bx_bool once = false; - int bit, i; + int i; // mask must include ONLY local APICs, or we will have problems. if (!deliver_bitmask) { @@ -821,7 +820,7 @@ bx_bool bx_local_apic_c::match_logical_addr (Bit8u address) Bit32u bx_local_apic_c::get_delivery_bitmask (Bit8u dest, Bit8u dest_mode) { int dest_shorthand = (icr_low >> 18) & 3; - Bit32u mask; + Bit32u mask = 0; /* stop compiler warnings */ switch (dest_shorthand) { case 0: // no shorthand, use real destination value diff --git a/bochs/cpu/ctrl_xfer64.cc b/bochs/cpu/ctrl_xfer64.cc index 6e25fa966..5e8e9de0b 100644 --- a/bochs/cpu/ctrl_xfer64.cc +++ b/bochs/cpu/ctrl_xfer64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: ctrl_xfer64.cc,v 1.26 2004-10-29 21:15:48 sshwarts Exp $ +// $Id: ctrl_xfer64.cc,v 1.27 2004-11-04 22:41:23 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -377,8 +377,6 @@ done: void BX_CPU_C::IRET64(bxInstruction_c *i) { - Bit32u rip, ecs_raw, eflags; - invalidate_prefetch_q(); #if BX_DEBUGGER diff --git a/bochs/cpu/exception.cc b/bochs/cpu/exception.cc index a3d81c5c2..28a473818 100644 --- a/bochs/cpu/exception.cc +++ b/bochs/cpu/exception.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: exception.cc,v 1.43 2004-11-02 16:10:01 sshwarts Exp $ +// $Id: exception.cc,v 1.44 2004-11-04 22:41:23 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -92,8 +92,7 @@ BX_CPU_THIS_PTR save_esp = ESP; // long mode interrupt Bit64u idtindex; - Bit32u save_upper; - Bit32u dword1, dword2, dword3; + Bit32u dword1, dword2, dword3; bx_descriptor_t gate_descriptor, cs_descriptor; bx_selector_t cs_selector; @@ -206,11 +205,10 @@ BX_CPU_THIS_PTR save_esp = ESP; // INTERRUPT TO INNER PRIVILEGE: if ((cs_descriptor.u.segment.c_ed==0 && cs_descriptor.dpl 0)) { - Bit16u old_SS, old_CS; - Bit64u RSP_for_cpl_x, old_RIP, old_RSP; + Bit16u old_SS; + Bit64u RSP_for_cpl_x, old_RSP; bx_descriptor_t ss_descriptor; bx_selector_t ss_selector; - int bytes; int savemode; BX_DEBUG(("interrupt(): INTERRUPT TO INNER PRIVILEGE")); @@ -227,7 +225,6 @@ BX_CPU_THIS_PTR save_esp = ESP; parse_selector(0,&ss_selector); parse_descriptor(0,0,&ss_descriptor); - // 386 int/trap gate // new stack must have room for 40|48 bytes, else #SS(0) //if ( is_error_code ) @@ -235,7 +232,6 @@ BX_CPU_THIS_PTR save_esp = ESP; //else // bytes = 40; - old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value; old_RSP = RSP; @@ -295,11 +291,9 @@ BX_CPU_THIS_PTR save_esp = ESP; // INTERRUPT TO SAME PRIVILEGE LEVEL: if (cs_descriptor.u.segment.c_ed==1 || cs_descriptor.dpl==CPL ) { - Bit64u old_RSP; - BX_DEBUG(("int_trap_gate286(): INTERRUPT TO SAME PRIVILEGE")); - old_RSP = RSP; + Bit64u old_RSP = RSP; // align stack RSP = RSP & BX_CONST64(0xfffffffffffffff0); diff --git a/bochs/cpu/proc_ctrl.cc b/bochs/cpu/proc_ctrl.cc index c894d89e5..85d0a2e87 100644 --- a/bochs/cpu/proc_ctrl.cc +++ b/bochs/cpu/proc_ctrl.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: proc_ctrl.cc,v 1.85 2004-11-02 16:10:01 sshwarts Exp $ +// $Id: proc_ctrl.cc,v 1.86 2004-11-04 22:41:23 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -455,23 +455,29 @@ void BX_CPU_C::MOV_DqRq(bxInstruction_c *i) if ( (((val_64>>16) & 3)==2) || (((val_64>>20) & 3)==2) || (((val_64>>24) & 3)==2) || - (((val_64>>28) & 3)==2) ) { + (((val_64>>28) & 3)==2) ) + { // IO breakpoints (10b) are not yet supported. - BX_PANIC(("MOV_DqRq: write of %08x contains IO breakpoint", val_64)); + BX_PANIC(("MOV_DqRq: write of %08x:%08x contains IO breakpoint", + (Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF))); } if ( (((val_64>>18) & 3)==2) || (((val_64>>22) & 3)==2) || (((val_64>>26) & 3)==2) || - (((val_64>>30) & 3)==2) ) { + (((val_64>>30) & 3)==2) ) + { // LEN0..3 contains undefined length specifier (10b) - BX_PANIC(("MOV_DqRq: write of %08x contains undefined LENx", val_64)); + BX_PANIC(("MOV_DqRq: write of %08x:%08x contains undefined LENx", + (Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF))); } if ( ((((val_64>>16) & 3)==0) && (((val_64>>18) & 3)!=0)) || ((((val_64>>20) & 3)==0) && (((val_64>>22) & 3)!=0)) || ((((val_64>>24) & 3)==0) && (((val_64>>26) & 3)!=0)) || - ((((val_64>>28) & 3)==0) && (((val_64>>30) & 3)!=0)) ) { + ((((val_64>>28) & 3)==0) && (((val_64>>30) & 3)!=0)) ) + { // Instruction breakpoint with LENx not 00b (1-byte length) - BX_PANIC(("MOV_DqRq: write of %08x, R/W=00b LEN!=00b", val_64)); + BX_PANIC(("MOV_DqRq: write of %08x:%08x , R/W=00b LEN!=00b", + (Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF))); } // Pentium+: bits15,14,12 are hardwired to 0, rest are settable. @@ -835,13 +841,9 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i) // Protected mode: #GP(0) if attempt to write a 1 to // any reserved bit of CR4 - BX_INFO(("MOV_CqRq: ignoring write to CR4 of 0x%08x", val_64)); - if (val_64) { - BX_INFO(("MOV_CqRq: (CR4) write of 0x%08x not supported!", val_64)); - } - // Only allow writes of 0 to CR4 for now. - // Writes to bits in CR4 should not be 1s as CPUID - // returns not-supported for all of these features. + BX_INFO(("MOV_CqRq: write to CR4 of %08x:%08x", + (Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF))); + SetCR4(val_64); break; #if BX_SUPPORT_APIC diff --git a/bochs/cpu/stack64.cc b/bochs/cpu/stack64.cc index ebbfa67af..354e3a067 100644 --- a/bochs/cpu/stack64.cc +++ b/bochs/cpu/stack64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: stack64.cc,v 1.16 2004-11-02 16:10:02 sshwarts Exp $ +// $Id: stack64.cc,v 1.17 2004-11-04 22:41:23 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -236,7 +236,6 @@ BX_CPU_C::PUSH_Eq(bxInstruction_c *i) BX_CPU_C::ENTER64_IwIb(bxInstruction_c *i) { Bit64u frame_ptr64; - Bit16u frame_ptr16; Bit8u level; static Bit8u first_time = 1; diff --git a/bochs/fpu/fpatan.cc b/bochs/fpu/fpatan.cc index d70e9e141..07a23d08f 100755 --- a/bochs/fpu/fpatan.cc +++ b/bochs/fpu/fpatan.cc @@ -37,12 +37,13 @@ static const float128 float128_sqrt3 = packFloat128(BX_CONST64(0x3fffbb67ae8584ca), BX_CONST64(0xa73b25742d7078b8)); static const floatx80 floatx80_pi = packFloatx80(0, 0x4000, BX_CONST64(0xc90fdaa22168c235)); -static const floatx80 floatx80_pi2 = - packFloatx80(0, 0x3fff, BX_CONST64(0xc90fdaa22168c235)); -static const floatx80 floatx80_pi4 = - packFloatx80(0, 0x3ffe, BX_CONST64(0xc90fdaa22168c235)); -static const floatx80 floatx80_pi6 = - packFloatx80(0, 0x3ffe, BX_CONST64(0x860a91c16b9b2c23)); + +static const float128 float128_pi2 = + packFloat128(BX_CONST64(0x3fff921fb54442d1), BX_CONST64(0x8469898CC5170416)); +static const float128 float128_pi4 = + packFloat128(BX_CONST64(0x3ffe921fb54442d1), BX_CONST64(0x8469898CC5170416)); +static const float128 float128_pi6 = + packFloat128(BX_CONST64(0x3ffe0c152382d736), BX_CONST64(0x58465BB32E0F580F)); static float128 atan_arr[FPATAN_ARR_SIZE] = { @@ -235,12 +236,9 @@ return_PI_or_ZERO: } Bit32s xExp = extractFloat128Exp(x); - floatx80 result; - if (xExp <= EXP_BIAS-40) { - result = float128_to_floatx80(x, status); + if (xExp <= EXP_BIAS-40) goto approximation_completed; - } if (x.hi >= BX_CONST64(0x3ffe800000000000)) // 3/4 < x < 1 { @@ -269,12 +267,12 @@ return_PI_or_ZERO: } x = poly_atan(x, status); - result = float128_to_floatx80(x, status); - if (add_pi6) result = floatx80_add(result, floatx80_pi6, status); - if (add_pi4) result = floatx80_add(result, floatx80_pi4, status); + if (add_pi6) x = float128_add(x, float128_pi6, status); + if (add_pi4) x = float128_add(x, float128_pi4, status); approximation_completed: - if (swap) result = floatx80_sub(floatx80_pi2, result, status); + if (swap) x = float128_sub(float128_pi2, x, status); + floatx80 result = float128_to_floatx80(x, status); if (zSign) floatx80_chs(result); int rSign = extractFloatx80Sign(result); if (!bSign && rSign) diff --git a/bochs/fpu/softfloat-macros.h b/bochs/fpu/softfloat-macros.h index c3e1cb861..6663cc004 100755 --- a/bochs/fpu/softfloat-macros.h +++ b/bochs/fpu/softfloat-macros.h @@ -418,7 +418,7 @@ BX_CPP_INLINE void add192( ) { Bit64u z0, z1, z2; - int carry0, carry1; + unsigned carry0, carry1; z2 = a2 + b2; carry1 = (z2 < a2); @@ -454,7 +454,7 @@ BX_CPP_INLINE void sub192( ) { Bit64u z0, z1, z2; - int borrow0, borrow1; + unsigned borrow0, borrow1; z2 = a2 - b2; borrow1 = (a2 < b2); diff --git a/bochs/fpu/softfloat.cc b/bochs/fpu/softfloat.cc index d8b26f1b5..8d64ee4db 100755 --- a/bochs/fpu/softfloat.cc +++ b/bochs/fpu/softfloat.cc @@ -92,12 +92,9 @@ float64 int32_to_float64(Bit32s a) float32 int64_to_float32(Bit64s a, float_status_t &status) { - Bit64u absA; - Bit32u zSig; - if (a == 0) return 0; int zSign = (a < 0); - absA = zSign ? -a : a; + Bit64u absA = zSign ? -a : a; int shiftCount = countLeadingZeros64(absA) - 40; if (0 <= shiftCount) { return packFloat32(zSign, 0x95 - shiftCount, absA<=0; i-- ) { - BX_DEBUG(( "session %d ctl_adr %d tno %d point %d lba %d z %d p lba %d\n", (int)toc->trackdesc[i].session, (int)toc->trackdesc[i].ctrl_adr, @@ -1331,22 +1328,16 @@ cdrom_interface::capacity() MSF_TO_LBA(toc->trackdesc[i].p ))); if ( start_sector != -1 ) { - start_sector = MSF_TO_LBA(toc->trackdesc[i].p) - start_sector; break; - } - if (( toc->trackdesc[i].ctrl_adr >> 4) != 1 ) continue; + if ((toc->trackdesc[i].ctrl_adr >> 4) != 1) continue; if ( toc->trackdesc[i].ctrl_adr & 0x04 ) { - data_track = toc->trackdesc[i].point; - start_sector = MSF_TO_LBA(toc->trackdesc[i].p); - } - } free( toc );