Continued preparing Voodoo2 CMDFIFO support.
- Zero out voodoo device state in init(). - Added the CMDFIFO state to save/restore list. - Added CMDFIFO register handling in read/write functions. - Added new function cmdfifo_put(). - TODO: CMDFIFO thread.
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@ -207,6 +207,7 @@ void bx_voodoo_c::init(void)
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BX_VOODOO_THIS s.vdraw.gui_update_pending = 0;
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v = new voodoo_state;
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memset(v, 0, sizeof(voodoo_state));
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BX_VOODOO_THIS s.model = (Bit8u)SIM->get_param_enum("model", base)->get();
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if (BX_VOODOO_THIS s.model == VOODOO_2) {
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init_pci_conf(0x121a, 0x0002, 0x02, 0x038000, 0x00);
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@ -326,6 +327,18 @@ void bx_voodoo_c::register_state(void)
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new bx_shadow_num_c(fbi, "dady", &v->fbi.dady);
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new bx_shadow_num_c(fbi, "dzdy", &v->fbi.dzdy);
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new bx_shadow_num_c(fbi, "dwdy", &v->fbi.dwdy);
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bx_list_c *cmdfifo = new bx_list_c(fbi, "cmdfifo", "");
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for (i = 0; i < 2; i++) {
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sprintf(name, "%d", i);
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bx_list_c *num = new bx_list_c(cmdfifo, name, "");
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new bx_shadow_bool_c(num, "enable", &v->fbi.cmdfifo[i].enable, BASE_HEX);
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new bx_shadow_num_c(num, "base", &v->fbi.cmdfifo[i].base, BASE_HEX);
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new bx_shadow_num_c(num, "end", &v->fbi.cmdfifo[i].end, BASE_HEX);
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new bx_shadow_num_c(num, "rdptr", &v->fbi.cmdfifo[i].rdptr, BASE_HEX);
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new bx_shadow_num_c(num, "depth", &v->fbi.cmdfifo[i].depth);
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new bx_shadow_num_c(num, "amin", &v->fbi.cmdfifo[i].amin, BASE_HEX);
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new bx_shadow_num_c(num, "amax", &v->fbi.cmdfifo[i].amax, BASE_HEX);
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}
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bx_list_c *fogblend = new bx_list_c(fbi, "fogblend", "");
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for (i = 0; i < 64; i++) {
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sprintf(name, "%d", i);
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@ -1455,7 +1455,7 @@ struct _fifo_state
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typedef struct _cmdfifo_info cmdfifo_info;
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struct _cmdfifo_info
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{
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Bit8u enable; /* enabled? */
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bx_bool enable; /* enabled? */
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Bit8u count_holes; /* count holes? */
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Bit32u base; /* base address in framebuffer RAM */
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Bit32u end; /* end address in framebuffer RAM */
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@ -1303,6 +1303,14 @@ void dacdata_r(dac_state *d, Bit8u regnum)
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d->read_result = result;
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}
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void cmdfifo_put(Bit32u fbi_offset, Bit32u data)
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{
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BX_ERROR(("Writing to CMDFIFO has no effect yet: FBI offset=0x%08x, data=0x%08x",
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fbi_offset, data));
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*(Bit32u*)&v->fbi.ram[fbi_offset] = data;
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v->fbi.cmdfifo[0].depth++;
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}
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voodoo_reg reg;
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void register_w(Bit32u offset, Bit32u data)
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@ -1335,9 +1343,7 @@ void register_w(Bit32u offset, Bit32u data)
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BX_ERROR(("CMDFIFO-to-FIFO mode not supported yet"));
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} else if ((offset & 0x80000) > 0) {
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Bit32u fbi_offset = (v->fbi.cmdfifo[0].base + ((offset & 0xffff) << 2)) & v->fbi.mask;
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BX_ERROR(("Writing to CMDFIFO has no effect yet: FBI offset=0x%08x, data=0x%08x",
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fbi_offset, data));
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*(Bit32u*)&v->fbi.ram[fbi_offset] = data;
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cmdfifo_put(fbi_offset, data);
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return;
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} else {
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if (v->regaccess[regnum] & REGISTER_WRITETHRU) {
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@ -1744,6 +1750,9 @@ void register_w(Bit32u offset, Bit32u data)
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if (v->type <= VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(v->pci.init_enable))
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{
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if ((v->type == VOODOO_2) && (regnum == fbiInit7)) {
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v->fbi.cmdfifo[0].enable = FBIINIT7_CMDFIFO_ENABLE(data);
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}
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v->reg[regnum].u = data;
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recompute_video_memory(v);
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v->fbi.video_changed = 1;
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@ -1872,8 +1881,26 @@ void register_w(Bit32u offset, Bit32u data)
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v->fbi.cmdfifo[0].end = ((data >> 16) & 0x3ff) << 12;
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break;
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case cmdFifoRdPtr:
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v->fbi.cmdfifo[0].rdptr = data;
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break;
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case cmdFifoDepth:
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v->fbi.cmdfifo[0].depth = data & 0xffff;
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break;
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case cmdFifoAMin:
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v->fbi.cmdfifo[0].amin = data;
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break;
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case cmdFifoAMax:
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v->fbi.cmdfifo[0].amax = data;
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break;
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case intrCtrl:
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case userIntrCMD:
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case bltSize:
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case bltCommand:
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BX_ERROR(("Writing to register %s not supported yet", v->regnames[regnum]));
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break;
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@ -2504,6 +2531,22 @@ Bit32u register_r(Bit32u offset)
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case cmdFifoBaseAddr:
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result = (v->fbi.cmdfifo[0].base >> 12) | ((v->fbi.cmdfifo[0].end >> 12) << 16);
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break;
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case cmdFifoRdPtr:
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result = v->fbi.cmdfifo[0].rdptr;
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break;
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case cmdFifoDepth:
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result = v->fbi.cmdfifo[0].depth;
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break;
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case cmdFifoAMin:
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result = v->fbi.cmdfifo[0].amin;
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break;
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case cmdFifoAMax:
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result = v->fbi.cmdfifo[0].amax;
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break;
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}
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return result;
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