mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- added pci_base_address array to bx_pci_device_stub_c and use it in most of the PCI devices instead

Browse Source 
of several base address variables (ne2k still uses base_address for both ISA and PCI)
This commit is contained in:
Volker Ruppert 2011-06-25 12:43:27 +00:00
parent beafa7c88b
commit 16bd4c6401
15 changed files with 60 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
bochs/iodev/es1370.cc
View File

@ -128,7 +128,7 @@ void bx_es1370_c::init(void)
for (unsigned i=0; i<256; i++) {
BX_ES1370_THIS pci_conf[i] = 0x0;
}
BX_ES1370_THIS s.base_ioaddr = 0;
BX_ES1370_THIS pci_base_address[0] = 0;
DEV_sound_init_module("default", &BX_ES1370_THIS soundmod, BX_ES1370_THIS_PTR);
BX_ES1370_THIS s.dac_outputinit = 0;
@ -224,10 +224,10 @@ void bx_es1370_c::register_state(void)
void bx_es1370_c::after_restore_state(void)
{
if (DEV_pci_set_base_io(BX_ES1370_THIS_PTR, read_handler, write_handler,
&BX_ES1370_THIS s.base_ioaddr,
&BX_ES1370_THIS pci_base_address[0],
&BX_ES1370_THIS pci_conf[0x10],
64, &es1370_iomask[0], "ES1370")) {
BX_INFO(("new base address: 0x%04x", BX_ES1370_THIS s.base_ioaddr));
BX_INFO(("new base address: 0x%04x", BX_ES1370_THIS pci_base_address[0]));
}
BX_ES1370_THIS check_lower_irq(BX_ES1370_THIS s.sctl);
BX_ES1370_THIS s.dac_outputinit = 0;
@ -257,7 +257,7 @@ Bit32u bx_es1370_c::read(Bit32u address, unsigned io_len)
BX_DEBUG(("register read from address 0x%04x - ", address));
offset = address - BX_ES1370_THIS s.base_ioaddr;
offset = address - BX_ES1370_THIS pci_base_address[0];
if (offset >= 0x30) {
offset |= (BX_ES1370_THIS s.mempage << 8);
}
@ -349,7 +349,7 @@ void bx_es1370_c::write(Bit32u address, Bit32u value, unsigned io_len)
BX_DEBUG(("register write to address 0x%04x - value = 0x%08x", address, value));
offset = address - BX_ES1370_THIS s.base_ioaddr;
offset = address - BX_ES1370_THIS pci_base_address[0];
if (offset >= 0x30) {
offset |= (BX_ES1370_THIS s.mempage << 8);
}
@ -715,10 +715,10 @@ void bx_es1370_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len
}
if (baseaddr_change) {
if (DEV_pci_set_base_io(BX_ES1370_THIS_PTR, read_handler, write_handler,
&BX_ES1370_THIS s.base_ioaddr,
&BX_ES1370_THIS pci_base_address[0],
&BX_ES1370_THIS pci_conf[0x10],
64, &es1370_iomask[0], "ES1370")) {
BX_INFO(("new base address: 0x%04x", BX_ES1370_THIS s.base_ioaddr));
BX_INFO(("new base address: 0x%04x", BX_ES1370_THIS pci_base_address[0]));
}
}

1
bochs/iodev/es1370.h
View File

@ -54,7 +54,6 @@ typedef struct {
int dac_nr_active;
Bit16u dac_packet_size[2];
Bit32u base_ioaddr;
Bit8u devfunc;
} bx_es1370_t;

1
bochs/iodev/iodev.h
View File

@ -98,6 +98,7 @@ public:
protected:
Bit8u pci_conf[256];
Bit32u pci_base_address[6];
};
//////////////////////////////////////////////////////////////////////

16
bochs/iodev/pci_ide.cc
View File

@ -104,7 +104,7 @@ void bx_pci_ide_c::init(void)
BX_PIDE_THIS pci_conf[0x0b] = 0x01;
BX_PIDE_THIS pci_conf[0x0e] = 0x00;
BX_PIDE_THIS pci_conf[0x20] = 0x01;
BX_PIDE_THIS s.bmdma_addr = 0;
BX_PIDE_THIS pci_base_address[4] = 0;
}
void bx_pci_ide_c::reset(unsigned type)
@ -162,10 +162,10 @@ void bx_pci_ide_c::register_state(void)
void bx_pci_ide_c::after_restore_state(void)
{
if (DEV_pci_set_base_io(BX_PIDE_THIS_PTR, read_handler, write_handler,
&BX_PIDE_THIS s.bmdma_addr, &BX_PIDE_THIS pci_conf[0x20],
&BX_PIDE_THIS pci_base_address[4], &BX_PIDE_THIS pci_conf[0x20],
16, &bmdma_iomask[0], "PIIX3 PCI IDE controller"))
{
BX_INFO(("new BM-DMA address: 0x%04x", BX_PIDE_THIS s.bmdma_addr));
BX_INFO(("new BM-DMA address: 0x%04x", BX_PIDE_THIS pci_base_address[4]));
}
}
@ -214,7 +214,7 @@ void bx_pci_ide_c::param_restore(bx_param_c *param, Bit64s val)
bx_bool bx_pci_ide_c::bmdma_present(void)
{
return (BX_PIDE_THIS s.bmdma_addr > 0);
return (BX_PIDE_THIS pci_base_address[4] > 0);
}
void bx_pci_ide_c::bmdma_set_irq(Bit8u channel)
@ -339,7 +339,7 @@ Bit32u bx_pci_ide_c::read(Bit32u address, unsigned io_len)
Bit8u offset, channel;
Bit32u value = 0xffffffff;
offset = address - BX_PIDE_THIS s.bmdma_addr;
offset = address - BX_PIDE_THIS pci_base_address[4];
channel = (offset >> 3);
offset &= 0x07;
switch (offset) {
@ -380,7 +380,7 @@ void bx_pci_ide_c::write(Bit32u address, Bit32u value, unsigned io_len)
#endif // !BX_USE_PIDE_SMF
Bit8u offset, channel;
offset = address - BX_PIDE_THIS s.bmdma_addr;
offset = address - BX_PIDE_THIS pci_base_address[4];
channel = (offset >> 3);
offset &= 0x07;
switch (offset) {
@ -458,9 +458,9 @@ void bx_pci_ide_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_le
}
if (bmdma_change) {
if (DEV_pci_set_base_io(BX_PIDE_THIS_PTR, read_handler, write_handler,
&BX_PIDE_THIS s.bmdma_addr, &BX_PIDE_THIS pci_conf[0x20],
&BX_PIDE_THIS pci_base_address[4], &BX_PIDE_THIS pci_conf[0x20],
16, &bmdma_iomask[0], "PIIX3 PCI IDE controller")) {
BX_INFO(("new BM-DMA address: 0x%04x", BX_PIDE_THIS s.bmdma_addr));
BX_INFO(("new BM-DMA address: 0x%04x", BX_PIDE_THIS pci_base_address[4]));
}
}
}

1
bochs/iodev/pci_ide.h
View File

@ -57,7 +57,6 @@ public:
private:
struct {
Bit32u bmdma_addr;
struct {
bx_bool cmd_ssbm;
bx_bool cmd_rwcon;

14
bochs/iodev/pcipnic.cc
View File

@ -100,7 +100,7 @@ void bx_pcipnic_c::init(void)
BX_PANIC(("could not locate null module"));
}
BX_PNIC_THIS s.base_ioaddr = 0;
BX_PNIC_THIS pci_base_address[4] = 0;
BX_INFO(("PCI Pseudo NIC initialized - I/O base and IRQ assigned by PCI BIOS"));
}
@ -177,10 +177,10 @@ void bx_pcipnic_c::register_state(void)
void bx_pcipnic_c::after_restore_state(void)
{
if (DEV_pci_set_base_io(BX_PNIC_THIS_PTR, read_handler, write_handler,
&BX_PNIC_THIS s.base_ioaddr,
&BX_PNIC_THIS pci_base_address[4],
&BX_PNIC_THIS pci_conf[0x10],
16, &pnic_iomask[0], "PNIC")) {
BX_INFO(("new base address: 0x%04x", BX_PNIC_THIS s.base_ioaddr));
BX_INFO(("new base address: 0x%04x", BX_PNIC_THIS pci_base_address[4]));
}
}
@ -209,7 +209,7 @@ Bit32u bx_pcipnic_c::read(Bit32u address, unsigned io_len)
BX_DEBUG(("register read from address 0x%04x - ", (unsigned) address));
offset = address - BX_PNIC_THIS s.base_ioaddr;
offset = address - BX_PNIC_THIS pci_base_address[4];
switch (offset) {
case PNIC_REG_STAT:
@ -258,7 +258,7 @@ void bx_pcipnic_c::write(Bit32u address, Bit32u value, unsigned io_len)
BX_DEBUG(("register write to address 0x%04x - ", (unsigned) address));
offset = address - BX_PNIC_THIS s.base_ioaddr;
offset = address - BX_PNIC_THIS pci_base_address[4];
switch (offset) {
case PNIC_REG_CMD:
@ -356,10 +356,10 @@ void bx_pcipnic_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_le
}
if (baseaddr_change) {
if (DEV_pci_set_base_io(BX_PNIC_THIS_PTR, read_handler, write_handler,
&BX_PNIC_THIS s.base_ioaddr,
&BX_PNIC_THIS pci_base_address[4],
&BX_PNIC_THIS pci_conf[0x20],
16, &pnic_iomask[0], "PNIC")) {
BX_INFO(("new base address: 0x%04x", BX_PNIC_THIS s.base_ioaddr));
BX_INFO(("new base address: 0x%04x", BX_PNIC_THIS pci_base_address[4]));
}
}

1
bochs/iodev/pcipnic.h
View File

@ -39,7 +39,6 @@
typedef struct {
Bit32u base_ioaddr;
Bit8u macaddr[6];
Bit8u irqEnabled;

10
bochs/iodev/pcivga.cc
View File

@ -100,7 +100,7 @@ void bx_pcivga_c::init(void)
BX_PCIVGA_THIS vbe_present = !strcmp(SIM->get_param_string(BXPN_VGA_EXTENSION)->getptr(), "vbe");;
if (BX_PCIVGA_THIS vbe_present) {
WriteHostDWordToLittleEndian(&BX_PCIVGA_THIS pci_conf[0x10], 0x08);
BX_PCIVGA_THIS base_address = 0;
BX_PCIVGA_THIS pci_base_address[0] = 0;
}
}
@ -127,9 +127,9 @@ void bx_pcivga_c::register_state(void)
void bx_pcivga_c::after_restore_state(void)
{
if (BX_PCIVGA_THIS vbe_present) {
if (DEV_vbe_set_base_addr(&BX_PCIVGA_THIS base_address,
if (DEV_vbe_set_base_addr(&BX_PCIVGA_THIS pci_base_address[0],
&BX_PCIVGA_THIS pci_conf[0x10])) {
BX_INFO(("new base address: 0x%08x", BX_PCIVGA_THIS base_address));
BX_INFO(("new base address: 0x%08x", BX_PCIVGA_THIS pci_base_address[0]));
}
}
}
@ -192,9 +192,9 @@ void bx_pcivga_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len
}
if (baseaddr_change) {
if (DEV_vbe_set_base_addr(&BX_PCIVGA_THIS base_address,
if (DEV_vbe_set_base_addr(&BX_PCIVGA_THIS pci_base_address[0],
&BX_PCIVGA_THIS pci_conf[0x10])) {
BX_INFO(("new base address: 0x%08x", BX_PCIVGA_THIS base_address));
BX_INFO(("new base address: 0x%08x", BX_PCIVGA_THIS pci_base_address[0]));
}
}
}

1
bochs/iodev/pcivga.h
View File

@ -40,7 +40,6 @@ public:
virtual void pci_write_handler(Bit8u address, Bit32u value, unsigned io_len);
private:
Bit32u base_address;
bx_bool vbe_present;
};

36
bochs/iodev/svga_cirrus.cc
View File

@ -437,17 +437,17 @@ void bx_svga_cirrus_c::after_restore_state(void)
if (BX_CIRRUS_THIS pci_enabled) {
if (DEV_pci_set_base_mem(BX_CIRRUS_THIS_PTR, cirrus_mem_read_handler,
cirrus_mem_write_handler,
&BX_CIRRUS_THIS pci_memaddr,
&BX_CIRRUS_THIS pci_base_address[0],
&BX_CIRRUS_THIS pci_conf[0x10],
0x2000000)) {
BX_INFO(("new pci_memaddr: 0x%04x", BX_CIRRUS_THIS pci_memaddr));
BX_INFO(("new pci_memaddr: 0x%04x", BX_CIRRUS_THIS pci_base_address[0]));
}
if (DEV_pci_set_base_mem(BX_CIRRUS_THIS_PTR, cirrus_mem_read_handler,
cirrus_mem_write_handler,
&BX_CIRRUS_THIS pci_mmioaddr,
&BX_CIRRUS_THIS pci_base_address[1],
&BX_CIRRUS_THIS pci_conf[0x14],
CIRRUS_PNPMMIO_SIZE)) {
BX_INFO(("new pci_mmioaddr = 0x%08x", BX_CIRRUS_THIS pci_mmioaddr));
BX_INFO(("new pci_mmioaddr = 0x%08x", BX_CIRRUS_THIS pci_base_address[1]));
}
}
#endif
@ -567,8 +567,8 @@ Bit8u bx_svga_cirrus_c::mem_read(bx_phy_address addr)
#if BX_SUPPORT_PCI
if (BX_CIRRUS_THIS pci_enabled) {
if ((addr >= BX_CIRRUS_THIS pci_memaddr) &&
(addr < (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE))) {
if ((addr >= BX_CIRRUS_THIS pci_base_address[0]) &&
(addr < (BX_CIRRUS_THIS pci_base_address[0] + CIRRUS_PNPMEM_SIZE))) {
Bit8u *ptr;
Bit32u offset = addr & (BX_CIRRUS_THIS s.memsize - 1);
@ -599,8 +599,8 @@ Bit8u bx_svga_cirrus_c::mem_read(bx_phy_address addr)
}
offset &= (BX_CIRRUS_THIS s.memsize - 1);
return *(ptr + offset);
} else if ((addr >= BX_CIRRUS_THIS pci_mmioaddr) &&
(addr < (BX_CIRRUS_THIS pci_mmioaddr + CIRRUS_PNPMMIO_SIZE))) {
} else if ((addr >= BX_CIRRUS_THIS pci_base_address[1]) &&
(addr < (BX_CIRRUS_THIS pci_base_address[1] + CIRRUS_PNPMMIO_SIZE))) {
Bit32u offset = addr & (CIRRUS_PNPMMIO_SIZE - 1);
if (offset >= 0x100) {
@ -694,8 +694,8 @@ void bx_svga_cirrus_c::mem_write(bx_phy_address addr, Bit8u value)
#if BX_SUPPORT_PCI
if (BX_CIRRUS_THIS pci_enabled) {
if ((addr >= BX_CIRRUS_THIS pci_memaddr) &&
(addr < (BX_CIRRUS_THIS pci_memaddr + CIRRUS_PNPMEM_SIZE))) {
if ((addr >= BX_CIRRUS_THIS pci_base_address[0]) &&
(addr < (BX_CIRRUS_THIS pci_base_address[0] + CIRRUS_PNPMEM_SIZE))) {
Bit32u offset = addr & (BX_CIRRUS_THIS s.memsize - 1);
if ((offset >= (BX_CIRRUS_THIS s.memsize - 256)) &&
@ -734,8 +734,8 @@ void bx_svga_cirrus_c::mem_write(bx_phy_address addr, Bit8u value)
SET_TILE_UPDATED(((offset % BX_CIRRUS_THIS svga_pitch) / (BX_CIRRUS_THIS svga_bpp / 8)) / X_TILESIZE,
(offset / BX_CIRRUS_THIS svga_pitch) / Y_TILESIZE, 1);
return;
} else if ((addr >= BX_CIRRUS_THIS pci_mmioaddr) &&
(addr < (BX_CIRRUS_THIS pci_mmioaddr + CIRRUS_PNPMMIO_SIZE))) {
} else if ((addr >= BX_CIRRUS_THIS pci_base_address[1]) &&
(addr < (BX_CIRRUS_THIS pci_base_address[1] + CIRRUS_PNPMMIO_SIZE))) {
// memory-mapped I/O.
// BX_DEBUG(("write mmio 0x%08x",addr));
@ -2346,8 +2346,8 @@ void bx_svga_cirrus_c::svga_init_pcihandlers(void)
BX_CIRRUS_THIS pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
BX_CIRRUS_THIS pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
BX_CIRRUS_THIS pci_memaddr = 0;
BX_CIRRUS_THIS pci_mmioaddr = 0;
BX_CIRRUS_THIS pci_base_address[0] = 0;
BX_CIRRUS_THIS pci_base_address[1] = 0;
}
Bit32u bx_svga_cirrus_c::pci_read_handler(Bit8u address, unsigned io_len)
@ -2423,19 +2423,19 @@ void bx_svga_cirrus_c::pci_write_handler(Bit8u address, Bit32u value, unsigned i
if (baseaddr0_change) {
if (DEV_pci_set_base_mem(BX_CIRRUS_THIS_PTR, cirrus_mem_read_handler,
cirrus_mem_write_handler,
&BX_CIRRUS_THIS pci_memaddr,
&BX_CIRRUS_THIS pci_base_address[0],
&BX_CIRRUS_THIS pci_conf[0x10],
0x2000000)) {
BX_INFO(("new pci_memaddr: 0x%04x", BX_CIRRUS_THIS pci_memaddr));
BX_INFO(("new pci_memaddr: 0x%04x", BX_CIRRUS_THIS pci_base_address[0]));
}
}
if (baseaddr1_change) {
if (DEV_pci_set_base_mem(BX_CIRRUS_THIS_PTR, cirrus_mem_read_handler,
cirrus_mem_write_handler,
&BX_CIRRUS_THIS pci_mmioaddr,
&BX_CIRRUS_THIS pci_base_address[1],
&BX_CIRRUS_THIS pci_conf[0x14],
CIRRUS_PNPMMIO_SIZE)) {
BX_INFO(("new pci_mmioaddr = 0x%08x", BX_CIRRUS_THIS pci_mmioaddr));
BX_INFO(("new pci_mmioaddr = 0x%08x", BX_CIRRUS_THIS pci_base_address[1]));
}
}
}

3
bochs/iodev/svga_cirrus.h
View File

@ -263,9 +263,6 @@ private:
BX_CIRRUS_SMF bx_bool cirrus_mem_read_handler(bx_phy_address addr, unsigned len, void *data, void *param);
BX_CIRRUS_SMF bx_bool cirrus_mem_write_handler(bx_phy_address addr, unsigned len, void *data, void *param);
Bit32u pci_memaddr;
Bit32u pci_mmioaddr;
#endif
};

14
bochs/iodev/usb_ohci.cc
View File

@ -127,7 +127,7 @@ void bx_usb_ohci_c::init(void)
for (i=0; i<256; i++)
BX_OHCI_THIS pci_conf[i] = 0x0;
BX_OHCI_THIS hub.base_addr = 0x0;
BX_OHCI_THIS pci_base_address[0] = 0x0;
BX_OHCI_THIS hub.ohci_done_count = 7;
BX_OHCI_THIS hub.use_control_head = 0;
BX_OHCI_THIS hub.use_bulk_head = 0;
@ -441,10 +441,10 @@ void bx_usb_ohci_c::register_state(void)
void bx_usb_ohci_c::after_restore_state(void)
{
if (DEV_pci_set_base_mem(BX_OHCI_THIS_PTR, read_handler, write_handler,
&BX_OHCI_THIS hub.base_addr,
&BX_OHCI_THIS pci_base_address[0],
&BX_OHCI_THIS pci_conf[0x10],
4096)) {
BX_INFO(("new base address: 0x%04x", BX_OHCI_THIS hub.base_addr));
BX_INFO(("new base address: 0x%04x", BX_OHCI_THIS pci_base_address[0]));
}
for (int j=0; j<BX_N_USB_OHCI_PORTS; j++) {
if (BX_OHCI_THIS hub.usb_port[j].device != NULL) {
@ -520,7 +520,7 @@ bx_bool bx_usb_ohci_c::read_handler(bx_phy_address addr, unsigned len, void *dat
return 1;
}
Bit32u offset = (Bit32u)(addr - BX_OHCI_THIS hub.base_addr);
Bit32u offset = (Bit32u)(addr - BX_OHCI_THIS pci_base_address[0]);
switch (offset) {
case 0x00: // HcRevision
val = BX_OHCI_THIS hub.op_regs.HcRevision;
@ -690,7 +690,7 @@ bx_bool bx_usb_ohci_c::read_handler(bx_phy_address addr, unsigned len, void *dat
bx_bool bx_usb_ohci_c::write_handler(bx_phy_address addr, unsigned len, void *data, void *param)
{
Bit32u value = *((Bit32u *) data);
Bit32u offset = (Bit32u)addr - BX_OHCI_THIS hub.base_addr;
Bit32u offset = (Bit32u)addr - BX_OHCI_THIS pci_base_address[0];
int p, org_state;
int name = offset >> 2;
@ -1439,10 +1439,10 @@ void bx_usb_ohci_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_l
}
if (baseaddr_change) {
if (DEV_pci_set_base_mem(BX_OHCI_THIS_PTR, read_handler, write_handler,
&BX_OHCI_THIS hub.base_addr,
&BX_OHCI_THIS pci_base_address[0],
&BX_OHCI_THIS pci_conf[0x10],
4096)) {
BX_INFO(("new base address: 0x%04x", BX_OHCI_THIS hub.base_addr));
BX_INFO(("new base address: 0x%04x", BX_OHCI_THIS pci_base_address[0]));
}
}

2
bochs/iodev/usb_ohci.h
View File

@ -136,8 +136,6 @@ struct OHCI_ISO_TD {
typedef struct {
Bit32u base_addr;
int frame_index;
int interval_index;

14
bochs/iodev/usb_uhci.cc
View File

@ -105,7 +105,7 @@ void bx_usb_uhci_c::init(void)
BX_UHCI_THIS pci_conf[i] = 0x0;
}
BX_UHCI_THIS hub.base_ioaddr = 0x0;
BX_UHCI_THIS pci_base_address[4] = 0x0;
//FIXME: for now, we want a status bar // hub zero, port zero
BX_UHCI_THIS hub.statusbar_id = bx_gui->register_statusitem("UHCI");
@ -283,11 +283,11 @@ void bx_usb_uhci_c::register_state(void)
void bx_usb_uhci_c::after_restore_state(void)
{
if (DEV_pci_set_base_io(BX_UHCI_THIS_PTR, read_handler, write_handler,
&BX_UHCI_THIS hub.base_ioaddr,
&BX_UHCI_THIS pci_base_address[4],
&BX_UHCI_THIS pci_conf[0x20],
32, &uhci_iomask[0], "USB UHCI Hub"))
{
BX_INFO(("new base address: 0x%04x", BX_UHCI_THIS hub.base_ioaddr));
BX_INFO(("new base address: 0x%04x", BX_UHCI_THIS pci_base_address[4]));
}
for (int j=0; j<BX_N_USB_UHCI_PORTS; j++) {
if (BX_UHCI_THIS hub.usb_port[j].device != NULL) {
@ -354,7 +354,7 @@ Bit32u bx_usb_uhci_c::read(Bit32u address, unsigned io_len)
Bit32u val = 0x0;
Bit8u offset,port;
offset = address - BX_UHCI_THIS hub.base_ioaddr;
offset = address - BX_UHCI_THIS pci_base_address[4];
switch (offset) {
case 0x00: // command register (16-bit)
@ -452,7 +452,7 @@ void bx_usb_uhci_c::write(Bit32u address, Bit32u value, unsigned io_len)
BX_DEBUG(("register write to address 0x%04X: 0x%08X (%2i bits)", (unsigned) address, (unsigned) value, io_len * 8));
offset = address - BX_UHCI_THIS hub.base_ioaddr;
offset = address - BX_UHCI_THIS pci_base_address[4];
switch (offset) {
case 0x00: // command register (16-bit) (R/W)
@ -1038,10 +1038,10 @@ void bx_usb_uhci_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_l
}
if (baseaddr_change) {
if (DEV_pci_set_base_io(BX_UHCI_THIS_PTR, read_handler, write_handler,
&BX_UHCI_THIS hub.base_ioaddr,
&BX_UHCI_THIS pci_base_address[4],
&BX_UHCI_THIS pci_conf[0x20],
32, &uhci_iomask[0], "USB UHCI Hub")) {
BX_INFO(("new base address: 0x%04x", BX_UHCI_THIS hub.base_ioaddr));
BX_INFO(("new base address: 0x%04x", BX_UHCI_THIS pci_base_address[4]));
}
}

1
bochs/iodev/usb_uhci.h
View File

@ -32,7 +32,6 @@
// defined in bochs.h: UHCI supports 2 ports per root hub
typedef struct {
Bit32u base_ioaddr;
int timer_index;
// Registers