Speed up memory access by devices
This commit is contained in:
Stanislav Shwartsman
parent
ed4be45a8b
commit
11b564b2f0
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: memory.cc,v 1.66 2008-05-01 20:46:00 sshwarts Exp $
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// $Id: memory.cc,v 1.67 2008-05-02 23:18:51 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -144,62 +144,71 @@ mem_write:
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data_ptr = (Bit8u *) data + (len - 1);
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#endif
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write_one:
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if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff))
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{
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// addr *not* in range 000A0000 .. 000FFFFF
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*(BX_MEM_THIS get_vector(a20addr)) = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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while(1) {
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// addr *not* in range 000A0000 .. 000FFFFF
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*(BX_MEM_THIS get_vector(a20addr)) = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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if (len == 1) return;
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len--;
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a20addr++;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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}
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}
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// addr must be in range 000A0000 .. 000FFFFF
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for(unsigned i=0; i<len; i++) {
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// SMMRAM
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if (a20addr <= 0x000bffff) {
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// devices are not allowed to access SMMRAM under VGA memory
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if (cpu) {
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*(BX_MEM_THIS get_vector(a20addr)) = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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}
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goto inc_one;
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}
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// adapter ROM C0000 .. DFFFF
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// ROM BIOS memory E0000 .. FFFFF
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#if BX_SUPPORT_PCI == 0
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// ignore write to ROM
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#else
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// Write Based on 440fx Programming
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if (BX_MEM_THIS pci_enabled && ((a20addr & 0xfffc0000) == 0x000c0000))
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{
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switch (DEV_pci_wr_memtype(a20addr)) {
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case 0x1: // Writes to ShadowRAM
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BX_DEBUG(("Writing to ShadowRAM: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
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*(BX_MEM_THIS get_vector(a20addr)) = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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break;
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case 0x0: // Writes to ROM, Inhibit
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BX_DEBUG(("Write to ROM ignored: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
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break;
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default:
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BX_PANIC(("writePhysicalPage: default case"));
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}
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}
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#endif
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inc_one:
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if (len == 1) return;
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len--;
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a20addr++;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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goto write_one;
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}
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// addr must be in range 000A0000 .. 000FFFFF
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// SMMRAM
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if (a20addr <= 0x000bffff) {
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// devices are not allowed to access SMMRAM under VGA memory
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if (cpu) {
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*(BX_MEM_THIS get_vector(a20addr)) = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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}
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goto inc_one;
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}
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// adapter ROM C0000 .. DFFFF
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// ROM BIOS memory E0000 .. FFFFF
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#if BX_SUPPORT_PCI == 0
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// ignore write to ROM
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#else
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// Write Based on 440fx Programming
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if (BX_MEM_THIS pci_enabled && ((a20addr & 0xfffc0000) == 0x000c0000))
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{
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switch (DEV_pci_wr_memtype(a20addr)) {
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case 0x1: // Writes to ShadowRAM
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BX_DEBUG(("Writing to ShadowRAM: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
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*(BX_MEM_THIS get_vector(a20addr)) = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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goto inc_one;
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case 0x0: // Writes to ROM, Inhibit
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BX_DEBUG(("Write to ROM ignored: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
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goto inc_one;
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default:
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BX_PANIC(("writePhysicalPage: default case"));
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goto inc_one;
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}
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}
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#endif
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goto inc_one;
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}
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else {
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// access outside limits of physical memory, ignore
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@ -295,65 +304,74 @@ mem_read:
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data_ptr = (Bit8u *) data + (len - 1);
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#endif
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read_one:
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if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff))
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{
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// addr *not* in range 00080000 .. 000FFFFF
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*data_ptr = *(BX_MEM_THIS get_vector(a20addr));
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while(1) {
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// addr *not* in range 00080000 .. 000FFFFF
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*data_ptr = *(BX_MEM_THIS get_vector(a20addr));
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if (len == 1) return;
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len--;
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a20addr++;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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}
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}
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// addr must be in range 000A0000 .. 000FFFFF
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for (unsigned i=0; i<len; i++) {
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// SMMRAM
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if (a20addr <= 0x000bffff) {
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// devices are not allowed to access SMMRAM under VGA memory
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if (cpu) *data_ptr = *(BX_MEM_THIS get_vector(a20addr));
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goto inc_one;
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}
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#if BX_SUPPORT_PCI
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if (BX_MEM_THIS pci_enabled && ((a20addr & 0xfffc0000) == 0x000c0000))
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{
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switch (DEV_pci_rd_memtype(a20addr)) {
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case 0x0: // Read from ROM
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if ((a20addr & 0xfffe0000) == 0x000e0000) {
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*data_ptr = BX_MEM_THIS rom[a20addr & BIOS_MASK];
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}
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else {
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*data_ptr = BX_MEM_THIS rom[(a20addr & EXROM_MASK) + BIOSROMSZ];
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}
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break;
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case 0x1: // Read from ShadowRAM
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*data_ptr = *(BX_MEM_THIS get_vector(a20addr));
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break;
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default:
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BX_PANIC(("readPhysicalPage: default case"));
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}
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}
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else
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#endif // #if BX_SUPPORT_PCI
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{
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if ((a20addr & 0xfffc0000) != 0x000c0000) {
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*data_ptr = *(BX_MEM_THIS get_vector(a20addr));
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}
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else if ((a20addr & 0xfffe0000) == 0x000e0000) {
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*data_ptr = BX_MEM_THIS rom[a20addr & BIOS_MASK];
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}
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else {
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*data_ptr = BX_MEM_THIS rom[(a20addr & EXROM_MASK) + BIOSROMSZ];
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}
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}
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inc_one:
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if (len == 1) return;
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len--;
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a20addr++;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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goto read_one;
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}
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// addr must be in range 000A0000 .. 000FFFFF
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// SMMRAM
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if (a20addr <= 0x000bffff) {
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// devices are not allowed to access SMMRAM under VGA memory
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if (cpu) *data_ptr = *(BX_MEM_THIS get_vector(a20addr));
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goto inc_one;
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}
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#if BX_SUPPORT_PCI
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if (BX_MEM_THIS pci_enabled && ((a20addr & 0xfffc0000) == 0x000c0000))
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{
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switch (DEV_pci_rd_memtype(a20addr)) {
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case 0x0: // Read from ROM
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if ((a20addr & 0xfffe0000) == 0x000e0000) {
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*data_ptr = BX_MEM_THIS rom[a20addr & BIOS_MASK];
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}
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else {
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*data_ptr = BX_MEM_THIS rom[(a20addr & EXROM_MASK) + BIOSROMSZ];
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}
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goto inc_one;
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case 0x1: // Read from ShadowRAM
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*data_ptr = *(BX_MEM_THIS get_vector(a20addr));
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goto inc_one;
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default:
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BX_PANIC(("readPhysicalPage: default case"));
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}
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goto inc_one;
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}
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else
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#endif // #if BX_SUPPORT_PCI
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{
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if ((a20addr & 0xfffc0000) != 0x000c0000) {
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*data_ptr = *(BX_MEM_THIS get_vector(a20addr));
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}
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else if ((a20addr & 0xfffe0000) == 0x000e0000) {
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*data_ptr = BX_MEM_THIS rom[a20addr & BIOS_MASK];
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}
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else {
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*data_ptr = BX_MEM_THIS rom[(a20addr & EXROM_MASK) + BIOSROMSZ];
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}
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goto inc_one;
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}
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}
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else
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